SFQ-based pulse conservation logic gate

Abstract

Josephson junction-based logic devices and methods of using the same are described. An example of a logic device based on a Josephson junction includes a dual input OR / AND (or / and) (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide a single flux quantum (SFQ) pulse. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate also includes a second plurality of inductors coupled between the second input node and one of the first or second output node. The OA2 gate also includes a Josephson junction coupled between the common node and one of: the first or second input node, or the first or second output node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application No. 17 / 815,368, filed on July 27, 2022, the contents of which are incorporated herein by reference.

[0003] Public domain

[0004] The present application relates to superconducting circuits. Specifically, the present application discloses various logic devices based on Josephson junctions and methods of using the same. Background Art

[0005] Superconducting digital systems are capable of performing computing operations at clock speeds exceeding 100 GHz. In these systems, the circuits include superconducting wires and Josephson junctions that together form a superconducting loop in which information in the form of single flux magnetic quanta (SFQ) is encoded and stored.

[0006] Superconducting circuits can be configured to implement traditional logic gates, such as AND gates, OR gates, flip-flops, etc. These gates can in turn be configured to implement more complex logic, such as shift registers, counters, processors, and the like.

[0007] SFQ pulse-based logic devices work by passing, storing, creating, and removing pulses. Over time, the scalability and combinatorial behavior of various logic families have been improved (i.e. RSFQ, QFP, RQL), but efficiency of logic gate implementation remains a challenge. Inversion is particularly expensive compared to CMOS. Summary of the invention

[0008] The present disclosure solves the inversion problem of SFQ logic and, more generally, 1) recreates all functions of the standard CMOS gate library using pulse-conserving gates and dual-rail data encoding. For completeness, the present disclosure describes gate implementations of 2) a D-latch device configured to eliminate signal jitter and 3) a single-ended to dual-rail data conversion device configured to be implemented without a transformer.

[0009] In a first aspect, a Josephson junction-based logic device is provided. The Josephson junction-based logic device includes a dual-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first input source and the second input source are configured to provide a single flux quantum (SFQ) pulse. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The OA2 gate also includes a second plurality of inductors coupled between the second input node and one of the following: the first output node or the second output node. The OA2 gate also includes a plurality of Josephson junctions. Each Josephson junction is coupled between a common node and one of the following: the first input node, the second input node, the first output node, or the second output node.

[0010] In a second aspect, a logic device based on a Josephson junction is provided. The logic device based on the Josephson junction includes a three-input OR / MAJ / AND (OR / MAjority decision / AND) (OMA3) gate. The OMA3 gate includes a first input node inductively coupled to a first input source, a second input node inductively coupled to a second input source, and a third input node inductively coupled to a third input source. The first input source, the second input source, and the third input source are configured to provide a single flux quantum (SFQ) pulse. The OMA3 gate also includes a first plurality of inductors coupled between the first input node and one of the following: a first output node, a second output node, or a third output node; a second plurality of inductors coupled between the second input node and one of the following: a first output node, a second output node, or a third output node; and a third plurality of inductors coupled between the third input node and one of the following: a first output node, a second output node, or a third output node. The OMA3 gate also includes a plurality of Josephson junctions. Each Josephson junction is coupled between the common node and one of: a first input node, a second input node, a third input node, a first output node, a second output node, or a third output node.

[0011] In a third aspect, a method is provided. The method includes providing a single flux quantum (SFQ) based input to a first input source and a second input source of a Josephson junction-based logic device. The Josephson junction-based logic device includes a first input node inductively coupled to the first input source and a second input node inductively coupled to the second input source. The Josephson junction-based logic device also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The Josephson junction-based logic device also includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The Josephson junction-based logic device also includes a plurality of Josephson junctions. Each Josephson junction is coupled between a common node and one of the following: a first input node, a second input node, a first output node, or a second output node. The method also includes providing an OR2 output at a first output node in response to the input. The OR2 output is the result of a logical OR function based on the input, and providing an AND2 output at a second output node. The AND2 output is configured to provide the result of a logical AND function based on the input. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above as well as additional features will be better understood from the following illustrative and non-limiting detailed description of example embodiments with reference to the accompanying drawings.

[0013] Figure 1 A block diagram of a Josephson junction based two-input OR / AND (OA2) gate is shown according to an example embodiment.

[0014] Figure 2A A circuit schematic diagram of a Josephson junction based two-input OR / AND (OA2) gate according to an example embodiment is shown.

[0015] Figure 2B A circuit schematic diagram of a Josephson junction based two-input OR / AND (OA2) gate according to an example embodiment is shown.

[0016] Figure 3A A schematic logic block diagram showing an arrangement of OA2 gates according to an example embodiment is shown.

[0017] Figure 3B A schematic logic block diagram showing an arrangement of OA2 gates according to an example embodiment is shown.

[0018] Figure 3C According to an example embodiment, Figure 3A Table of possible Boolean logic functions for the arrangement of OA2 gates.

[0019] Figure 4A A dual-rail waveform is shown according to an example embodiment.

[0020] Figure 4B A dual-rail waveform is shown according to an example embodiment.

[0021] Figure 5 A block diagram of a Josephson junction based three-input OR / MAJ / AND (OMA3) gate is shown according to an example embodiment.

[0022] Fig. 6A A circuit diagram of a Josephson junction based three-input OR / MAJ / AND (OMA3) gate is shown according to an example embodiment.

[0023] Figure 6B According to an example embodiment, Fig. 6A The waveform diagram of the OMA3 gate.

[0024] Fig. 7A A schematic logical block diagram showing an arrangement of an OMA3 gate according to an example embodiment is shown.

[0025] Figure 7B A schematic logic block diagram showing an arrangement of OMA3 gates and OA2 gates according to an example embodiment is shown.

[0026] Figure 7C A schematic logic block diagram showing an arrangement of OMA3 gates and OA2 gates according to an example embodiment is shown.

[0027] Fig.7D A schematic logic block diagram showing an arrangement of OMA3 gates and OA2 gates according to an example embodiment is shown.

[0028] Fig. 7E A table showing possible logic functions and outputs corresponding to an arrangement of OMA3 gates according to an example embodiment is shown.

[0029] Figure 8 A schematic logic block diagram showing an arrangement of OA2 gates according to an example embodiment is shown.

[0030] Fig. 9 A circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown.

[0031] Fig.10 The corresponding Fig. 9 A waveform diagram of the operation of the circuit.

[0032] Fig.11 A circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown.

[0033] Fig. 12AA circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown.

[0034] Fig. 12B A circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown.

[0035] Fig. 12C A circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown.

[0036] Fig.13 A circuit diagram of a Josephson junction based circuit configured to convert a single-ended input into a gated dual-rail signal is shown according to an example embodiment.

[0037] Fig.14 A schematic logic diagram of a Josephson junction based circuit configured to remove jitter from return-to-zero (RZ) data is shown according to an example embodiment.

[0038] Fig.15 The corresponding Fig.14 A waveform diagram of the operation of the circuit.

[0039] Fig.16 A method according to an example embodiment is shown.

[0040] Fig.17 A method according to an example embodiment is shown.

[0041] All figures are schematic, not necessarily to scale, and generally show only parts which are necessary for elucidating the example embodiments, wherein other parts may be omitted or merely suggested. DETAILED DESCRIPTION

[0042] Various examples of systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as an example is not necessarily to be construed as being superior to any other embodiment, implementation, and / or feature unless so stated. Therefore, other embodiments, implementations, and / or features may be utilized, and other changes may be made, without departing from the scope of the subject matter presented herein.

[0043] Therefore, the examples described herein are not meant to be limiting.It will be readily understood that the various aspects of the present disclosure as generally described herein and shown in the accompanying drawings may be arranged, substituted, combined, separated and designed in a variety of different configurations.

[0044] In addition, unless the context suggests otherwise, the features shown in each of the figures may be used in combination with each other. Therefore, the figures should generally be viewed as forming aspects of one or more overall embodiments, and it should be understood that not all of the features shown are necessary for each embodiment.

[0045] In addition, any listing of elements, blocks or steps in this specification or claims is for clarity. Therefore, such listing should not be interpreted as requiring or implying that these elements, blocks or steps follow a specific arrangement or are performed in a specific order.

[0046] Additionally, terms such as “substantially” or “approximately” that may be used herein mean that the characteristics, parameters or values ​​described need not be achieved precisely, but rather deviations or variations (including, for example, tolerances, measurement errors, measurement precision limitations and other factors known to those skilled in the art) may occur in an amount that does not exclude the effect that the characteristic is intended to provide.

[0047] Furthermore, terms such as "A is coupled to B," "A is electrically coupled to B," and the like do not necessarily mean that items A and B are directly coupled to each other. For example, a first component electrically coupled to a second component is interpreted to mean that the components are coupled to each other directly (e.g., via conductors) or via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0048] As described above, a superconducting circuit includes a superconducting wire and a Josephson junction, which together form a superconducting loop in which information in the form of a single flux magnetic quantum (SFQ) is encoded and stored. Examples of AC-powered single flux quantum (AC-SFQ) superconducting circuits correspond to reciprocal quantum logic (RQL) circuits and quantum flux parameter (QFP) circuits, in which both power and clock are provided by multi-phase alternating current signals.

[0049] Superconducting wires are formed from materials that are able to carry direct current (DC) in the absence of an electric field. Such materials have almost zero resistance at or below their critical temperature. An example superconductor, niobium, has a critical temperature (Tc) of 9.3 Kelvin. At temperatures below this critical temperature, niobium is superconducting. However, at temperatures above the critical temperature, niobium behaves like a normal metal with electrical resistance.

[0050] A Josephson junction comprises two superconductors coupled by a region that impedes the flow of current. Examples of such regions include or correspond to physical narrowing of the superconductors themselves, metallic regions, or thin insulating barriers. Some examples of Josephson junctions include niobium superconductors and an Al2O3 barrier between them. When the potential difference between the two superconductors is integrated with respect to time over a phase change period, the magnetic flux through the loop varies by an integer multiple of the single quantum flux. The voltage pulse associated with the single quantum flux corresponds to the SFQ pulse mentioned above. For example, an overdamped Josephson junction can produce individual SFQ pulses. In an AC-SFQ circuit, each Josephson junction can be part of one or more superconducting loops. The phase difference across the junction can be modulated by the magnetic flux applied to the loop.

[0051] The present disclosure relates to SFQ-based pulse-conserving logic gates that have an equal number of outputs as inputs and convert the inputs into thermometer code. The dual-input implementation is described as an improvement over conventional designs and generalized to entirely new gates with multiple outputs. When dual-rail data encoding is used, these gates can efficiently implement all standard logic functions. XOR and full adder implementations are particularly efficient. The present disclosure solves the "inversion problem" of pulse-based SFQ logic. These gates avoid physically large components such as transformers and can therefore use 400M JJ / cm at a clock rate of 30GHz. 2 , with 12 levels of logic per pipeline stage. These performance metrics achieve compute density comparable to leading-node CMOS.

[0052] Example of a Josephson junction based logic device

[0053] This disclosure describes a library of SFQ gates built from several logic primitives: Josephson transmission line (JTL), OA2 gate, and OMA3 gate. In some examples, LC shunt junctions can be used to create a resonant clock power network. The logic is AC powered, which means that the gates pass positive and negative SFQ pulses in opposite halves of the clock cycle.

[0054] Advantages over conventional implementations include elimination of transformers and elimination of auxiliary inductors connecting the output nodes to each other or to ground. This is achieved by directly flux biasing the interconnecting inductors.

[0055] Figure 1 A block diagram of a Josephson junction based two-input OR / AND (OA2) gate 100 is shown according to an example embodiment. The OA2 gate 100 includes a first input node 110 inductively coupled to a first input source 120. The OA2 gate 100 also includes a second input node 112 inductively coupled to a second input source 122. The first input source 120 and the second input source 122 are configured to provide a single flux quantum (SFQ) pulse 102.

[0056] The OA2 gate 100 also includes a first plurality of inductors 130 coupled between the first input node 110 and one of: the first output node 140 or the second output node 142 .

[0057] The OA2 gate 100 also includes a second plurality of inductors 132 coupled between the second input node 112 and one of: the first output node 140 or the second output node 142 .

[0058] The OA2 gate 100 also includes a plurality of Josephson junctions 150. Each of the plurality of Josephson junctions 150 is coupled between a common node (eg, ground) and one of the first input node 110, the second input node 112, the first output node 140, or the second output node 142.

[0059] In an example embodiment, the first output node 140 may be configured to provide an OR2 output 160. In such a scenario, the OR2 output 160 is configured to provide a result of a logical OR function based on the signals provided by the first input source 120 and the second input source 122.

[0060] In another example, the second output node 142 may be configured to provide an AND2 output 162. In this scenario, the AND2 output 162 is configured to provide a result of a logical AND function based on the signals provided by the first input source 120 and the second input source 122.

[0061] In some embodiments, OA2 gate 100 may be configured to generate a generated pulse at each output node (eg, first output node 140 and second output node 142 ) in response to each input pulse provided at an input node (eg, first input node 110 and second input node 112 ).

[0062] In various examples, the first plurality of inductors 130 can be biased with a flux bias equal to half SFQ. However, it will be appreciated that other flux bias values ​​are possible and contemplated.

[0063] In some embodiments, the OA2 gate 100 may additionally or alternatively include a global clock input 180 configured to provide a global clock signal 182. In such a scenario, the Josephson junction-based OA2 gate 100 may be configured to operate based on the global clock signal 182. As an example embodiment, the global clock signal 182 has a clock frequency of at least 30 GHz.

[0064] In some examples, the OA2 gate 100 can include a flux bias initialization system 170, which can be configured to initialize one or more inductors with a flux bias. The bias initialization system 170 can include one or more current sources configured to provide current to one or more primary inductors, which can be inductively coupled to one or more secondary loops of the OMA3 gate.

[0065] In the exemplary embodiment, the inputs and outputs of the OA2 gate 100 are generally connected to other gates via JTLs (not shown for clarity). All Josephson junctions are AC powered either directly or through leakage from adjacent junctions (not shown for clarity). In the exemplary embodiments, all inputs are inductively coupled to all outputs.

[0066] In some examples, flux bias applied to the interconnect inductor can preferentially bias the output without interfering with the input and without the need for additional interconnects. After a positive SFQ at the input generates a positive event at the OR2 output, the preferential bias moves to AND2 by adding flux in the inductive loop. In such a scenario, a subsequent positive input will generate a positive output on AND2. Alternatively, a subsequent negative input will generate a negative output on OR2.

[0067] Figure 2A A circuit schematic diagram of a Josephson junction based two-input OR / AND (OA2) gate 200 according to an example embodiment is shown. In this scenario, the flux bias applied to the first plurality of inductors 130 is equal to half SFQ.

[0068] Figure 2B A circuit schematic diagram of a Josephson junction based dual input OR / AND (OA2) gate 220 according to an example embodiment is shown. In some examples, the first plurality of inductors 130 may include a first pair of inductors 222 coupled in parallel between the first input node 110 and the first output node 140 and a second pair of inductors 224 coupled in parallel between the first input node 110 and the second output node 142. In this scenario, full SFQ may be applied to one of the two parallel inductors of the first pair of inductors 222 and the second pair of inductors 224.

[0069] Figure 3A A schematic logic block diagram of an arrangement 300 of OA2 gates (OA2 gates 100a, 100b, 100c, and 100d) according to an example embodiment is shown. As an example, a logic block may include a plurality of OA2 gates coupled together in a logic block, the plurality of OA2 gates being configured to accept two dual-rail inputs and provide a plurality of logic outputs, including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

[0070] As an example embodiment, dual-rail data encoding of arrangement 300 applied to OA2 gates may produce OR2, NOR2, AND2, and NAND2 logic functions in a single stage, and XOR2 and XNOR2 in two stages.

[0071] Figure 3B A schematic logic block diagram of an arrangement 320 of OA2 gates according to an example embodiment is shown. In an example, dual-rail data encoding applied to the arrangement 320 of OA2 gates may produce XOR2 and XNOR2 in two stages and have different intermediate values ​​compared to the arrangement 300.

[0072] Figure 3C According to an example embodiment, Figure 3A Table 330 of possible Boolean logic functions for the OA2 gate arrangement 300. The JTL, OA2, and OMA3 gates described herein are all pulse conserving, meaning that each input pulse produces one output pulse. In addition, these gates have degenerate inputs, meaning that the inputs are indistinguishable—only the total number of inputs that are high or low is important. Degenerate two-input logic functions are Figure 3C For each logic function, the number of inputs that must be high (true) to produce a true output is given. The "input code" numbers the logic function accordingly.

[0073] Tie Low and Tie High are trivial functions corresponding to constant outputs that do not use input values. The remaining two-input logic functions are generated using dual-rail data encoding and OA2 gates 100.

[0074] Figure 4A A dual rail waveform 400 is shown according to an example embodiment. The present dual rail data encoding technique is energy efficient because while the dual rail waveforms may jitter from low to high every clock cycle, they may also remain in a low or high state for any number of clock cycles, thereby minimizing transitions. In some implementations, both rails may indicate a low state in an inactive circuit.

[0075] Figure 4B A dual rail waveform 420 is shown in accordance with an example embodiment. Waveform 400 and waveform 420 have different numbers of transitions, but are logically equivalent in that logically valid states are read during the positive half clock cycle.

[0076] Figure 5 A block diagram of a Josephson junction based three-input OR / MAJ / AND (OMA3) gate 500 is shown according to an example embodiment. In an example, the OMA3 gate 500 can be configured to generate logical OR3, MAJ3, and AND3 based on three inputs.

[0077] In an example embodiment, the OMA3 gate 500 includes a first input node 510 inductively coupled to a first input source 520, a second input node 512 inductively coupled to a second input source 522, and a third input node 514 inductively coupled to a third input source 524. In such a scenario, the first input source 520, the second input source 522, and the third input source 524 are configured to provide single flux quantum (SFQ) pulses.

[0078] The OMA3 gate 500 also includes a first plurality of inductors 530 coupled between the first input node 510 and one of: the first output node 540, the second output node 542, or the third output node 544. The OMA3 gate 500 also includes a second plurality of inductors 532 coupled between the second input node 512 and one of: the first output node 540, the second output node 542, or the third output node 544. The OMA3 gate 500 also includes a third plurality of inductors 534 coupled between the first input node 514 and one of: the first output node 540, the second output node 542, or the third output node 544.

[0079] The OMA3 gate 500 further includes a plurality of Josephson junctions 550. Each of the plurality of Josephson junctions 550 is coupled between a common node (e.g., ground) and one of the following: the first input node 510, the second input node 512, the third input node 514, the first output node 540, or the second output node 542 or the third output node 544.

[0080] In an example embodiment, the first output node 540 may provide an OR3 output 560. In this scenario, the OR3 output 560 is configured to provide a result of a logical OR function based on the signals provided by the first input source 520, the second input source 522, and the third input source 524.

[0081] In some examples, the second output node 542 can provide a MAJ3 output 562. In this scenario, the MAJ3 output 562 is configured to provide a result of a logical majority function based on the signals provided by the first input source 520, the second input source 522, and the third input source 524.

[0082] In various other embodiments, the third output node 544 can provide an AND3 output 564. The AND3 output 564 is configured to provide a result of a logical AND function based on the signals provided by the first input source 520, the second input source 522, and the third input source 524.

[0083] In some examples, OMA3 gate 500 can be configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0084] In various embodiments, the OMA3 gate 500 may include a global clock input 580 configured to provide a global clock signal 582. In such a scenario, a Josephson junction-based logic device may be configured to operate based on the global clock signal 582. Furthermore, in some examples, the global clock signal 582 may have a clock frequency of at least 30 GHz.

[0085] In some examples, the OMA3 gate 500 can include a flux bias initialization system 570, which can be configured to initialize one or more inductors with a flux bias. The bias initialization system 570 can include one or more current sources configured to provide current to one or more primary inductors, which can be inductively coupled to one or more secondary loops of the OMA3 gate.

[0086] Fig. 6A A circuit diagram of a three-input OR / MAJ / AND (OMA3) gate 600 based on a Josephson junction according to an example embodiment is shown. In various examples, the inputs and outputs are generally connected to other gates via JTL (not shown for clarity). In addition, in some embodiments, the Josephson junction is AC powered directly or through leakage from an adjacent junction (not shown for clarity). In various examples, the input inductively coupled to all outputs. In addition, a flux bias can preferentially bias the output without interfering with the input and without the need for additional interconnection. In one embodiment, after a positive SFQ at an input produces a positive event at the OR3 output, the preferential bias is rotated forward to the MAJ3 output by adding flux in the inductive loop. In addition, a subsequent positive input will produce a positive output on MAJ3 and rotate the preferential bias to AND3. In addition, a negative input produces a negative output and rotates the preferential bias in the opposite direction.

[0087] In various example embodiments, at least a portion of the first plurality of inductors 530 (e.g., inductor 602 and inductor 606) are biased with a flux bias equal to one full SFQ. In such scenarios, some of the first plurality of inductors 530 (e.g., inductor 604) may be configured to be unbiased. It will be appreciated that the flux bias may be applied to other inductors in at least some of the first plurality of inductors 530, the second plurality of inductors 532, and / or the third plurality of inductors 534.

[0088] Figure 6B According to an example embodiment, Fig. 6AWaveform diagram 620 of OMA3 gate 600. In some embodiments, a positive polarity SFQ event results in a positive transition in the junction phase, while a negative polarity event results in a negative transition. Each input SFQ pulse produces a corresponding output pulse. The positive and negative transitions occur in opposite halves of the clock cycle, but can be separated by any number of cycles.

[0089] Fig. 7A A schematic logic block diagram of an arrangement 700 of OMA3 gates (e.g., OMA3 gates 500a, 500b, 500c, and 500d) according to an example embodiment is shown. In some examples, the arrangement 700 may include a plurality of OMA3 gates coupled together in a logic block, the plurality of OMA3 gates being configured to accept three dual-rail inputs and provide a plurality of logic outputs, including: NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, and AND3. It will be appreciated that other logic functions are possible and contemplated within the scope of the present disclosure.

[0090] In an exemplary embodiment, various combinations of OA2 and OMA3 gates may be used (particularly with reference to Fig. 7A , 7B , 7C and 7D) to generate all standard three-input logic functions in one or two stages. Fig. 7A The MAJ3 function from the first stage and the XOR3 from the second stage produce the logic of a full adder, as shown in arrangement 700. Note that the OMA3 gate primitive in the second stage can never have three true inputs, allowing for a more efficient implementation.

[0091] Additionally or alternatively, various logic blocks may include various combinations of OMA3 and OA2 gates, such as Figure 7B , 7C In such scenarios, it is conceivable to use several non-standard logic functions, such as exclusive single input, XS, exclusive double input, XD, and exclusive equal input, XE.

[0092] Figure 7B A schematic logical block diagram of an arrangement 720 of an OMA3 gate (eg, OMA3 gate 500 ) and an OA2 gate (eg, OA2 gate 100 ) according to an example embodiment is shown.

[0093] Figure 7C A schematic logical block diagram of an arrangement 730 of an OMA3 gate (eg, OMA3 gate 500 ) and an OA2 gate (eg, OA2 gate 100 ) according to an example embodiment is shown.

[0094] Fig.7DA schematic logical block diagram of an arrangement 740 of an OMA3 gate (eg, OMA3 gate 500 ) and an OA2 gate (eg, OA2 gate 100 ) according to an example embodiment is shown.

[0095] Fig. 7E An arrangement 700 of an OMA3 door according to an example embodiment is shown (such as with reference to Fig. 7A Table 750 of possible Boolean logic functions for the arrangement shown and described above. The degenerate three-input logic function is Fig. 7E For each logic function, the number of inputs that must be high (true) to produce a true output is given. The "input code" numbers the logic function accordingly.

[0096] Tie Low and Tie High are trivial functions corresponding to constant outputs regardless of input value. The remaining three-input logic functions are generated using dual-rail data encoding, OA2 gate 100 and OMA3 gate 500.

[0097] It will be appreciated that four-input logic functions may be implemented in the various logic blocks contemplated herein. For example, Figure 8 A schematic logic block diagram of an arrangement 800 of eight OA2 gates according to an example embodiment is shown. In this example, the eight OA2 gates may be arranged in two stages and may perform logic functions of AND4, NAND4, OR4, NOR4, etc.

[0098] Several other auxiliary operations are possible and contemplated herein.For example, a first auxiliary operation includes conversion from a single-ended encoded signal to a dual-rail encoded signal, which involves logic inversion. Fig. 9 A circuit diagram of a Josephson junction based circuit 900 configured to provide gating logic inversion is shown according to an example embodiment.

[0099] The logic inversion is implemented as a polarity inversion to convert A to A', and then the logic inverter is gated with the signal S to produce the output !AS. Note that A and !AS are logically valid dual rail signals only when S is in the active state. Otherwise, both rails are logical "zero", producing an inactive logic cycle. It will be noted that in some embodiments, the Josephson junction based circuit 900 can be configured to provide gated logic inversion without the need for a transformer (e.g., involving changing magnetic flux and energy transfer between primary and secondary loops / coils to change AC voltage levels).

[0100] Fig.10 The corresponding Fig. 9 A waveform diagram 1000 of the operation of the circuit.

[0101] Fig.11A circuit diagram of a Josephson junction based circuit 1100 configured to provide polarity reversal according to an example embodiment is shown. It will be appreciated that other circuits configured to provide polarity reversal are possible and contemplated within the scope of the present disclosure.

[0102] Fig. 12A , 12B and 12C show circuit variations configured to provide a logic inversion function. Fig. 12A A circuit diagram of a Josephson junction based circuit 1200 configured to provide gating logic inversion according to an example embodiment is shown. In this scenario, a first loop 1202 may initially be biased with a flux bias equal to one full SFQ having a first polarity, and a second loop 1204 may initially be biased with a flux bias equal to one full SFQ and also having the first polarity.

[0103] In an example embodiment, the Josephson junction based circuit 1200 may include an input node 1206 inductively coupled to an input source 1208. In such a scenario, the input node 1206 may be inductively coupled to a common ground node through a first loop inductor 1210. The circuit 1200 may include an output node 1212 inductively coupled to the common ground node through a second loop inductor 1214. In some examples, the output node 1212 may be coupled to a gate source 1216 through a gate resistor 1219 and a gate inductor 1218. The circuit 1200 includes a bridge inductor 1201 coupled between the input node 1206 and the output node 1212.

[0104] The circuit 1200 also includes a first Josephson junction 1203 coupled between an input node 1206 and a common ground node. The circuit 1200 also includes a second Josephson junction 1205 coupled between an output node 1212 and a common ground node. In such a scenario, the Josephson junction-based circuit 1200 is configured to provide a gated logic inversion function at the output node 1212 relative to a logic input provided by the input source 1208.

[0105] Fig. 12B A circuit diagram of a Josephson junction based circuit 1220 configured to provide gating logic inversion according to an example embodiment is shown. In this scenario, loop 1222 may initially be biased with a flux bias equal to one full SFQ and of a given polarity.

[0106] Fig. 12C A circuit diagram of a Josephson junction based circuit configured to provide gating logic inversion according to an example embodiment is shown. In this scenario, loop 1232 may initially be biased with a flux bias equal to one full SFQ and of a given polarity.

[0107] Fig.13 A circuit diagram of a Josephson junction based circuit 1300 configured to convert a single-ended input into a gated dual-rail signal according to an example embodiment is shown. The single-ended to dual-rail converter can accept return-to-zero (RZ) data encoding on the input, which means that the input must transition low within a half cycle after each transition high. This produces RZ encoding on the output.

[0108] The second auxiliary operation involves removing unnecessary jitter from the waveform, thereby improving power efficiency. Fig.14 A schematic logic diagram of a Josephson junction based circuit 1400 configured to remove jitter from RZ data according to an example embodiment is shown. In some examples, an OR gate with non-standard phases of input and output can be used to remove jitter from a signal. In some examples, the Josephson junction based circuit 1400 includes an input node 1402, which is configured to receive an input signal 1404 from an input source 1406. The circuit 1400 also includes a Josephson junction transmission line 1408, which is configured to accept the input signal 1404 from the input source 1406 and provide a delayed signal 1410. In such a scenario, the delayed signal 1410 is a delayed 180° version of the input signal 1404.

[0109] Circuit 1400 also includes an OR2 gate 1412 that is configured to accept input signal 1404 and delayed signal 1410 and provide an output signal 1414 that includes a delayed 225° version of input signal 1404 and does not include signal jitter.

[0110] Optionally, the circuit 1400 may further include a Josephson junction transmission line 1416 coupled to the OR2 gate 1412 and configured to output an output signal 1414 .

[0111] Fig.15 The corresponding Fig.14 1500 is a waveform diagram of the operation of circuit 1400. Note that based solely on causality, de-jittering must require a delay of half a clock cycle. Otherwise, the desired behavior would require knowledge of signal transitions half a cycle in the future.

[0112] Example Method

[0113] Fig.16 1600 according to an example embodiment is shown. It will be understood that method 1600 may include fewer or more steps or blocks than are explicitly shown or otherwise disclosed herein. Furthermore, the various steps or blocks of method 1600 may be performed in any order, and each step or block may be performed one or more times. In some embodiments, some or all blocks or steps of method 1600 may involve Figure 1 and Figure 5OA2 door 100 and / or OMA3 door 500 are shown and described.

[0114] Block 1602 includes providing single flux quantum (SFQ) based inputs to a first input source (e.g., first input source 120) and a second input source (e.g., second input source 122) of a Josephson junction based logic device (e.g., OA2 gate 100). In this scenario, the Josephson junction based logic device includes a first input node (e.g., first input node 110) inductively coupled to the first input source and a second input node (e.g., second input node 112) inductively coupled to the second input source. The logic device also includes a first plurality of inductors (e.g., first plurality of inductors 130) coupled between the first input node and one of the following: a first output node (e.g., first output node 140) or a second output node (e.g., second output node 142). The logic device also includes a second plurality of inductors (e.g., second plurality of inductors 132) coupled between the second input node and one of the following: the first output node or the second output node. The logic device includes a plurality of Josephson junctions (e.g., a plurality of Josephson junctions 150). In this scenario, each Josephson junction of the plurality of Josephson junctions may be coupled between a common node (eg, ground) and one of: a first input node, a second input node, a first output node, or a second output node.

[0115] Block 1604 includes providing an OR2 output (e.g., OR2 output 160) at a first output node in response to the input. In this scenario, the OR2 output is the result of a logical OR function based on the input. Additionally, block 1604 includes providing an AND2 output (e.g., AND2 output 162) at a second output node in response to the input. In such a scenario, the AND2 output is configured to provide the result of a logical AND function based on the input.

[0116] In some example embodiments, method 1600 may include providing an initialization signal to generate a desired flux bias in the first plurality of inductors while cooling the Josephson junction-based logic device. In such a scenario, method 1600 may also include, when a superconducting critical temperature of the Josephson junction-based logic device is reached, turning off the initialization signal so that the desired flux bias persists in the first plurality of inductors.

[0117] Fig.17 1700 according to an example embodiment is shown. It will be understood that method 1700 may include fewer or more steps or blocks than are explicitly shown or otherwise disclosed herein. Furthermore, the various steps or blocks of method 1700 may be performed in any order, and each step or block may be performed one or more times. In some embodiments, some or all blocks or steps of method 1700 may involve Figure 1 and Figure 5 OA2 door 100 and / or OMA3 door 500 are shown and described.

[0118] Method 1700 involves initializing a flux bias of one or more inductors of a plurality of inductors in a Josephson junction based logic device (e.g., OA2 gate 100 and / or OMA3 gate 500). In some embodiments, one or more primary sensors may be inductively coupled to one or more secondary loops configured to present at least a portion of a magnetic flux quantum. In some embodiments, method 1700 may be performed to initialize a flux bias in one or more secondary loops in a given logic device.

[0119] As an example, method 1700 may be performed at least in part by flux bias initialization system 170 and / or flux bias initialization system 570 .

[0120] Block 1702 includes applying a negative polarity current to the primary inductor such that approximately one magnetic flux quantum is induced in the secondary loop.

[0121] Block 1704 includes cooling the circuit to below the superconductor transition temperature of the secondary loop.The secondary loop will be initialized to a low energy, low flux state.

[0122] Block 1706 includes shutting off the current to the primary inductor to subtract exactly one negative flux quantum from the zero flux state, thereby producing a quantum accurate flux quantum in the secondary loop.

[0123] Upon initialization, various logic functions and operations may be performed by the logic devices described herein.

[0124] Listed Example Embodiments

[0125] Embodiments of the present disclosure may thus be directed to one of the Enumerated Example Embodiments (EEE) listed below.

[0126] EEE 1 includes Josephson junction based logic devices, including:

[0127] A two-input OR / AND (OA2) gate, wherein the OA2 gate comprises:

[0128] a first input node inductively coupled to a first input source;

[0129] a second input node inductively coupled to a second input source, wherein the first input source and the second input source are configured to provide single flux quantum (SFQ) pulses;

[0130] a first plurality of inductors coupled between the first input node and one of the first output node or the second output node;

[0131] a second plurality of inductors coupled between the second input node and one of the first output node or the second output node; and

[0132] A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a first output node, or a second output node.

[0133] EEE 2 comprises the Josephson junction based logic device of EEE 1, wherein the first output node comprises an OR2 output, wherein the OR2 output is configured to provide a result of a logical OR function based on signals provided by the first input source and the second input source.

[0134] EEE 3 comprises the Josephson junction based logic device of EEE 1, wherein the second output node comprises an AND2 output, wherein the AND2 output is configured to provide a result of a logical AND function based on signals provided by the first input source and the second input source.

[0135] EEE 3 includes the Josephson junction based logic device of EEE 1, wherein the Josephson junction based logic device is configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0136] EEE 5 comprises the Josephson junction based logic device of EEE 1, wherein the first plurality of inductors are biased with a flux bias equal to half the SFQ.

[0137] EEE 6 includes the Josephson junction based logic device of EEE 1, wherein the first plurality of inductors includes:

[0138] a first pair of inductors coupled in parallel between the first input node and the first output node; and

[0139] A second pair of inductors is coupled in parallel between the first input node and the second output node.

[0140] EEE 7 includes the Josephson junction based logic device of EEE 6, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to a full SFQ.

[0141] EEE 8 includes the Josephson junction based logic device of EEE 1, the Josephson junction based logic device further including a global clock input configured to provide a global clock signal, wherein the Josephson junction based logic device is configured to operate based on the global clock signal.

[0142] EEE 9 includes the Josephson junction based logic device of EEE 8, wherein the global clock signal has a clock frequency of at least 30 GHz.

[0143] EEE 10 includes the Josephson junction based logic device of EEE 1, which further includes a plurality of OA2 gates coupled together in a logic block, the plurality of OA2 gates being configured to accept two dual-rail inputs and provide a plurality of logic outputs including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

[0144] EEE 11 covers logic devices based on Josephson junctions, including:

[0145] A three-input OR / MAJ / AND (OMA3) gate, wherein the OMA3 gate comprises:

[0146] a first input node inductively coupled to a first input source;

[0147] a second input node inductively coupled to a second input source;

[0148] a third input node inductively coupled to a third input source, wherein the first input source, the second input source, and the third input source are configured to provide single flux quantum (SFQ) pulses;

[0149] a first plurality of inductors coupled between the first input node and one of: a first output node, a second output node, or a third output node;

[0150] a second plurality of inductors coupled between the second input node and one of: the first output node, the second output node, or a third output node;

[0151] a third plurality of inductors coupled between the third input node and one of: the first output node, the second output node, or a third output node; and

[0152] A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a third input node, a first output node, a second output node, or a third output node.

[0153] EEE 12 includes the Josephson junction based logic device of EEE 11, wherein the first output node includes an OR3 output, wherein the OR3 output is configured to provide a result of a logical OR function based on signals provided by the first input source, the second input source, and the third input source.

[0154] EEE 13 comprises the Josephson junction based logic device of EEE 11, wherein the second output node comprises a MAJ3 output, wherein the MAJ3 output is configured to provide a result of a logical majority decision function based on signals provided by the first input source, the second input source, and the third input source.

[0155] EEE 14 comprises the Josephson junction based logic device of EEE 11, wherein the third output node comprises an AND3 output, wherein the AND3 output is configured to provide a result of a logical AND function based on signals provided by the first input source, the second input source, and the third input source.

[0156] The EEE 15 includes the Josephson junction based logic device of the EEE 11, wherein the Josephson junction based logic device is configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0157] EEE 16 comprises the Josephson junction based logic device of EEE 11, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to a full SFQ.

[0158] EEE 17 includes the Josephson junction based logic device of EEE 11, the Josephson junction based logic device further including a global clock input configured to provide a global clock signal, wherein the Josephson junction based logic device is configured to operate based on the global clock signal, wherein the global clock signal has a clock frequency of at least 30 GHz.

[0159] EEE 18 includes the Josephson junction based logic device of EEE 11, which further includes a plurality of OMA3 gates coupled together in a logic block, the plurality of OMA3 gates being configured to accept three dual-rail inputs and provide a plurality of logic outputs including NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3 and AND3.

[0160] EEE 19 includes a method comprising:

[0161] Providing a single flux quantum (SFQ) based input to a first input source and a second input source of a Josephson junction based logic device, wherein the Josephson junction based logic device comprises:

[0162] a first input node inductively coupled to the first input source;

[0163] a second input node inductively coupled to the second input source;

[0164] a first plurality of inductors coupled between the first input node and one of: a first output node or a second output node;

[0165] a second plurality of inductors coupled between the second input node and one of: the first output node or the second output node; and

[0166] a plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a first output node, or a second output node; and

[0167] In response to the input, an OR2 output is provided at the first output node, wherein the OR2 output is a result of a road-based OR function based on the input, and an AND2 output is provided at the second output node, wherein the AND2 output is configured to provide a result of a logical AND function based on the input.

[0168] EEE 20 includes the method of EEE 19, the method further comprising:

[0169] providing an initialization signal to generate a desired flux bias in at least a portion of the first plurality of inductors while cooling the Josephson junction-based logic device; and

[0170] When the superconducting critical temperature of the Josephson junction-based logic device is reached, the initialization signal is turned off so that a desired flux bias persists in the first plurality of inductors.

[0171] EEE 21 includes a method comprising:

[0172] Providing single flux quantum (SFQ) based inputs to a first input source, a second input source, and a third input source of a Josephson junction based logic device, wherein the Josephson junction based logic device comprises:

[0173] a first input node inductively coupled to a first input source;

[0174] a second input node inductively coupled to a second input source;

[0175] a third input node inductively coupled to a third input source, wherein the first input source, the second input source, and the third input source are configured to provide single flux quantum (SFQ) pulses;

[0176] a first plurality of inductors coupled between the first input node and one of: a first output node, a second output node, or a third output node;

[0177] a second plurality of inductors coupled between the second input node and one of: the first output node, the second output node, or a third output node;

[0178] a third plurality of inductors coupled between the third input node and one of: the first output node, the second output node, or a third output node; and

[0179] a plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a third input node, a first output node, a second output node, or a third output node; and

[0180] In response to the input, an OR3 output is provided at the first output node, wherein the OR3 output is a result of a logical OR function based on the input, a MAJ3 output is provided at the second output node, wherein the MAJ3 output is configured to provide a result of a logical MAJ function based on the input, and an AND3 output is provided at the third output node, wherein the AND3 output is configured to provide a result of a logical AND function based on the input.

[0181] EEE 22 includes the method of EEE 21, the method further comprising:

[0182] providing an initialization signal to generate a desired flux bias in at least a portion of the first plurality of inductors while cooling the Josephson junction-based logic device; and

[0183] When the superconducting critical temperature of the Josephson junction-based logic device is reached, the initialization signal is turned off so that a desired flux bias persists in the first plurality of inductors.

[0184] EEE 23 includes an arrangement of logic gates based on Josephson junctions, wherein the arrangement includes:

[0185] A plurality of Josephson junction based logic devices, wherein each logic device of the plurality of Josephson junction based logic devices comprises at least two inputs, is configured to accept a single flux quantum (SFQ) input pulse, and is configured to provide a logic function output via at least two outputs in response to each input pulse.

[0186] EEE 24 includes an arrangement of logic gates of EEE 23, wherein the plurality of Josephson junction based logic devices include at least two dual-input OR / AND (OA2) gates, wherein the OA2 gates include:

[0187] a first input node inductively coupled to a first input source;

[0188] a second input node inductively coupled to a second input source, wherein the first input source and the second input source are configured to provide single flux quantum (SFQ) pulses;

[0189] a first plurality of inductors coupled between the first input node and one of: a first output node or a second output node;

[0190] a second plurality of inductors coupled between the second input node and one of: the first output node or the second output node; and

[0191] A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a first output node, or a second output node.

[0192] EEE 25 comprises an arrangement of logic gates of EEE 23, wherein the plurality of Josephson junction based logic devices comprises at least two three-input OR / MAJ / AND (OMA3) gates, wherein the OMA3 gates comprise:

[0193] a first input node inductively coupled to a first input source;

[0194] a second input node inductively coupled to a second input source;

[0195] a third input node inductively coupled to a third input source, wherein the first input source, the second input source, and the third input source are configured to provide single flux quantum (SFQ) pulses;

[0196] a first plurality of inductors coupled between the first input node and one of: a first output node, a second output node, or a third output node;

[0197] a second plurality of inductors coupled between the second input node and one of: the first output node, the second output node, or a third output node;

[0198] a third plurality of inductors coupled between the third input node and one of: the first output node, the second output node, or a third output node; and

[0199] A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first input node, a second input node, a third input node, a first output node, a second output node, or a third output node.

[0200] EEE 26 includes an arrangement of logic gates of EEE 23, wherein the plurality of Josephson junction based logic devices include at least two two-input OR / AND (OA2) gates and two three-input OR / MAJ / AND (OMA3) gates, wherein the OA2 gates include:

[0201] a first OA2 input node inductively coupled to a first OA2 input source;

[0202] a second OA2 input node inductively coupled to a second OA2 input source, wherein the first OA2 input source and the second OA2 input source are configured to provide single flux quantum (SFQ) pulses;

[0203] a first plurality of OA2 inductors coupled between the first OA2 input node and one of: a first OA2 output node or a second OA2 output node;

[0204] a second plurality of OA2 inductors coupled between the second OA2 input node and one of: the first OA2 output node or the second OA2 output node; and

[0205] a plurality of OA2 Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: a first OA2 input node, a second OA2 input node, a first OA2 output node, or a second OA2 output node, and wherein the OMA3 gate comprises:

[0206] a first OMA3 input node inductively coupled to a first OMA3 input source;

[0207] a second OMA3 input node inductively coupled to a second OMA3 input source;

[0208] a third OMA3 input node inductively coupled to a third OMA3 input source, wherein the first OMA3 input source, the second OMA3 input source, and the third OMA3 input source are configured to provide single flux quantum (SFQ) pulses;

[0209] a first plurality of OMA3 inductors coupled between the first OMA3 input node and one of: a first OMA3 output node, a second OMA3 output node, or a third OMA3 output node;

[0210] a second plurality of OMA3 inductors coupled between the second OMA3 input node and one of: the first OMA3 output node, the second OMA3 output node, or a third OMA3 output node;

[0211] a third plurality of OMA3 inductors coupled between the third OMA3 input node and one of: the first OMA3 output node, the second OMA3 output node, or a third OMA3 output node; and

[0212] A plurality of OMA3 Josephson junctions, wherein each OMA3 Josephson junction is coupled between a common node and one of: a first OMA3 input node, a second OMA3 input node, a third OMA3 input node, a first OMA3 output node, a second OMA3 output node, or a third OMA3 output node.

[0213] EEE 27 includes an arrangement of logic gates of EEE 23, wherein the logic function output includes at least one of the following: OR2, NOR2, AND2, NAND2, XOR2, XNOR2, NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, or AND3.

[0214] EEE 28 includes a Josephson junction based logic device, the Josephson junction based logic device including:

[0215] an input node inductively coupled to an input source, wherein the input node is inductively coupled to a common ground node through a first loop inductor;

[0216] an output node inductively coupled to the common ground node through a second loop inductor, wherein the output node is coupled to a gate source through a gate resistor and a gate inductor;

[0217] a bridge inductor coupled between the input node and the output node;

[0218] a first Josephson junction coupled between the input node and the common ground node; and

[0219] A second Josephson junction is coupled between the output node and the common ground node, wherein the Josephson junction based logic device is configured to provide a gating logic inversion function at the output node relative to a logic input provided by the input source.

[0220] EEE 29 includes a gated single-ended to dual-rail converter based on the Josephson junction based logic device of EEE 28, wherein the single-ended to dual-rail converter is configured to accept a return-to-zero (RZ) input signal, wherein the single-ended to dual-rail converter is configured to output the RZ input signal and a gated component of the RZ input signal.

[0221] The EEE 30 includes a Josephson junction based logic device, the Josephson junction based logic device including:

[0222] an input node configured to receive an input signal from an input source;

[0223] a Josephson junction transmission line configured to accept an input signal from the input source and provide a delayed signal, wherein the delayed signal comprises a 180° delayed version of the input signal;

[0224] An OR2 gate configured to accept the input signal and the delayed signal and provide an output signal comprising a version of the input signal without signal jitter; and

[0225] An optional Josephson junction transmission line is coupled to the OR2 gate and configured to output the output signal.

[0226] Although some embodiments have been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be regarded as illustrative and not restrictive. Other variations of the disclosed embodiments may be understood and effected from a study of the drawings, the present disclosure, and the appended claims when implementing the claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A logic device based on a Josephson junction, comprising: A two-input OR / AND (OA2) gate, wherein the OA2 gate comprises: a first input node inductively coupled to a first input source; a second input node inductively coupled to a second input source, wherein the first input source and the second input source are configured to provide single flux quantum (SFQ) pulses; a first plurality of inductors coupled between the first input node and one of: a first output node or a second output node; a second plurality of inductors coupled between the second input node and one of: the first output node or the second output node; and A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: the first input node, the second input node, the first output node, or the second output node.

2. The Josephson junction based logic device of claim 1 , wherein the first output node comprises an OR2 output, wherein the OR2 output is configured to provide a result of a logical OR function based on signals provided by the first input source and the second input source, and the second output node comprises an AND2 output, wherein the AND2 output is configured to provide a result of a logical AND function based on signals provided by the first input source and the second input source.

3. The Josephson junction based logic device of claim 1, wherein the Josephson junction based logic device is configured to generate an output pulse at each output node in response to each input pulse provided at the input node.

4. The Josephson junction based logic device of claim 1, wherein the first plurality of inductors are biased with a flux bias equal to half the SFQ.

5. The Josephson junction based logic device of claim 1, wherein the first plurality of inductors comprises: a first pair of inductors coupled in parallel between the first input node and the first output node; as well as A second pair of inductors is coupled in parallel between the first input node and the second output node.

6. The Josephson junction based logic device of claim 5, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one full SFQ.

7. The Josephson junction based logic device of claim 1, further comprising a global clock input configured to provide a global clock signal, wherein the Josephson junction based logic device is configured to operate based on the global clock signal.

8. The Josephson junction based logic device of claim 7, wherein the global clock signal has a clock frequency of at least 30 GHz.

9. The Josephson junction based logic device of claim 1 , further comprising a plurality of OA2 gates coupled together in a logic block, the plurality of OA2 gates being configured to accept two dual-rail inputs and provide a plurality of logic outputs, including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

10. A logic device based on a Josephson junction, comprising: A three-input OR / MAJ / AND (OMA3) gate, wherein the OMA3 gate comprises: a first input node inductively coupled to a first input source; a second input node inductively coupled to a second input source; a third input node inductively coupled to a third input source, wherein the first input source, the second input source, and the third input source are configured to provide single flux quantum (SFQ) pulses; a first plurality of inductors coupled between the first input node and one of: a first output node, a second output node, or a third output node; a second plurality of inductors coupled between the second input node and one of: the first output node, the second output node, or the third output node; a third plurality of inductors coupled between the third input node and one of: the first output node, the second output node, or the third output node; and A plurality of Josephson junctions, wherein each Josephson junction is coupled between a common node and one of: the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node.

11. A Josephson junction based logic device as described in claim 10, wherein the first output node includes an OR3 output, wherein the OR3 output is configured to provide a result of a logical OR function based on the signals provided by the first input source, the second input source and the third input source, wherein the second output node includes a MAJ3 output, wherein the MAJ3 output is configured to provide a result of a logical majority decision function based on the signals provided by the first input source, the second input source and the third input source, wherein the third output node includes an AND3 output, wherein the AND3 output is configured to provide a result of a logical AND function based on the signals provided by the first input source, the second input source and the third input source.

12. The Josephson junction based logic device of claim 10, wherein the Josephson junction based logic device is configured to generate an output pulse at each output node in response to each input pulse provided at the input node.

13. The Josephson junction based logic device of claim 10, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one full SFQ.

14. The Josephson junction based logic device of claim 10, further comprising a global clock input configured to provide a global clock signal, wherein the Josephson junction based logic device is configured to operate based on the global clock signal, wherein the global clock signal has a clock frequency of at least 30 GHz.

15. The Josephson junction based logic device of claim 10, further comprising a plurality of OMA3 gates coupled together in a logic block, the plurality of OMA3 gates being configured to accept three dual rail inputs and provide a plurality of logic outputs, including NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, and AND3.

16. A method comprising: Providing a single flux quantum (SFQ) based input to a Josephson junction based logic device, wherein the Josephson junction based logic device comprises at least one of an OA2 gate or an OMA3 gate, wherein the OA2 gate comprises: a first OA2 input node inductively coupled to a first OA2 input source; a second OA2 input node inductively coupled to a second OA2 input source; a first plurality of OA2 inductors coupled between the first OA2 input node and one of: a first OA2 output node or a second OA2 output node; a second plurality of OA2 inductors coupled between the second OA2 input node and one of: the first OA2 output node or the second OA2 output node; and a plurality of OA2 Josephson junctions, wherein each OA2 Josephson junction is coupled between a common node and one of: the first OA2 input node, the second OA2 input node, the first OA2 output node, or the second OA2 output node, and wherein the OMA3 gate comprises: a first OMA3 input node inductively coupled to a first OMA3 input source; a second OMA3 input node inductively coupled to a second OMA3 input source; a third OMA3 input node inductively coupled to a third OMA3 input source, wherein the first OMA3 input source, the second OMA3 input source, and the third OMA3 input source are configured to provide single flux quantum (SFQ) pulses; a first plurality of OMA3 inductors coupled between the first OMA3 input node and one of: a first OMA3 output node, a second OMA3 output node, or a third OMA3 output node; a second plurality of OMA3 inductors coupled between the second OMA3 input node and one of: the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; a third plurality of OMA3 inductors coupled between the third OMA3 input node and one of: the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; and a plurality of OMA3 Josephson junctions, wherein each OMA3 Josephson junction is coupled between a common node and one of: the first OMA3 input node, the second OMA3 input node, the third OMA3 input node, the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; and In response to the input, a logic function is provided at an output node based on the input, wherein the logic function includes at least one of the following: OR2, NOR2, AND2, NAND2, XOR2, XNOR2, NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, or AND3.

17. The method of claim 16, further comprising: providing an initialization signal to generate a desired flux bias in at least a portion of the first plurality of inductors or the first plurality of OMA3 inductors while cooling the Josephson junction based logic device; as well as When a superconducting critical temperature of the Josephson junction-based logic device is reached, the initialization signal is turned off to allow the desired flux bias to persist in the first plurality of OA2 inductors or the first plurality of OMA3 inductors.

18. The method of claim 16, further comprising converting a single-ended encoded signal into a dual-rail encoded signal, wherein the conversion is performed by a SFQ-based gated logic inversion circuit, wherein the logic inversion circuit comprises a polarity inversion portion and a logic inversion portion.

19. The method of claim 18, wherein the SFQ-based input comprises the dual-track encoded signal.

20. The method of claim 18, further comprising removing jitter from at least a portion of the dual-rail data signal, wherein the removing is performed by a Josephson junction based circuit, wherein the Josephson junction based circuit comprises at least one Josephson junction transmission line, at least one delay element, and at least one OR2 gate.

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