High-throughput true random number generator based on MUX latch

Abstract

The invention discloses a high-throughput true random number generator based on MUX latches, which comprises an entropy source circuit, a sampling circuit and a post-processing circuit, and is characterized in that the entropy source circuit comprises two groups of MUX latch circuits, and each group of MUX latch circuits comprises i-level MUX latch units; the D flip-flop is used for sampling the output in each stage of MUX latch unit; the post-treatment consists of an exclusive or chain. According to the method, the jitter and the metastable state are extracted at the same time under low hardware overhead, the high throughput rate is output, and good randomness and robustness are achieved.

Description

Technical Field

[0001] The invention belongs to the field of hardware security, and in particular relates to a high-throughput true random number generator based on a MUX latch. Background Art

[0002] With the development of technologies such as the Internet of Things, the number of devices connected to the network and communicating with each other has increased significantly, making information security more critical than ever. Random number generators are crucial components for ensuring information security, including authentication protocols, cryptographic algorithms, and key management mechanisms. Generally speaking, according to the principle of data generation, random number generators can be divided into true random number generators (TRNG) and pseudo-random number generators (PRNG). Although PRNG is easy to implement, it is difficult to provide security due to its repeatability and predictability. TRNG is mainly used in the field of cryptography to meet the growing demand for information security. Generally, the entropy source of TRNG is generally generated by random physical phenomena in nature, such as jitter, metastable state, chaos, etc. Among them, jitter and metastable state are the most widely used entropy sources among many entropy sources.

[0003] In recent years, many scholars have conducted a lot of research on different entropy sources. For example, a novel entropy source circuit with dynamic reconfigurability (DrCRO) uses two types of entropy sources, including signal jitter and circuit metastable, to enhance the randomness of the circuit. A true random number generator using a latched XOR (LX) gate aims to improve the throughput of a TRNG based on a traditional ring oscillator by combining the effects of latch metastable and RO jitter. The latched ring oscillator (LRO) simultaneously utilizes the jitter of the RO and the metastable state of the latch, reducing hardware resource overhead. The above entropy sources all use jitter and metastable states to generate the required random numbers, solving the problem of the singleness of the entropy source, but all have the limitation of being unable to extract metastable states and jitter at the same time, resulting in low throughput and high resource overhead due to the serialization of the entropy source. Summary of the invention

[0004] In order to solve the problems of low throughput and high resource overhead caused by the serialization of entropy sources, the present invention proposes a high-throughput true random number generator based on a MUX latch, in order to achieve simultaneous extraction of jitter and metastable state with less hardware overhead, thereby outputting a higher throughput and making the generator have good randomness and robustness.

[0005] In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme:

[0006] The high-throughput true random number generator based on a MUX latch of the present invention is characterized in that it comprises: an entropy source circuit, a sampling circuit, and a post-processing circuit;

[0007] The entropy source circuit is composed of two groups of MUX latch circuits; wherein each group of MUX latch circuits is composed of J-level MUX latch units cascaded together, and any level of MUX latch unit is composed of a MUX selector, an XOR gate and a NAND gate;

[0008] One input end of the current-stage MUX selector is connected to the output end of the NAND gate in the next-stage MUX latch unit, and the other input end of the current-stage MUX selector is connected to the output end of the NAND gate of the current stage;

[0009] The selection port of the current-stage MUX selector is connected to the PLL phase-locked loop frequency division clock;

[0010] The output of the current-stage MUX selector is connected to an input of the current-stage NAND gate;

[0011] One input end of the XOR gate of the current-stage MUX latch unit is connected to the output end of the XOR gate of the previous-stage MUX latch unit, another input end of the XOR gate of the current-stage MUX latch unit is connected to the output end of the NAND gate of the current stage, and the output end of the XOR gate of the current-stage MUX latch unit is connected to one input end of the XOR gate of the next-stage MUX latch unit;

[0012] One input end of the NAND gate of the current-stage MUX latch unit is connected to the output end of the current-stage XOR gate, another input end of the NAND gate of the current-stage MUX latch unit is connected to the output end of the current-stage MUX selector, and the output end of the NAND gate of the current-stage MUX latch unit is connected to another input end of the current-stage XOR gate;

[0013] The sampling circuit uses a D flip-flop to sample the output of the XOR gate in each level of the MUX latch unit of each group of MUX latch circuits to obtain an output signal {DFF_out ij |i=1,2;j=1,2,…,J}; where DFF_out ij represents the output signal of the XOR gate in the j-th level MUX latch unit of the i-th group of MUX latch circuits; J represents the total number of MUX latch units;

[0014] The post-processing circuit outputs the signal {DFF_out ij |i=1,2;j=1,2,…,J} are XOR-post-processed to generate a true random number TRNG_OUT.

[0015] The true random number generator of the present invention is also characterized in that:

[0016] If the selection ports of all MUX selectors are logic "1", the entropy source circuit is equivalent to J XOR-NAND latch units, each of which consists of an XOR gate and a NAND gate;

[0017] One input end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to the output end of the XOR gate of the XOR-NAND latch unit of the previous stage, another input end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to the output end of the NAND gate of the XOR-NAND latch unit of the current stage, and the output end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to one input end of the XOR gate of the XOR-NAND latch unit of the next stage; one input end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to the output end of the XOR gate of the current stage, another input end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to the output end of the NAND gate of the XOR-NAND latch unit of the next stage, and the output end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to another input end of the XOR gate of the current stage;

[0018] If all the MUX selector selection ports are logic "0", the entropy source circuit is equivalent to J self-feedback units, each of which consists of an XOR gate and a self-feedback NAND gate;

[0019] One input end of the XOR gate of the current-stage self-feedback unit is connected to the output end of the XOR gate of the previous-stage self-feedback unit, another input end of the XOR gate of the current-stage self-feedback unit is connected to the output end of the NAND gate of the current-stage self-feedback unit, and the output end of the XOR gate of the current-stage self-feedback unit is connected to one input end of the XOR gate of the next-stage self-feedback unit; one input end of the NAND gate of the current-stage self-feedback unit is connected to the output end of the XOR gate of the current-stage self-feedback unit, another input end of the NAND gate of the current-stage self-feedback unit is connected to the output end of the NAND gate of the current-stage self-feedback unit, and the output end of the NAND gate of the current-stage self-feedback unit is connected to another input end of the XOR gate of the current-stage self-feedback unit.

[0020] Furthermore, the output end of each level of XOR gate and NAND gate in the J-level XOR-NAND latch unit is analyzed according to the following process:

[0021] When initially powered on, one input end of the XOR gate and the NAND gate in each level of the XOR-NAND latch unit is a random value;

[0022] If one input end of the XOR gate and one input end of the NAND gate of the i-th XOR-NAND latch unit are both logic 0, the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 1, the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 1 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1;

[0023] If one input end of the XOR gate and one input end of the NAND gate in the i-th XOR-NAND latch unit are logic 0 and logic 1 respectively, then the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 0 or 1, the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 1 or 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1 or 0;

[0024] If one input end of the XOR gate and one input end of the NAND gate of the i-th XOR-NAND latch unit are logic 1 and logic 0 respectively, then the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 1, and the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 0;

[0025] If one input end of the XOR gate and one input end of the NAND gate of the i-th level XOR-NAND latch unit are both logic 1, then the output end of the NAND gate in the i-th level XOR-NAND latch unit is logic 1 or logic 0, the output end of the XOR gate in the i-th level XOR-NAND latch unit is logic 0 or logic 1 and serves as the output value of the i-th level XOR-NAND latch unit, and the D flip-flop samples the logic 0 or logic 1.

[0026] Further: the output end of an XOR gate and a self-feedback NAND gate of each level in the J-level self-feedback unit is analyzed according to the following process:

[0027] When initially powered on, the input value at one input terminal of the XOR gate in each level of the self-feedback unit is a random value;

[0028] If one of the inputs of the XOR gate of the i-th self-feedback unit is logic 0:

[0029] When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 0, the output of the NAND gate of the i-th self-feedback unit is logic 1, the other input in the XOR gate of the i-th self-feedback unit is also logic 1, the output of the XOR gate in the i-th self-feedback unit is logic 1 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 1;

[0030] When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value in the NAND gate of the i-th self-feedback unit depends on the other input value in the NAND gate of the i-th self-feedback unit:

[0031] If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate of the i-th self-feedback unit is logic 1, the other input terminal of the XOR gate of the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate of the i-th self-feedback unit is logic 1 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 1;

[0032] If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 1, the output value of the NAND gate of the i-th self-feedback unit is logic 0, the other input terminal of the XOR gate of the i-th self-feedback unit is also logic 0, the output terminal of the XOR gate of the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0;

[0033] If one input terminal of the XOR gate of the i-th self-feedback unit is logic 1:

[0034] When one of the input terminals of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate in the i-th self-feedback unit is logic 1, the other input terminal of the XOR gate in the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate in the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0;

[0035] When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value of the NAND gate in the i-th self-feedback unit depends on the other input value in the NAND gate of the i-th self-feedback unit:

[0036] If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate in the i-th self-feedback unit is logic 1, and the other input terminal of the XOR gate in the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate in the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0;

[0037] If the other input terminal of the NAND gate of the i-th level self-feedback unit is logic 1, the output value of the NAND gate of the i-th level self-feedback unit is logic 0, the other input terminal of the XOR gate in the i-th level self-feedback unit is also logic 0, the output terminal of the XOR gate in the i-th level self-feedback unit is logic 1 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 1.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. The entropy source proposed in the present invention is not only a mixed entropy, but also a mixed entropy source that can output a compound metastable state and jitter at the same time. When the circuit operates in situation A, the values ​​sampled from the four operating states are steady-state values, random bit strings with jitter, or metastable values; when the circuit operates in situation B, the value sampled from the J-level self-feedback unit is a steady-state value or a metastable value; the D trigger samples the J-level XOR-NAND latch unit or the self-feedback unit, so it can generate random numbers by compounding metastable states and jitter, thereby increasing the diversity of the entropy source.

[0040] 2. The TRNG proposed in the present invention achieves a high throughput of 500Mbps. The entropy source is sampled using a D flip-flop with a sampling clock of CLK. The output random sequence is subjected to various randomness tests and passes the various randomness tests with higher indicators, thereby improving the randomness and throughput of the entropy source.

[0041] 3. There are two operating states of the circuit of the generator of the present invention, depending on the control of the MUX selection port. When the MUX selection ports are all logic 1, the J-level XOR-NAND latch unit has 4 different operating states; when the MUX selection ports are all logic 0, the J-level self-feedback unit has 2 different operating states, thereby further increasing the randomness and diversity of the entropy source. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is the overall architecture diagram of the true random number generator proposed by the present invention;

[0043] Figure 2 A group of MUX latch structure diagrams of the present invention;

[0044] Figure 3 It is the circuit model of the present invention when operating based on situation A;

[0045] Figure 4 It is the circuit model of the present invention when operating based on situation B;

[0046] Figure 5 The four state diagrams of XNL-cell when the present invention is running based on situation A are shown. DETAILED DESCRIPTION

[0047] In this embodiment, a high-throughput true random number generator based on a MUX latch is composed of two groups of MUX latch circuits, and each group of MUX latch circuits is formed by i-level MUX latch units cascaded mutually.

[0048] like Figure 1 As shown, the entropy source structure is two groups of MUX latch circuits, and the D flip-flop samples the outputs of the two groups of MUX latch circuits to obtain the final random sequence output TRNG_OUT;

[0049] like Figure 2 As shown, each group of MUX latch circuits is composed of i-level MUX latch units cascaded together, and the D flip-flop samples the output of each level of MUX latch unit to obtain the original random sequence output DFF_out ij , {i=1,2;j=1,2,3,4,5};

[0050] The selector determines whether the circuit operates in A or B. When the selector selection terminals are both logical "1", the circuit operates in A. Figure 3 As shown; when the selector selection ends are all logic "0", the circuit operation is B, such as Figure 4 shown.

[0051] In a specific implementation, each group of MUX latch circuits is composed of i-level MUX latch units, and each level of MUX latch unit is composed of a MUX selector, an XOR gate, and a NAND gate to form a latch structure.

[0052] The MUX is composed of selection statements, and the XOR gate and the NAND gate are both configured by the single-output dual-input lookup table LUT2.

[0053] According to the truth table, the initial value of the single-output dual-input NAND gate lookup table LUT2_NAND is set to 4'b0111, and the initial value of the single-output dual-input XOR gate lookup table LUT2_XOR is set to 4'b0110; the order of the first row of the lookup table from left to right is: LUT2_XOR-1, LUT2_XOR-2, LUT2_XOR-3, LUT2_XOR-4, LUT2_XOR-5; the order of the second row of the lookup table from left to right is: LUT2_NAND-1, LUT2_NAND-2, LUT2_NAND-3, LUT2_NAND-4, LUT2_NAND-5; the order of MUX from left to right is: MUX-1, MUX-2, MUX-3, MUX-4, MUX-5.

[0054] If the MUX selector selection ports are all logic "1", the circuit is equivalent to a J-level XOR-NAND latch unit. Each level of XOR-NAND latch unit has two input terminals, one of the input terminals of the XOR gate and one of the input terminals of the NAND gate, and two output terminals, the output terminal of the XOR gate and the output terminal of the NAND gate. Figure 3 shown.

[0055] When initially powered on, one input end of the XOR gate and the NAND gate in each level of the XOR-NAND latch unit is a random value;

[0056] If both input terminals of the i-th level XOR-NAND latch unit are logic 0, that is, one input terminal of the XOR gate and one input terminal of the NAND gate of the i-th level XOR-NAND latch unit are both logic 0, such as Figure 5 As shown in (a), since one of the input terminals of the NAND gate of the i-th XOR-NAND latch unit is logic 0, the output value of the NAND gate of the i-th XOR-NAND latch unit is logic 1, and since the output terminal of the NAND gate of the i-th XOR-NAND latch unit is connected to one of the input terminals of the XOR gate of the i-th XOR-NAND latch unit is logic 1, the output terminal of the XOR gate of the i-th XOR-NAND latch unit is logic 1 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1;

[0057] If the two input terminals of the i-th level XOR-NAND latch unit are logic 0 and logic 1 respectively, that is, one input terminal of the XOR gate and one input terminal of the NAND gate of the i-th level XOR-NAND latch unit are logic 0 and logic 1 respectively. Figure 5 As shown in (b), since one of the input terminals of the NAND gate of the i-th level XOR-NAND latch unit is logic 1, the output value of the NAND gate of the i-th level XOR-NAND latch unit depends on the other input value of the NAND gate of the i-th level XOR-NAND latch unit.

[0058] When the other input terminal of the NAND gate of the i-th XOR-NAND latch unit is logic 0:

[0059] Then the output end of the NAND gate of the i-th XOR-NAND latch unit is logic 1. Since the other input end of the XOR gate of the i-th XOR-NAND latch unit is connected to logic 1 by the output end of the NAND gate of the i-th XOR-NAND latch unit, the output value of the XOR gate of the i-th XOR-NAND latch unit is logic 1 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1.

[0060] When the other input terminal of the NAND gate of the i-th XOR-NAND latch unit is logic 1:

[0061] Then the output end of the NAND gate of the i-th level XOR-NAND latch unit is logic 0. Since the other input end of the XOR gate of the i-th level XOR-NAND latch unit is connected to logic 0 by the output end of the NAND gate of the i-th level XOR-NAND latch unit, the output value of the XOR gate of the i-th level XOR-NAND latch unit is logic 0, then the output value of the i-th level XOR-NAND latch unit is logic 0 and serves as the output value of the i-th level XOR-NAND latch unit, and the D flip-flop samples the logic 0.

[0062] If the two input terminals of the i-th level XOR-NAND latch unit are logic 1 and logic 0 respectively, that is, one input terminal of the XOR gate and one input terminal of the NAND gate of the i-th level XOR-NAND latch unit are logic 1 and logic 0 respectively. Figure 5 As shown in (c), since one of the input terminals of the NAND gate of the i-th XOR-NAND latch unit is logic 0, the output value of the NAND gate of the i-th XOR-NAND latch unit is logic 1, and since the output terminal of the NAND gate of the i-th XOR-NAND latch unit is connected to one of the input terminals of the XOR gate of the i-th XOR-NAND latch unit is logic 1, the output terminal of the XOR gate of the i-th XOR-NAND latch unit is logic 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 0;

[0063] If both input terminals of the i-th level XOR-NAND latch unit are logic 1, that is, one input terminal of the XOR gate and one input terminal of the NAND gate of the i-th level XOR-NAND latch unit are both logic 1. Figure 5 As shown in (d), since one of the input terminals of the NAND gate of the i-th XOR-NAND latch unit is logic 1, the output value of the NAND gate of the i-th XOR-NAND latch unit depends on the other input value of the NAND gate of the i-th XOR-NAND latch unit:

[0064] When the other input terminal of the NAND gate of the i-th XOR-NAND latch unit is logic 0:

[0065] Then the output terminal of the NAND gate of the i-th XOR-NAND latch unit is logic 1. Since the other input terminal of the XOR gate of the i-th XOR-NAND latch unit is connected to logic 1 by the output terminal of the NAND gate of the i-th XOR-NAND latch unit, the output terminal of the XOR gate of the i-th XOR-NAND latch unit is logic 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 0.

[0066] When the other input terminal of the NAND gate in the i-th level XOR-NAND latch unit is logic 1:

[0067] Then the output end of the NAND gate of the i-th XOR-NAND latch unit is logic 0. Since the other input end of the XOR gate of the i-th XOR-NAND latch unit is connected to logic 0 by the output end of the NAND gate of the i-th XOR-NAND latch unit, the output end of the XOR gate of the i-th XOR-NAND latch unit is logic 1 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1.

[0068] If the MUX selector selection ports are all logic "0", the circuit is equivalent to a J-level self-feedback unit. Each level of self-feedback unit has an input terminal, which is one of the input terminals of the XOR gate, and an output terminal, which is the output terminal of the XOR gate. Figure 4 shown.

[0069] When initially powered on, the input value at one input terminal of the XOR gate in each level of the self-feedback unit is a random value;

[0070] If the input terminal of the i-th self-feedback unit is logic 0, that is, one of the input terminals of the XOR gate of the self-feedback unit of this level is logic 0:

[0071] When one of the input terminals of the NAND gate of the i-th level self-feedback unit is logic 0, the output value of the NAND gate of the i-th level self-feedback unit is logic 1. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 1 by the output terminal of the NAND gate of the i-th level self-feedback unit, the output terminal of the XOR gate in the i-th level self-feedback unit is logic 1 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 1.

[0072] When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value in the NAND gate of the i-th self-feedback unit depends on the other input value in the NAND gate of the self-feedback unit of this level:

[0073] If the other input terminal of the NAND gate of the self-feedback unit of this level is logic 0, the output value of the NAND gate of the i-th level self-feedback unit is logic 1. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 1 by the output terminal of the NAND gate of the i-th level self-feedback unit, the output terminal of the XOR gate of the i-th level self-feedback unit is logic 1 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 1.

[0074] If the other input terminal of the NAND gate of the self-feedback unit of this level is logic 1, the output value of the NAND gate of the i-th level self-feedback unit is logic 0. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 0 by the output terminal of the NAND gate of the i-th level self-feedback unit, the other input terminal of the XOR gate of the i-th level self-feedback unit is logic 0, and the output terminal of the XOR gate of the i-th level self-feedback unit is logic 0 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 0.

[0075] If the input terminal of the i-th self-feedback unit is logic 1, that is, one of the input terminals of the XOR gate of the self-feedback unit of this level is logic 1:

[0076] When one of the input terminals of the NAND gate of the i-th level self-feedback unit is logic 0, the output value of the NAND gate in the i-th level self-feedback unit is logic 1. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 1 by the output terminal of the NAND gate of the i-th level self-feedback unit, the output terminal of the XOR gate of the i-th level self-feedback unit is logic 0 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 0.

[0077] When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value of the NAND gate in the i-th self-feedback unit depends on the other input value in the NAND gate of the self-feedback unit at this level:

[0078] If the other input terminal of the NAND gate of the self-feedback unit of this level is logic 0, the output value of the NAND gate in the i-th level self-feedback unit is logic 1. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 1 by the output terminal of the NAND gate of the i-th level self-feedback unit, the output terminal of the XOR gate in the i-th level self-feedback unit is logic 0 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 0.

[0079] If the other input terminal of the NAND gate of the self-feedback unit of this level is logic 1, the output value of the NAND gate of the i-th level self-feedback unit is logic 0. Since the other input terminal of the XOR gate of the i-th level self-feedback unit is connected to logic 0 by the output terminal of the NAND gate of the i-th level self-feedback unit, the output terminal of the XOR gate in the i-th level self-feedback unit is logic 1 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 1.

[0080] In this embodiment, a high-throughput true random number generator based on a MUX latch is generated according to the following steps:

[0081] Step 1: Build an entropy source circuit and set the clock input frequency of each D flip-flop in the sampling circuit to CLK;

[0082] Step 2: Set the frequency of the MUX selector selection end to S, and the circuit starts to oscillate;

[0083] Step 3: The external D flip-flop samples the output of each group of XOR gates in each stage in the above two cases to obtain the output signal DFF_out. ij , {i=1,2;j=1,2,3,4,5}; finally, the output signal DFF_out ij Through XOR post-processing, a high-speed true random number TRNG_OUT is generated.

[0084] Step 4: The final random sequence is subjected to various randomness tests.

[0085] The present invention can collect jitter and metastable state at the same time, solving the problems of low throughput and high resource consumption; various randomness tests were performed to verify the quality and performance of the present invention. The present invention has shown high efficiency in hardware resources, consuming only 33 lookup tables (LUTs) and 13 D flip-flops (DFFs) on the Kintex-7 and Artix-7 development boards to achieve a throughput of up to 500Mbps. In summary, the structure proposed in the present invention not only shows randomness and high robustness in actual circuits. This is of great significance in fields that require high-speed random numbers, such as cryptography and secure communications.

Claims

1. A high-throughput true random number generator based on a MUX latch, characterized in that: include: Entropy source circuit, sampling circuit, post-processing circuit; The entropy source circuit is composed of two groups of MUX latch circuits; wherein each group of MUX latch circuits is composed of J-level MUX latch units cascaded together, and any level of MUX latch unit is composed of a MUX selector, an XOR gate and a NAND gate; One input end of the current-stage MUX selector is connected to the output end of the NAND gate in the next-stage MUX latch unit, and the other input end of the current-stage MUX selector is connected to the output end of the NAND gate of the current stage; The selection port of the current-stage MUX selector is connected to the PLL phase-locked loop frequency division clock; The output of the current-stage MUX selector is connected to an input of the current-stage NAND gate; One input end of the XOR gate of the current-stage MUX latch unit is connected to the output end of the XOR gate of the previous-stage MUX latch unit, another input end of the XOR gate of the current-stage MUX latch unit is connected to the output end of the NAND gate of the current stage, and the output end of the XOR gate of the current-stage MUX latch unit is connected to one input end of the XOR gate of the next-stage MUX latch unit; One input end of the NAND gate of the current-stage MUX latch unit is connected to the output end of the current-stage XOR gate, another input end of the NAND gate of the current-stage MUX latch unit is connected to the output end of the current-stage MUX selector, and the output end of the NAND gate of the current-stage MUX latch unit is connected to another input end of the current-stage XOR gate; The sampling circuit uses a D flip-flop to sample the output of the XOR gate in each level of the MUX latch unit of each group of MUX latch circuits to obtain an output signal {DFF_out ij |i=1,2;j=1,2,…,J}; where DFF_out ij represents the output signal of the XOR gate in the j-th level MUX latch unit of the i-th group of MUX latch circuits; J represents the total number of MUX latch units; The post-processing circuit outputs the signal {DFF_out ij |i=1,2;j=1,2,…,J} are XOR-post-processed to generate a true random number TRNG_OUT.

2. The true random number generator according to claim 1, characterized in that: If the selection ports of all MUX selectors are logic "1", the entropy source circuit is equivalent to J XOR-NAND latch units, each of which consists of an XOR gate and a NAND gate; One input end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to the output end of the XOR gate of the XOR-NAND latch unit of the previous stage, another input end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to the output end of the NAND gate of the XOR-NAND latch unit of the current stage, and the output end of the XOR gate of the XOR-NAND latch unit of the current stage is connected to one input end of the XOR gate of the XOR-NAND latch unit of the next stage; one input end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to the output end of the XOR gate of the current stage, another input end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to the output end of the NAND gate of the XOR-NAND latch unit of the next stage, and the output end of the NAND gate of the XOR-NAND latch unit of the current stage is connected to another input end of the XOR gate of the current stage; If all the MUX selector selection ports are logic "0", the entropy source circuit is equivalent to J self-feedback units, each of which consists of an XOR gate and a self-feedback NAND gate; One input end of the XOR gate of the current-stage self-feedback unit is connected to the output end of the XOR gate of the previous-stage self-feedback unit, another input end of the XOR gate of the current-stage self-feedback unit is connected to the output end of the NAND gate of the current-stage self-feedback unit, and the output end of the XOR gate of the current-stage self-feedback unit is connected to one input end of the XOR gate of the next-stage self-feedback unit; one input end of the NAND gate of the current-stage self-feedback unit is connected to the output end of the XOR gate of the current-stage self-feedback unit, another input end of the NAND gate of the current-stage self-feedback unit is connected to the output end of the NAND gate of the current-stage self-feedback unit, and the output end of the NAND gate of the current-stage self-feedback unit is connected to another input end of the XOR gate of the current-stage self-feedback unit.

3. The true random number generator according to claim 2, characterized in that: The output of each level of XOR gate and NAND gate in the J-level XOR-NAND latch unit is analyzed according to the following process: When initially powered on, one input end of the XOR gate and the NAND gate in each level of the XOR-NAND latch unit is a random value; If one input end of the XOR gate and one input end of the NAND gate of the i-th XOR-NAND latch unit are both logic 0, the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 1, the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 1 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1; If one input end of the XOR gate and one input end of the NAND gate in the i-th XOR-NAND latch unit are logic 0 and logic 1 respectively, then the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 0 or 1, the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 1 or 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 1 or 0; If one input end of the XOR gate and one input end of the NAND gate of the i-th XOR-NAND latch unit are logic 1 and logic 0 respectively, then the output end of the NAND gate in the i-th XOR-NAND latch unit is logic 1, and the output end of the XOR gate in the i-th XOR-NAND latch unit is logic 0 and serves as the output value of the i-th XOR-NAND latch unit, and the D flip-flop samples the logic 0; If one input end of the XOR gate and one input end of the NAND gate of the i-th level XOR-NAND latch unit are both logic 1, then the output end of the NAND gate in the i-th level XOR-NAND latch unit is logic 1 or logic 0, the output end of the XOR gate in the i-th level XOR-NAND latch unit is logic 0 or logic 1 and serves as the output value of the i-th level XOR-NAND latch unit, and the D flip-flop samples the logic 0 or logic 1.

4. The true random number generator according to claim 2, characterized in that: The output of an XOR gate and a self-feedback NAND gate in each level of the J-level self-feedback unit is analyzed according to the following process: When initially powered on, the input value at one input terminal of the XOR gate in each level of the self-feedback unit is a random value; If one of the inputs of the XOR gate of the i-th self-feedback unit is logic 0: When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 0, the output of the NAND gate of the i-th self-feedback unit is logic 1, the other input in the XOR gate of the i-th self-feedback unit is also logic 1, the output of the XOR gate in the i-th self-feedback unit is logic 1 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 1; When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value in the NAND gate of the i-th self-feedback unit depends on the other input value in the NAND gate of the i-th self-feedback unit: If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate of the i-th self-feedback unit is logic 1, the other input terminal of the XOR gate of the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate of the i-th self-feedback unit is logic 1 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 1; If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 1, the output value of the NAND gate of the i-th self-feedback unit is logic 0, the other input terminal of the XOR gate of the i-th self-feedback unit is also logic 0, the output terminal of the XOR gate of the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0; If one input terminal of the XOR gate of the i-th self-feedback unit is logic 1: When one of the input terminals of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate in the i-th self-feedback unit is logic 1, the other input terminal of the XOR gate in the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate in the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0; When one of the inputs in the NAND gate of the i-th self-feedback unit is logic 1, the output value of the NAND gate in the i-th self-feedback unit depends on the other input value in the NAND gate of the i-th self-feedback unit: If the other input terminal of the NAND gate of the i-th self-feedback unit is logic 0, the output value of the NAND gate in the i-th self-feedback unit is logic 1, and the other input terminal of the XOR gate in the i-th self-feedback unit is also logic 1, the output terminal of the XOR gate in the i-th self-feedback unit is logic 0 and serves as the output value of the i-th self-feedback unit, and the D flip-flop samples the logic 0; If the other input terminal of the NAND gate of the i-th level self-feedback unit is logic 1, the output value of the NAND gate of the i-th level self-feedback unit is logic 0, the other input terminal of the XOR gate in the i-th level self-feedback unit is also logic 0, the output terminal of the XOR gate in the i-th level self-feedback unit is logic 1 and serves as the output value of the i-th level self-feedback unit, and the D flip-flop samples the logic 1.

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