Integrated circuit package including substrate coupled to glass core by interconnect

Abstract

Microelectronic assemblies and related devices and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including a conductive through glass via (TGV); a dielectric layer at a surface of the glass layer, the dielectric layer including a conductive via; and an interconnect between a surface of the glass layer and the dielectric layer, where the individual interconnect electrically couples the individual TGV to the individual conductive path. In some embodiments, the interconnect includes solder or liquid metal ink. In some embodiments, the interconnect includes a metal-metal bond and a dielectric-dielectric bond.

Description

Background Art

[0001] Electronic circuits are generally referred to as integrated circuits (ICs) when they are made onto wafers made of semiconductor materials (e.g., silicon). Wafers with such ICs are generally cut into a large number of individual dies. In multi-die IC packages, IC devices (e.g., dies) are generally coupled together to integrate features or functions and facilitate connection with other components (e.g., package substrates). IC packages may include embedded multi-die interconnect bridges (EMIBs) for coupling two or more dies. IC packages may be integrated into electronic systems (e.g., consumer electronic systems). Some ICs have specific functions, such as memory or processing. Some other ICs have multiple functions, such as systems on chip (SOCs), in which all or most of the components of a computer or other electronic system are integrated into a single monolithic die. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The various embodiments will be easily understood by considering the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are shown in the figures of the accompanying drawings by way of example and not by way of limitation.

[0003] Figure 1 is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0004] Figure 2A and Figure 2B is a schematic cross-sectional view of an enlarged portion of a microelectronic assembly according to some embodiments of the present disclosure.

[0005] Figure 3 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0006] Figure 4A is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0007] Figure 4B yes Figure 4A Schematic cross-sectional view of a portion of an exemplary microelectronic assembly.

[0008] Figures 5A-5D is a simplified cross-sectional view showing various fabrication steps of the core of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0009] Figures 6A-6E is a simplified cross-sectional view showing various fabrication steps of a substrate of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0010] Figures 7A-7Care simplified cross-sectional views showing various fabrication steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0011] Fig. 8A and Figure 8B is a simplified cross-sectional view showing various fabrication steps of the core of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0012] Figures 9A-9D is a simplified cross-sectional view showing various fabrication steps of a substrate of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0013] Fig. 10A and Fig. 10B are simplified cross-sectional views showing various fabrication steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0014] Fig.11 is a cross-sectional view of a device package that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0015] Fig.12 is a cross-sectional side view of a device assembly that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0016] Fig.13 is a block diagram of an exemplary computing device that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0017] For the purpose of illustrating the IC packaging described herein, it is important to understand the phenomena that occur during the assembly and packaging of the IC. The basic information below can be considered as the basis for properly interpreting the present disclosure. Such information is provided only for the purpose of explanation, and accordingly, it should not be regarded as limiting the broad scope of the present disclosure and its potential applications in some way.

[0018] Die segmentation, where multiple smaller dies are coupled together via high-density interconnects, can achieve smaller form factors and higher yields than using a single monolithic die. However, coupling dies together at the fine pitch required to achieve the desired interconnect density has been limited by conventional approaches. One approach to achieving finer pitches involves incorporating a thin glass core into the package substrate.

[0019] The structures and components disclosed herein may include a glass core (also referred to herein as a "glass layer") having vias extending through the glass core to achieve front-to-back connections between two different substrates. The glass core provides several advantages over conventional epoxy cores, including higher through-glass via (TGV) density, lower signal loss, and lower total thickness variation (TTV), among others. The substrate may include a dielectric material having conductive pathways therein, which are typically formed on the surface of the glass core. The conductive pathways through the dielectric material may provide routing for achieving design flexibility, and the uniform diameter of the TGVs may provide dimensional stability and improved connectivity. One challenge in bonding a substrate to a glass layer is that conductive features have to be patterned directly on the glass layer because conductive materials (e.g., copper) tend to delaminate. One way to reduce this reliability risk is to add a buffer layer between the glass layer and the substrate. The buffer layer includes individual conductive vias, one end of which is electrically coupled to an individual TGV, and the other end is electrically coupled to an individual conductive contact in the substrate. The conductive vias are required to have a diameter that is smaller than the diameter of the TGV to compensate for any overlap alignment errors with individual landing pads. Smaller sizes of conductive vias are more likely to cause malfunctions, failures, and other reliability issues. Various of the embodiments disclosed herein can help reduce the cost and complexity of assembling multi-die IC packages relative to conventional approaches, and improve the reliability and functionality of these IC packages during use.

[0020] Accordingly, disclosed herein is a microelectronic assembly comprising: a glass layer having a surface, the glass layer comprising conductive through-glass vias (TGVs); a dielectric layer located at the surface of the glass layer, the dielectric layer comprising conductive paths; and interconnects located between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive paths. In some embodiments, the interconnects comprise solder or liquid metal ink. In some embodiments, the interconnects comprise metal-metal bonding and dielectric-dielectric bonding.

[0021] Each of the structures, components, packaging, methods, devices, and systems disclosed herein may have several innovative aspects, no single one of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0022] In the following detailed description, terms commonly used by those skilled in the art may be used to describe various aspects of the exemplary embodiments so as to convey the substance of their work to others skilled in the art.

[0023] The terms "circuit" and "circuitry" refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide the intended functionality. The terms refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0024] The term "integrated circuit" refers to an electrical circuit that is integrated into a monolithic semiconductor or similar material.

[0025] In some embodiments, the IC die disclosed herein may include a substantially single crystal semiconductor such as silicon or germanium as a base material on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) structure. In some other embodiments, the base material of one or more of the IC dies may include an alternative material, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium indium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In yet other embodiments, the base material may include a compound semiconductor, for example, a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still further embodiments, the base material may include an intrinsic Group IV or Group III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still further embodiments, the die may include an amorphous material, such as a polymer; for example, the base material may include a silicone-filled epoxy. In other embodiments, the base material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of materials for the die are described here, any material or structure that can serve as a substrate (e.g., a base material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.

[0026] Unless otherwise described, an IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, a control logic unit configured to control the memory device and array, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs that implement logic / computing circuitry (e.g., an IC that implements input / output (I / O) functions, arithmetic operations, pipelining of data, etc.).

[0027] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “chiplet,” “die,” and “IC die” are used interchangeably herein.

[0028] The term "optical structure" includes various arrangements made in the IC structure to receive, transform and / or transmit optical signals as described herein. It can include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0029] In various embodiments, any of the photonic ICs (PICs) described herein may include semiconductor materials, such as N-type or P-type materials. The PICs may include, for example, crystalline base materials formed using bulk silicon (or other bulk semiconductor materials) or SOI structures (or more generally semiconductor-on-insulator structures). In some embodiments, the PICs may be formed using alternative materials that may or may not be combined with silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium aluminum arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, gallium indium arsenide, gallium nitride, gallium indium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV group materials. In some embodiments, the PICs may include amorphous materials, such as polymers. In some embodiments, the PICs may be formed on a printed circuit board (PCB). In some embodiments, the PIC can be heterogeneous, including a carrier material (e.g., glass or silicon carbide) as a base material along with a thin semiconductor layer on top of which the active side including transistors and similar components is located. Although several examples of materials for PICs are described herein, any material or structure that can serve as a foundation on which a PIC can be built falls within the spirit and scope of the present disclosure.

[0030] The term "insulation" means "electrical insulation" and the term "conduction" means "conductive conduction" unless otherwise specified. With reference to optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction".

[0031] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0032] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0033] The term "insulating material" refers to a solid material (and / or a liquid material that becomes solid after processing as described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon and alumina, or combinations thereof. They may include dielectric materials, high polarizability materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and moldings or materials similar to moldings used in packaging applications, including, for example, materials used in organic interposers, packaging supports, and other such components.

[0034] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements integrated into the IC in a monolithic form, those elements mounted on the IC, or those elements connected to the IC. The IC described herein may be analog or digital, and may be used in many applications, such as microprocessors, optoelectronic components, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC described herein may be used in a single IC die, or may be used as part of a chipset that performs one or more related functions in a computer.

[0035] In various embodiments of the present disclosure, the transistors described herein may be field effect transistors (FETs), such as metal oxide semiconductor (MOS) FETs (MOSFETs). In general, a FET is a three-terminal device that includes a source, a drain, and a gate terminal and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in and / or on the channel material, and a gate stack, the gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided on a portion of the channel material located between the source region and the drain region ("channel portion"), and optionally also including a gate dielectric material located between the gate electrode material and the channel material.

[0036] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect described herein should be understood with reference to the signal medium associated with the interconnect. Thus, when used with reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more elements associated with the IC or / and between various such elements. In such a case, the term "interconnect" can refer to both electrical traces (sometimes also referred to as "wires", "conductors", "metal wires" or "trench") and electrical vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, thereby emphasizing the fact that these elements include conductive materials (e.g., metals). Similarly, when used with reference to a device that also operates on optical signals (e.g., a PIC), "interconnect" may also describe any element formed of an optically conductive material for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to an optical waveguide (e.g., a structure that guides and constrains light waves), which includes optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0037] The term "waveguide" refers to any structure that functions to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed from silicon, doped silicon, silicon nitride, glass (e.g., silica (e.g., silicon dioxide or SiO2)), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and the like. The waveguide can be formed using various techniques including, but not limited to, forming the waveguide in situ. For example, in some embodiments, the waveguide can be formed in situ in glass using low temperature glass-to-glass bonding or by laser direct writing. The waveguide formed in situ can have lower loss characteristics.

[0038] The term "conductive trace" may be used to describe conductive elements that are isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided into the IC die. Within package substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto build-up film (ABF), polyimide, or epoxy. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0039] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, the via may be provided substantially perpendicular to the plane of the IC die / chip or to the plane of a support structure on which the IC structure is provided, and the via may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0040] The term "package substrate" may be used to describe any substrate material that helps package any collection of semiconductor die and / or other electrical components (e.g., passive electrical components) together. As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a build layer (e.g., ABF layer).

[0041] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0042] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0043] In the context of a stack of mutually coupled dies or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first level interconnect (FLI). A DTPS interconnect may also be referred to as a second level interconnect (SLI). Although not specifically shown in all of the introduced illustrations to avoid cluttering the drawings, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts of the first group may be electrically and mechanically coupled to some of the conductive contacts of the second group through a DTD or DTPS interconnect. In some embodiments, the spacing of the DTD interconnect may be different from the spacing of the DTPS interconnect, although in other embodiments, the spacings may be substantially the same.

[0044] It should be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, each level of underfill may include the same or different insulating materials. In some embodiments, each level of underfill may include a thermosetting epoxy with silicon oxide particles; in some embodiments, each level of underfill may include any suitable material capable of performing an underfill function (such as supporting the die and reducing thermal stresses acting on the interconnects). In some embodiments, the selection of underfill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of underfill material may be based on material properties and processing conditions, such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of underfill material may be based on both design considerations and processing considerations.

[0045] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC packages described herein and may not be labeled or illustrated to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0046] The terms "substantially," "close," "approximately," "near," and "approximately" generally mean within + / - 20% of a target value (e.g., within + / - 5% or + / - 10% of a target value), based on the context of the specific values ​​described herein or as known in the art.

[0047] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally mean within + / - 5%-20% of the target value, based on the context of specific values ​​described herein or as known in the art.

[0048] The term "connected" refers to a direct connection between the connected objects (which may be one or more of mechanical, electrical and / or thermal connections) without any intermediate devices, while the term "coupled" refers to a direct connection between the connected objects or an indirect connection through one or more passive or active intermediate devices.

[0049] The specification uses the phrase "in an embodiment," which may refer to one or more of the same or different embodiments.

[0050] Furthermore, the terms "comprising," "including," "having," and the like used in connection with embodiments of the present disclosure are synonymous.

[0051] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0052] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intervening layers. In contrast, a first layer described as being "above" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0053] As used herein, the term "disposed" refers to positioning, location, placement, and / or arrangement, rather than any particular method of formation.

[0054] When used in connection with a range of measurements, the term "between" includes the end values ​​of the range of measurements.

[0055] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0056] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0057] Unless otherwise indicated, the use of ordinal adjectives such as "first," "second," "third," etc., to describe common objects simply indicates that different instances of similar objects are being referred to, and does not imply that the objects described must be in a given order temporally, spatially, sequentially, or in any other manner.

[0058] In the detailed description below, reference is made to the accompanying drawings which form a part thereof, and in the accompanying drawings, embodiments that can be practiced are shown by way of example. It should be understood that other embodiments can be utilized and structural and logical changes can be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limiting sense.

[0059] The drawings are not necessarily drawn to scale.

[0060] In the drawings, like reference numerals refer to the same or similar elements / materials illustrated, and unless otherwise stated, the interpretation of an element / material with a given reference numeral provided in the context of one of the drawings may be applicable to other drawings that may illustrate an element / material with the same reference numeral.

[0061] Additionally, in the accompanying drawings, some schematic illustrations of exemplary structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic illustrations may not reflect real-life process limitations that may cause the features to appear less than "ideal" when any of the structures described herein are examined using, for example, images of appropriate characterization tools (such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact surface profilometers). In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, deviations in curvature or profile, pits or scratches, imperfectly straight edges of materials, tilted vias or other openings, unintended rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device fabrication and / or packaging.

[0062] Note that in the drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) only for ease of illustration; in reality, some or all of them may be misaligned. In addition, there may be other components in the assembly, such as bonding pads, landing pads, metallizations, etc., which are not shown in the drawings to avoid confusion. In addition, the drawings are intended to show the relative arrangement of the components within their assemblies, and in general such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal relief). For example, in some other embodiments, the assemblies shown in the drawings may include more dies together with other electrical components. In addition, although some components of the assemblies are shown as planar rectangles or formed by rectangular entities in the drawings, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, which is determined by the manufacturing processes used to make the various components and is sometimes unavoidable due to these manufacturing processes.

[0063] In the drawings, specific numbers and arrangements of structures and components are described for purposes of illustration, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0064] Furthermore, unless otherwise stated, the structures shown in the drawings may take any appropriate form or shape depending on material properties, manufacturing processes and operating conditions.

[0065] For convenience, if there is a collection of drawings designated by different letters (e.g. Figures 5A-5D ), then such a set may be referred to herein without those letters (e.g., as “FIG. 5”). Similarly, if there is a set of reference numerals designated with different numbers and / or letters (e.g., 105-1, 105-2), then such a set may be referred to herein without those numbers (e.g., as “105”).

[0066] Each operation may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the subject matter claimed for protection. However, the order of description should not be interpreted as implying that these operations are necessarily sequence-dependent. Specifically, these operations may not be performed in the order in which they are introduced. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0067] Figure 1is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a core 103 having a TGV 110 and a substrate 148 electrically coupled to the core 103 through an interconnect 107. Specifically, the core may have a first surface 170-1 and an opposite second surface 170-2. The TGV 110 may extend through the core 103 from the first surface 170-1 to the second surface 170-2. The first substrate 148-1 may be electrically coupled to the first surface 170-1 of the core 103 through the first interconnect 107-1, and the second substrate 148-2 may be electrically coupled to the second surface 170-2 of the core 103 through the second interconnect 107-2. In some embodiments, the first interconnect 107-1 and the second interconnect 107-2 may include solder or liquid metal ink (LMI). The interconnect 107 including solder may include any suitable solder material such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys.

[0068] The microelectronic assembly 100 may further include a first material 105-1 around the first interconnect 107-1 between the first surface 170-1 of the core 103 and the first substrate 148-1, and a second material 105-2 around the second interconnect 107-2 between the second surface 170-2 of the core 103 and the second substrate 148-2. The material 105 may include an underfill material. The material 105 may be an insulating material, such as a suitable epoxy material. In some embodiments, the material 105 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the material 105 may include an epoxy flux that helps solder the substrate 148 to the core 103 when forming the interconnect 107, and then polymerizes and encapsulates the interconnect 107. The underfill process may include dispensing an underfill material in liquid form, allowing the material to flow and fill the gap around the interconnect 107, and subjecting the assembly to a curing process (e.g., baking) to make the material solid. The material 105 can be selected to have a coefficient of thermal expansion (CTE) that can alleviate or minimize stress between the substrate 148 and the core 103 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the material 105 can have a value intermediate the CTE of the substrate 148 (e.g., the CTE of the dielectric material of the substrate 148) and the CTE of the core 103. In some embodiments, the first material 105-1 and the second material 105-2 are the same material. In some embodiments, the first material 105-1 and the second material 105-2 are different materials.

[0069] The first substrate 148-1 and the second substrate 148-2 may include conductive pathways 196 (e.g., including conductive traces and / or conductive vias, as shown) through the dielectric material. The substrate 148 may include a set of first conductive contacts 172 located at the bottom surface of the substrate 148 and a set of second conductive contacts 174 located at the top surface of the substrate 148, wherein the conductive pathways 196 electrically couple each of the first conductive contacts 172 and the second conductive contacts 174. The first substrate 148-1 and the second substrate 148-2 may be manufactured using any suitable technology, such as conventional substrate packaging or PCB manufacturing processes (e.g., semi-additive plating processes, etc.). In some embodiments, the dielectric material of substrate 148 may include bismaleimide triazine (BT) resin, polyimide material, epoxy material (e.g., glass reinforced epoxy matrix material or epoxy build film, etc.), molding material, oxide-based material (e.g., silicon dioxide or spin-on oxide), or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). The TVG 110 in core 103 may electrically couple the first substrate 148-1 and the second substrate 148-2. As used herein, the core 103 having the second substrate 148-2 and / or the first substrate 148-1 may be referred to as a packaging substrate. The TGV 110 in core 103 may enable power, ground, and signal connections to components located on both sides of the core 103 (e.g., between the die 114-1, 114-2 and the circuit board 131).

[0070] Figure 2A Shows Figure 1 1, which shows the dimensions of the TGV 110 passing through the core 103 and the thickness of the first material 105-1 and the second material 105-2. The first material 105-1 and the second material 105-2 can have any suitable dimensions, including a thickness 195 (e.g., z-height or z-dimension) between 5 microns and 50 microns. In some embodiments, the thickness 195-1 of the first material 105-1 can be equal to the thickness 195-2 of the second material 105-2. In some embodiments, the thickness 195-1 of the first material 105-1 can be different from the thickness 195-2 of the second material 105-2.

[0071] TGV 110 may have any suitable size and shape. Figure 2A TGV 110 is shown as having straight and parallel edges; however, in various embodiments, for example, Figure 2B As shown in , depending on the processing conditions used to create the TGV 110, the edges may be tapered and / or have other irregularities. Figure 2AAs shown in , the TGV 110 can have the same diameter 197 throughout the core 103 (eg, the diameter 197 is substantially equal across the thickness (eg, z-height)). Figure 2B As shown in FIG. 1 , the TGV 110 may have a tapered or angled profile, wherein the TGV 110 has a narrower diameter 197-3 in the middle and thicker diameters 197-1, 197-2 at the first surface 170-1 and the second surface 170-2, respectively. In some embodiments, the diameter 197 (e.g., Figure 2A The diameter of 197 and Figure 2B The diameters 197-1, 197-2 of the core 103, respectively, at the adjacent surfaces 170-1, 170-2 may be between 10 microns and 200 microns (e.g., between 35 microns and 75 microns). The TGVs 110 may be formed using any suitable process, including, for example, by laser drilling a via opening through the core 103 and depositing a conductive material in the opening. The TGVs 110 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. In some embodiments, the pitch of the TGVs 110 may be between 50 microns and 200 microns (e.g., between 75 microns and 150 microns).

[0072] The material of core 103 may include glass, for example, bulk transparent glass, which is different from the glass fiber typically used in the reinforced epoxy core for packaging substrates or motherboards. In addition, in various embodiments, the glass of core 103 is not obviously combined with any organic material, but includes any type of bulk amorphous or polycrystalline transparent, opaque or translucent glass, including fused silica, borosilicate glass, soda-lime glass, ceramic glass, etc. In such embodiments, core 103 may be referred to as "glass layer" in this article. In some embodiments, the thickness 191 of core 103 can be between 25 microns and 2 millimeters (e.g., between 25 microns and 200 microns, between 100 microns and 1 millimeter or between 500 microns and 2 millimeters).

[0073] Re-watch Figure 1, the microelectronic assembly 100 may further include a die 114-1 and a die 114-2 electrically coupled to the top surface of the second substrate 148-2 through an interconnect 150. Specifically, the conductive contacts 122 located on the bottom surfaces of the dies 114-1, 114-2 may be electrically and mechanically coupled to the conductive contacts 174 located at the top surface of the second substrate 148-2 through the interconnect 150. The interconnect 150 may achieve electrical coupling between the die 114-1 and the die 114-2 through a conductive path 196 in the substrate 148-2. The interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of interconnects 150 may include solder 124 (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the interconnects 150). The interconnects 150 including solder may include any suitable solder material, for example, as described above with reference to the interconnect 107. In some embodiments, a set of interconnects 150 may include an anisotropic conductive material, for example, an anisotropic conductive film or an anisotropic conductive paste. Anisotropic conductive materials may include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials may include tiny conductive particles embedded in a glue or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy or an acrylic resin-based material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include gold coated with nickel or copper coated with silver, which are then coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is fully compressed (e.g., by a conductive contact located on either side of the anisotropic conductive material), the conductive materials near the compressed area may contact each other, thereby forming a conductive path from one side of the film to the other side in the compressed area. In some embodiments, the interconnect 150 disclosed herein may have a spacing between about 18 microns and 75 microns.

[0074] The tube core 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the tube core 114 may include a semiconductor material such as silicon, germanium, or a III-V group material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the tube core 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts in the tube core 114 (e.g., connecting multiple conductive contacts located on the same surface or different surfaces of the tube core 114) in any appropriate manner. Conductive paths in die 114 may be adjacent to liner materials, such as adhesive liners and / or barrier liners, as appropriate. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a single crystal silicon, fan-out or fan-in packaged die, or a die stack (e.g., a stacked wafer, a stacked die, or a stacked multi-layer die). In various embodiments, die 114 may include a central processing unit (CPU), a memory device (e.g., a high bandwidth memory device), a logic circuit, an input / output circuit system, a transceiver (e.g., a field programmable gate array transceiver), a gate array logic unit (e.g., a field programmable gate array logic unit), a power delivery circuit system, a III-V or III-N device (such as a III-V or III-N amplifier (e.g., a GaN amplifier)), a high-speed peripheral component interconnect (PCIe) circuit system, a double data rate (DDR) transmission circuit system, or one or more of other electronic components known in the art, or may be a portion thereof. In some embodiments, die 114-1 and die 114-2 may include different functions. As used herein, the term "function" with reference to a die refers to one or more functions (e.g., capabilities, tasks, operations, actions, instruction execution, etc.) that the referenced die is capable of performing. For example, die 114-1 may be a CPU, and die 114-2 may be a graphics processing unit (GPU) or a memory. In other embodiments, die 114-1 and die 114-2 may include the same or similar functions. For example, die 114-1 and die 114-2 may both include a memory.

[0075] Figure 1The microelectronic assembly 100 may also include an insulating material 133 encapsulating the tube core 114 (e.g., located on and around the tube core 114 and the interconnect 150). The insulating material 133 can extend from the top surface of the second substrate 148-2 to the top surface of the tube core 114. In some embodiments, the insulating material 133 can be a molding material, for example, an organic polymer, a resin material, or an epoxy resin material with inorganic silicon oxide or aluminum oxide particles. In some embodiments (not shown), other components (e.g., a heat sink) can be coupled to the microelectronic assembly 100 based on specific needs.

[0076] Figure 1 The microelectronic assembly 100 can also include an underfill material 127. In some embodiments, the underfill material 127 can extend around the associated interconnects 150 between the die 114-1, 114-2 and the second substrate 148-2. The underfill material 127 can include any suitable underfill material, such as those described above with reference to the material 105. In some embodiments, the underfill material 127 can extend around the associated interconnects 150 between the second substrate 148-2 and the die 114-1, 114-2. In some embodiments, the underfill material 127 can be omitted. Although Figure 1 Two separate underfill material 127 portions are shown under die 114-1 and die 114-2, but underfill material 127 can be a single underfill material 127 under die 114-1 and die 114-2. Underfill material 127 can be selected to have a coefficient of thermal expansion (CTE) that can relieve or minimize stress between die 114 and second substrate 148-2 caused by uneven thermal expansion in microelectronic assembly 100. In some embodiments, the CTE of underfill material 127 can have a value that is intermediate the CTE of second substrate 148-2 (e.g., the CTE of the dielectric material of substrate 148) and the CTE of the insulating material of die 114.

[0077] Figure 1 The microelectronic assembly 100 may also include a circuit board 131. Specifically, the conductive contacts 172 located on the bottom surface of the first substrate 148-1 may be electrically coupled to the conductive contacts 146 located on the top surface of the circuit board 131 via an interconnect 190. The interconnect 190 disclosed herein may take any suitable form, including solder balls in a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement, or may be any of the forms described above with reference to the interconnect 150. Figure 1As shown in , in some embodiments, a set of interconnects 190 may include solder 136 (e.g., solder bumps or balls that are subjected to thermal reflow to form interconnects 190). In some embodiments, the interconnects 190 disclosed herein may have a spacing between approximately 50 microns and 300 microns. In some embodiments, the bottom fill material 127 may extend around the associated interconnects 190 between the first substrate 148-1 and the circuit board 131. For example, the circuit board 131 may be a motherboard and may have other components attached thereto. As is known in the art, a circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the interconnect 190 may not be coupled to the circuit board 131, but may instead be coupled to another IC package, an interposer, or any other suitable component.

[0078] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC packages described herein and may not be labeled or illustrated to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0079] Figure 3 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. Except for the differences that will be further described, the configuration of the embodiment shown in the figure is similar to Figure 1Similar to that shown. The configuration of the microelectronic assembly 100 as described herein further includes a TGV 110 having the same material as the interconnect 107. Specifically, the material of the TGV 110 is the same as the interconnect 107 and includes solder or LMI. The configuration of the microelectronic assembly 100 as described herein further includes a bridge die 202. The bridge die 202 can be at least partially located within the dielectric material of the second substrate 148-2 (e.g., at least partially embedded in the cavity). The bridge die 202 can be electrically coupled to the tube core 114 (e.g., the tube core 114-1 and the tube core 114-2) through the interconnect 150. Specifically, the conductive contact 122 located on the bottom surface of the tube core 114 can be electrically and mechanically coupled to the conductive contact 125 located at the top surface of the bridge die 202 through the interconnect 150. The bridge die 202 can include appropriate circuit systems located on / in the semiconductor substrate to connect at silicon interconnect speeds with a small footprint. In some embodiments, bridge die 202 may include active components such as transistors and diodes in addition to bridge circuitry including metallization traces, vias, and passive components for achieving electrical coupling between two ICs; in other embodiments, bridge die 202 may include bridge circuitry including metallization traces, vias, and passive components for achieving electrical coupling between die 114-1 and die 114-2, and may not include active components. "Bridge die" may also be referred to as "interconnect die" herein.

[0080] Figure 4A is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. Except for the differences that will be further described, the configuration of the embodiment shown in the figure is similar to Figure 3 Similar to that shown. The configuration of the microelectronic assembly 100 described herein includes a substrate 148 electrically coupled to the core 103 via an interconnect 106 (e.g., a hybrid bond) and further includes a double-sided bridge die 202. The double-sided bridge die 202 can be at least partially located within the dielectric material of the second substrate 148-2 (e.g., at least partially embedded in a cavity). The bridge die 202 can be electrically coupled to the tube core 114 (e.g., the tube core 114-1 and the tube core 114-2) via the interconnect 150 and electrically coupled to the conductive path 196 in the second substrate 148-2 via the interconnect 120. Specifically, the conductive contact portion 122 located on the bottom surface of the bridge die 202 can be electrically coupled to the conductive path 196 of the second substrate 148-2 (e.g., a conductive trace in a metal layer). In some embodiments, the bridge die 202 can include a through-substrate via (TSV) (not shown).

[0081] Figure 4B1 is a schematic cross-sectional view of the details of a specific interconnection in the interconnection 106 in the microelectronic assembly 100. In some embodiments, the example of the interconnection 106 is a hybrid joint including a metal-metal joint and a dielectric-dielectric joint. In a general sense, the interconnection 106 may include a metal-metal joint between a bonding pad 132 of the layer 106-1 and a bonding pad 134 of the layer 106-2 at an interface 130 between the layer 106-1 and the layer 106-2 and a dielectric-dielectric joint in the layer 106-1 and the layer 106-2. The bonding pad 132 of the layer 106-1 can be bonded with the bonding pad 134 of the layer 106-2. The bonding pads 132 and 134 may also be referred to as conductive contacts or metal contacts in this article. The material of the metal-metal joint (e.g., the bonding pads 132 and 134) may include copper-copper. The dielectric material 104 in the layer 106-1 and the layer 106-2 may be bonded to each other. The dielectric material 104 may include an inorganic dielectric (e.g., silicon and oxygen in the form of silicon oxide) or an organic dielectric (e.g., polyimide). The bonded metallic material and dielectric material form an interconnect 106 including a hybrid bond that provides electrical and mechanical coupling between layer 106-1 and layer 106-2. In various embodiments, the thickness 199 of the interconnect 106 may be between 5 nanometers and 25 microns. In various embodiments, the interconnect 106 may have a spacing of less than 10 microns between adjacent interconnects. In some embodiments, the interconnect 106 may have a spacing of between 2 microns and 70 microns (e.g., between 2 microns and 10 microns, between 10 microns and 45 microns, or between 45 microns and 70 microns).

[0082] The microelectronic assembly 100 disclosed herein may be manufactured using any suitable technique. For example, Figures 5A-5D According to various embodiments, Figure 1 The following are side cross-sectional views of various stages in an exemplary process of a microelectronic assembly 100. Figures 5A-5D The operations discussed in the present disclosure (and other figures showing the manufacturing process) are shown in a particular order, but these operations can be performed in any suitable order. In addition, additional operations not shown can be performed without departing from the scope of the present disclosure. Moreover, the present disclosure can be modified according to the present disclosure. Figures 5A-5D Various of the operations discussed may be performed to fabricate other of the microelectronic assemblies 100 disclosed herein.

[0083] Figure 5A A core 103 is shown including a first surface 170 - 1 and a second surface 170 - 2 . Figure 5BThe assembly is shown after forming a via opening 511 through the core 103. The via opening 511 can be formed using any suitable process, including photolithography, laser-assisted wet etching, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching. The via opening 511 can have any suitable shape. For example, the via opening 511 can have substantially vertical sidewalls to form a rectangular-shaped via as shown, or can have angled sidewalls to form a tapered-shaped via. The shape of the via opening 511 can depend on the process used to form the via opening 511 (e.g., a photolithography process for a rectangular-shaped via and a laser drilling process for a tapered-shaped via).

[0084] Figure 5C Shown in Figure 5B A conductive material is deposited in the via opening of the TGV 110 to form a subsequent component. The conductive material may include any suitable material, such as copper (e.g., Figure 1 ), or may include solder or LMI (e.g., as shown in Figure 3 ). The conductive material may be deposited using any suitable process including electroplating, slot coating, or inkjet printing.

[0085] Figure 5D The assembly is shown after depositing interconnect material 507 (e.g., solder or LMI) on the top and bottom surfaces of TGV 110. In embodiments where TGV 110 includes solder, interconnect material 507 may include solder. In embodiments where TGV 110 includes LMI, interconnect material 507 may include LMI. In some embodiments, interconnect material 507 may be omitted from core 103.

[0086] Fig. 6A The carrier 601 is shown after patterning the conductive material on the surface to form the conductive contacts 172. The carrier 601 may include any suitable material for providing mechanical stability during manufacturing operations. The conductive material may be deposited using any suitable process including photolithography, electrolytic plating or electroless plating.

[0087] Figure 6B The assembly is shown after forming a second substrate 148-2 on the carrier 601 and depositing solder 124 on the conductive contacts 174 at the top surface of the second substrate 148-2. Conventional packaging substrate manufacturing techniques may be used to manufacture the Figure 6B components.

[0088] Figure 6C It is shown that the tube core 114-1, 114-2 is placed Figure 6BThe assembly after forming interconnect 150 and depositing bottom fill material 127 around interconnect 150 on the top surface of the assembly. Dies 114-1, 114-2 may be placed using any suitable method, such as automated pick and place. In some embodiments, interconnect 150 may include solder. In such an embodiment, Figure 6C The assembly may be subjected to a solder reflow process during which the solder features of interconnect 150 melt and bond to mechanically and electrically couple die 114-1, 114-2 to Figure 6C In some embodiments, insulating material 133 (eg, as shown in FIG. 1 ) may be deposited on and around die 114 - 1 , 114 - 2 . Figure 1 In such an embodiment, underfill 127 may be dispensed around interconnect 150 prior to depositing insulating material 133. In some embodiments, underfill 127 around interconnect 150 may be omitted. In some embodiments, dies 114-1, 114-2 may be electrically coupled after second substrate 148-2 is coupled to core 103 via interconnect 107.

[0089] Fig.6D The assembly 600-2 is shown after removing the carrier 601 from the second substrate 148-2 and depositing an interconnect material 507 on the conductive contacts 172. The interconnect material 507 may include solder or LMI.

[0090] Fig. 6E The assembly 600-1 is shown to include a first substrate 148-1 having an interconnect material 507 located on the conductive contact 174. The interconnect material 507 may include solder or LMI. Conventional packaging substrate manufacturing techniques may be used to manufacture the Fig. 6E Components, as referenced above Fig. 6A and Figure 6B described.

[0091] Fig. 7A They are shown respectively Figure 5D , Fig. 6E and Fig.6D Components 500, 600-1, and 600-2, wherein component 600-1 is aligned at the first surface 170-1 of component 500, and component 600-2 is aligned at the second surface 170-2 of component 500. Fig. 7A Components of show interconnect material 507 located on component 500 and on components 600-1, 600-2 (e.g., located on both sides of the interconnect), but in some embodiments, interconnect material 507 may be located only on component 500 or only on components 600-1, 600-2 (e.g., located on only one side of the interconnect).

[0092] Figure 7B The assembly is shown after placing assembly 600-1 on first surface 170-1 of assembly 500 and forming first interconnect 107-1, and placing assembly 600-2 on second surface 170-2 of assembly 500 and forming second interconnect 107-2. In some embodiments, interconnect 107 may include solder. In such embodiments, Figure 7B The components 600 - 1 , 600 - 2 may be subjected to a solder reflow process during which solder features of the interconnects 107 melt and bond to mechanically and electrically couple the components 600 - 1 , 600 - 2 to the component 500 .

[0093] Figure 7C Component 100 is shown after depositing a first material 105-1 around a first interconnect 107-1 between a first surface 170-1 of core 103 and a first substrate 148-1 and a second material 105-2 around a second interconnect 107-2 between a second surface 170-2 of core 103 and a second substrate 148-2. The first material 105-1 and the second material 105-2 may be deposited using any suitable process, including capillary underflow. If multiple components are manufactured together, the components may be singulated. Figure 7C The component itself can be a microelectronic component 100, as shown. Figure 7C The microelectronic assembly 100 is subjected to further manufacturing operations to form other microelectronic assemblies 100; for example, solder 136 can be deposited on the conductive contact portion 172 at the bottom surface of the first substrate 148-1 and used to Figure 7C The microelectronic assembly 100 is coupled to the circuit board 131 via the interconnect 190, which is Figure 1 The microelectronic assembly 100 is similar.

[0094] Fig. 8A An assembly 800 - 1 is shown including a core 103 having a TGV 110 , the core 103 having a first surface 170 - 1 and a second surface 170 - 2 . Fig. 8A The component 800-1 may be manufactured using any suitable process, as described above with reference to Figures 5A-5C described.

[0095] Figure 8B Shown in Fig. 8A The assembly 800-2 after depositing the first bonding layer 106-1 and the second bonding layer 106-2 on the respective second surface 170-2 and the first surface 170-1 of the assembly. The first bonding layer 106-1 may include the bonding pad 132 located in the dielectric material 104. The second bonding layer 106-2 may include the bonding pad 134 located in the dielectric material 104.

[0096] Fig.9A The assembly is shown after forming a second bonding layer 106-2 on the carrier 901. The second bonding layer 106-2 may include bonding pads 134 located in the dielectric material 104. The carrier 901 may include any suitable material for providing mechanical stability during manufacturing operations.

[0097] Fig. 9B Shown in Fig.9A The component after the second substrate 148-2 is formed on the top surface of the component. Fig. 9B The assembly may include a conductive contact 172 coupled to the bonding pad 134 of the second bonding layer 106 - 2 . Fig. 9B The components can be manufactured using conventional package substrate manufacturing techniques.

[0098] Fig. 9C It is shown that the tube core 114-1, 114-2 is placed Fig. 9B 1, 114-2. The die 114-1, 114-2 may be placed using any suitable method, such as automated pick and place. In some embodiments, the interconnect 150 may include solder. In such an embodiment, Fig. 9C The assembly may be subjected to a solder reflow process during which the solder features of interconnect 150 melt and bond, thereby mechanically and electrically coupling die 114-1, 114-2 to Fig. 9C 1. In some embodiments, insulating material 133 may be deposited on and around die 114-1, 114-2 (e.g., as shown in FIG. 4). In such embodiments, underfill 127 may be dispensed around interconnect 150 prior to depositing insulating material 133. In some embodiments, underfill 127 around interconnect 150 may be omitted. In some embodiments, die 114-1, 114-2 may be coupled after second substrate 148-2 is attached to the core via interconnect 106.

[0099] Fig.9D An assembly 900 - 1 is shown that includes a first substrate 148 - 1 having a first bonding layer 106 - 1 with bonding pads 132 located in a dielectric material 104 . Fig.9D The assembly may include a conductive contact 174 coupled to the bonding pad 132 of the first bonding layer 106-1. Conventional packaging substrate manufacturing techniques may be used to manufacture the Fig.9D components.

[0100] Fig. 10A They are shown respectively Figure 8B , Fig. 9C and Fig.9D Components 800-2, 900-1, and 900-2, wherein component 900-1 is aligned at the first surface 170-1 of component 800-2 and component 900-2 is aligned at the second surface 170-2 of component 800-2. Fig. 10A Component 800-2 is included (eg, bonding layers on both sides of the interconnect), but in some embodiments, Fig. 10A The components can instead include Fig. 8A Component 800-1 (e.g., a bonding layer located on one side of the interconnect).

[0101] Fig. 10B The assembly is shown after placing assembly 900 - 1 on first surface 170 - 1 of assembly 800 - 2 , placing assembly 900 - 2 on second surface 170 - 2 of assembly 800 - 2 , and forming interconnect 106 . Fig. 10B The assembly may be subjected to an appropriate bonding process to form interconnect 106. For example, the bonding process may include applying an appropriate pressure for a certain duration and heating to an appropriate temperature (e.g., heating to a moderately high temperature, such as between about 50 degrees Celsius and 400 degrees Celsius). Fig.9D The components may be subjected to a suitable bonding process to form interconnect 106. For example, the bonding process may include applying a suitable pressure for a certain duration and heating to a suitable temperature (e.g., heating to a moderately high temperature, e.g., between about 50 degrees Celsius and 400 degrees Celsius). If multiple components are manufactured together, the components may be singulated. Fig. 10B The component itself can be a microelectronic component 100, as shown. Fig. 10B The microelectronic assembly 100 is subjected to further manufacturing operations to form other microelectronic assemblies 100; for example, solder 136 can be deposited on the conductive contact portion 172 at the bottom surface of the first substrate 148-1 and used to Fig. 10B The microelectronic assembly 100 of FIG. 4 is coupled to the circuit board 131 through the interconnect 190 , which is similar to the microelectronic assembly 100 of FIG. 4 .

[0102] A package disclosed herein (eg, any of microelectronic assemblies 100 ) or any other embodiment described herein can be included in any suitable electronic component. Figure 11-13 Various examples of packages, components, and devices are shown that may be used in conjunction with or include any of the IC packages disclosed herein.

[0103] Fig.11is a side cross-sectional view of an exemplary IC package 2200 that can include a microelectronic assembly according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 can be a system-in-package (SiP).

[0104] like Fig.11 As shown in , the package support portion 2252 can be formed of an insulator (e.g., ceramic, a built-up film, an epoxy resin film with filler particles therein, etc.), and can have conductive paths extending through the insulator between the first side 2272 and the second side 2274, or extending between different locations on the first side 2272, and / or extending between different locations on the second side 2274. These conductive paths can take the form of any interconnect structure including wires and / or vias, for example, as described above with reference to Figure 1 Discussed.

[0105] The package support portion 2252 may include a conductive contact portion 2263 coupled to a conductive path 2262 passing through the package support portion 2252, thereby allowing the circuit system within the tube core 2256 and / or the interposer 2257 to be electrically coupled to the individual conductive contacts in the conductive contact portion 2264 (or to other devices not shown contained in the package support portion 2252).

[0106] The IC package 2200 may include an interposer 2257 coupled to a package support 2252 via conductive contacts 2261 of the interposer 2257 , a first level interconnect (FLI) 2265 , and conductive contacts 2263 of the package support 2252 . Fig.11 The FLI 2265 shown in FIG. 2 is a solder bump, but any suitable FLI 2265 may be used, such as a solder bump, a solder column, or a bond wire.

[0107] The IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of the die 2256, FLI 2258, and conductive contacts 2260 of the interposer 2257. In various embodiments, the interposer 2257 may include a core as described herein. The conductive contacts 2260 may be coupled to conductive pathways (not shown) passing through the interposer 2257, thereby allowing the circuitry within the die 2256 to be electrically coupled to the respective conductive contacts 2261 (or to other devices not shown contained in the interposer 2257). Fig.11The FLI 2258 shown in the figure is a solder bump, but any suitable FLI 2258 may be used, such as a solder bump, a solder column, or a bonding wire. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that acts as an interface between different components; a conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0108] In some embodiments, an underfill material 2266 may be disposed around the FLI 2265 between the package support 2252 and the interposer 2257, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package support 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. Where appropriate, an exemplary material that may be used for the underfill material 2266 and the molding 2268 is epoxy. A second level interconnect (SLI) 2270 may be coupled to the conductive contact 2264. Fig.11 The SLI 2270 is shown as a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable SLI 2270 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The SLI 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and described below with reference to Fig.13 discussed.

[0109] In embodiments where IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-die package (MCP). Dies 2256 may include circuitry that performs any intended function. For example, in addition to one or more of dies 2256 including components of die 114 as described herein, one or more of dies 2256 may be a logic die (e.g., a silicon-based die), and one or more of dies 2256 may be a memory die (e.g., a high bandwidth memory), etc. In some embodiments, at least some of dies 2256 may not include components of die 114 as described herein.

[0110] although Fig.11The IC package 2200 shown is a flip chip package, but other package architectures may be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package support 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the prior art.

[0111] Fig.12 is a cross-sectional side view of an IC device assembly 2300, which includes components that may have one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes several components disposed on a circuit board 2302 (e.g., which may be a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposite second side 2342 of the circuit board 2302; in general, the components may be disposed on one or both of the sides 2340 and 2342. Specifically, any appropriate component of the components of the IC device assembly 2300 may include any of the microelectronic components in one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form described above with reference to the IC package. Fig.11 The IC package 2200 may be in the form of any of the embodiments discussed.

[0112] In some embodiments, circuit board 2302 may be a PCB that includes multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed into a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB package support.

[0113] Fig.12It is shown that in some embodiments, the IC device assembly 2300 can include an interposer package structure 2336 coupled to the first side 2340 of the circuit board 2302 via a coupling component 2316. Although not shown to avoid cluttering the drawings, in some embodiments, the interposer package structure 2336 can include a core. In other embodiments, the interposer package structure 2336 may not include a core. The coupling component 2316 can electrically and mechanically couple the interposer package structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, adhesive, bottom fill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0114] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling feature 2318. In some embodiments, the IC package 2320 may include the microelectronic assembly 100 and other components described herein, which are not shown to avoid cluttering the drawing. Depending on the intended function, the coupling feature 2318 may take any suitable form, such as the forms discussed above with reference to the coupling feature 2316. In some embodiments, the IC package 2320 may be or may include the IC package 2200, such as described above with reference to the IC package 2200. Fig.11 as described.

[0115] although Fig.12 A single IC package 2320 is shown, but multiple IC packages can be coupled to interposer 2304; indeed, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediate package support for bridging circuit board 2302 and IC package 2320. In general, interposer 2304 can redistribute connections to a wider spacing or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 to a BGA of coupling component 2316 for coupling to circuit board 2302.

[0116] exist Fig.12 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected via interposer 2304.

[0117] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 2304 may be formed of alternating rigid or flexible materials, which may include materials similar to those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including TSVs 2306. The interposer 2304 may further include embedded devices 2314, which include both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. Package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0118] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0119] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together via coupling component 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0120] Fig.132400 may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include microelectronic assembly 100 according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., Fig.11 In yet another example, any one or more of the components of the computing device 2400 may include the IC device assembly 2300 (e.g., as shown in Fig.12 shown in ).

[0121] exist Fig.13 Several components are shown as included in computing device 2400, but any one or more of these components may be omitted or duplicated, depending on the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

[0122] Furthermore, in various embodiments, the computing device 2400 may not include Fig.13 The computing device 2400 may include one or more of the components shown, but the computing device 2400 may include interface circuitry for coupling to one or more of the components. For example, the computing device 2400 may not include the display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0123] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other appropriate processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0124] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips; note that the terms "chip," "die," and "IC die" are used interchangeably herein). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0125] The communication chip 2412 can implement any of several wireless standards or protocols, including Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project together with any revisions, updates and / or adaptations thereof (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0126] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 2412 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0127] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0128] Computing device 2400 may include display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0129] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0130] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0131] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0132] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0133] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, a trackpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0134] The computing device 2400 may have any desired form factor, such as a portable or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0135] The above description of the exemplary embodiments of the present disclosure (including the contents described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the exact forms disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the present disclosure.

[0136] The following paragraphs provide various examples of the embodiments disclosed herein.

[0137] Example 1 is a microelectronic assembly comprising: a glass layer having a surface, the glass layer comprising conductive through-glass vias (TGVs); a dielectric layer located at the surface of the glass layer, the dielectric layer comprising conductive paths; and interconnects located between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive paths.

[0138] Example 2 may include the subject matter of Example 1, and may further specify that the interconnect comprises solder or liquid metal ink.

[0139] Example 3 may include the subject matter of Example 2, and may further include: an underfill material surrounding the interconnect between a surface of the glass layer and the dielectric layer.

[0140] Example 4 may include the subject matter of Example 3, and may further specify that the thickness of the underfill material is between 5 microns and 50 microns.

[0141] Example 5 may include the subject matter of Example 1, and may further specify that the interconnect comprises a metal-to-metal bond and a dielectric-to-dielectric bond.

[0142] Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the diameter of the individual TGVs is between 10 microns and 200 microns.

[0143] Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the glass layer has a thickness between 25 micrometers and 2 millimeters.

[0144] Example 8 may include the subject matter of any of Examples 1-7, and may further include: a die on the dielectric layer and electrically coupled to the conductive vias in the dielectric layer.

[0145] Example 9 may include the subject matter of Example 8, and may further include: an interconnect die at least partially within the dielectric layer and electrically coupled to the die.

[0146] Example 10 may include the subject matter of any of Examples 1-9, and may further specify: the interconnect is a second interconnect, the dielectric layer is a second dielectric layer including a second conductive path, the surface is a second surface, and the glass layer further includes a first surface opposite the second surface, and the microelectronic assembly may further include: a first dielectric layer located at the first surface of the glass layer, the first dielectric layer including a first conductive path; and a first interconnect located between the first surface of the glass layer and the first dielectric layer, wherein an individual first interconnect electrically couples an individual TGV to the individual first conductive path.

[0147] Example 11 may include the subject matter of Example 10, and may further specify that the first interconnect comprises solder or liquid metal ink.

[0148] Example 12 may include the subject matter of Example 11, and may further specify that the material of the first interconnect, the second interconnect, and the TGV comprises solder.

[0149] Example 13 may include the subject matter of Example 11, and may further specify that the material of the first interconnect, the second interconnect, and the TGV comprises liquid metal ink.

[0150] Example 14 may include the subject matter of Example 11, and may further include: an underfill material surrounding the first interconnect between the first surface of the glass layer and the first dielectric layer.

[0151] Example 15 may include the subject matter of Example 10, and may further specify that the first interconnect includes a metal-metal bond and a dielectric-dielectric bond.

[0152] Example 16 may include the subject matter of any of Examples 10-15, and may further include: a circuit board at the first dielectric layer and electrically coupled to the first conductive path.

[0153] Example 17 is a microelectronic component comprising: a glass layer having a surface; a via extending through the glass layer, wherein the via comprises a conductive material; a dielectric layer located at the surface of the glass layer, the dielectric layer comprising a conductive path; an interconnect comprising solder or liquid metal ink located between the surface of the glass layer and the dielectric layer, the interconnect electrically coupling the via and the conductive path; and a bottom fill material surrounding the interconnect located between the glass layer and the dielectric layer.

[0154] Example 18 may include the subject matter of Example 17, and may further specify that the thickness of the underfill material is between 5 micrometers and 50 micrometers.

[0155] Example 19 may include the subject matter of Example 17 or 18, and may further specify that the via has a diameter between 10 micrometers and 200 micrometers.

[0156] Example 20 may include the subject matter of any of Examples 17-19, and may further specify that the thickness of the glass layer is between 25 micrometers and 2 millimeters.

[0157] Example 21 may include the subject matter of any of Examples 17-20, and may further specify that the underfill material includes epoxy, capillary underfill, non-conductive film (NCF), or molded underfill.

[0158] Example 22 may include the subject matter of any of Examples 17-21, and may further include: a die on the dielectric layer and electrically coupled to the conductive vias in the dielectric layer.

[0159] Example 23 may include the subject matter of Example 22, and may further include: an interconnect die at least partially within the dielectric layer and electrically coupled to the die.

[0160] Example 24 may include the subject matter of any of Examples 17-23, and may further specify: the interconnect is a second interconnect, the dielectric layer is a second dielectric layer including a second conductive path, the surface is a second surface, and the glass layer further includes a first surface opposite the second surface, and the microelectronic assembly may further include: a first dielectric layer located at the first surface of the glass layer, the first dielectric layer including the first conductive path; a first interconnect including solder or liquid metal ink located between the first surface of the glass layer and the first dielectric layer, the first interconnect electrically coupling the via and the first conductive path; and an underfill material surrounding the first interconnect located between the first surface of the glass layer and the first dielectric layer.

[0161] Example 25 may include the subject matter of Example 24, and may further include: a circuit board at the first dielectric layer and electrically coupled to the first conductive path.

[0162] Example 26 is a microelectronic component comprising: a glass layer having a through glass via (TGV), the TGV comprising a conductive material; a substrate layer comprising a conductive path; and a hybrid bonding region between the glass layer and the substrate layer, wherein the hybrid bonding region comprises a metal-metal bond and a dielectric-dielectric bond, and the TGV is electrically coupled to the conductive path via the metal-metal bond.

[0163] Example 27 may include the subject matter of Example 26, and may further specify that the thickness of the hybrid bonding region is between 5 nanometers and 25 micrometers.

[0164] Example 28 may include the subject matter of Example 26 or 27, and may further specify that the diameter of the TGV is between 10 microns and 200 microns.

[0165] Example 29 may include the subject matter of any of Examples 26-28, and may further specify that the thickness of the glass layer is between 25 micrometers and 2 millimeters.

[0166] Example 30 may include the subject matter of any of Examples 26-29, and may further specify: the glass layer includes a first surface and an opposite second surface, the substrate layer is a first substrate including a first conductive path; the hybrid bonding region is a first hybrid bonding region having a first metal-metal bond and a first dielectric-dielectric bond, and the first hybrid bonding region is located between the first surface of the glass layer and the first substrate layer, and the microelectronic assembly may further include: a second substrate layer including a second conductive path; and a second hybrid bonding region located between the second surface of the glass layer and the second substrate layer, wherein the second hybrid bonding region includes a second metal-metal bond and a second dielectric-dielectric bond, and the TGV is electrically coupled to the second conductive path through the second metal-metal bond.

[0167] Example 31 may include the subject matter of Example 26, and may further include: a die on the substrate layer and electrically coupled to the conductive vias in the substrate layer.

[0168] Example 32 may include the subject matter of Example 31, and may further include: an interconnect die at least partially located within the substrate layer and electrically coupled to the die.

[0169] Example 33 may include the subject matter of Example 31 or 32, and may further include: an insulating material surrounding the die.

Claims

1. A microelectronic assembly comprising: a glass layer having a surface, the glass layer comprising a conductive through-glass via (TGV); a dielectric layer at the surface of the glass layer, the dielectric layer comprising conductive pathways; and Interconnects are located between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive pathways.

2. The microelectronic assembly according to claim 1, wherein: The interconnect comprises solder or liquid metal ink.

3. The microelectronic assembly of claim 2 further comprising: An underfill material surrounding the interconnect is located between the surface of the glass layer and the dielectric layer.

4. The microelectronic assembly according to claim 3, wherein: The thickness of the underfill material is between 5 microns and 50 microns.

5. The microelectronic assembly according to claim 1, wherein: The interconnects include metal-metal bonding and dielectric-dielectric bonding.

6. The microelectronic assembly according to any one of claims 1 to 5, wherein: The diameter of individual TGVs is between 10 and 200 microns.

7. The microelectronic assembly according to any one of claims 1 to 5, wherein: The thickness of the glass layer is between 25 micrometers and 2 millimeters.

8. The microelectronic assembly according to any one of claims 1 to 5, further comprising: A die is located on the dielectric layer and electrically coupled to the conductive vias in the dielectric layer.

9. The microelectronic assembly according to any one of claims 1 to 5, wherein: The interconnect is a second interconnect, the dielectric layer is a second dielectric layer including a second conductive path, the surface is a second surface, and the glass layer further includes a first surface opposite the second surface, and the microelectronic assembly further includes: a first dielectric layer at the first surface of the glass layer, the first dielectric layer comprising a first conductive path; and First interconnects are located between the first surface of the glass layer and the first dielectric layer, wherein individual first interconnects electrically couple individual TGVs to individual first conductive pathways.

10. The microelectronic assembly of claim 9, wherein: The first interconnect includes solder or liquid metal ink.

11. The microelectronic assembly of claim 9, wherein: The first interconnect includes a metal-metal bond and a dielectric-dielectric bond.

12. A microelectronic assembly comprising: A glass layer having a surface; a via extending through the glass layer, wherein the via comprises a conductive material; a dielectric layer at the surface of the glass layer, the dielectric layer comprising conductive pathways; an interconnect comprising solder or liquid metal ink between the surface of the glass layer and the dielectric layer, the interconnect electrically coupling the via and the conductive path; and An underfill material surrounding the interconnect is located between the glass layer and the dielectric layer.

13. The microelectronic assembly of claim 12, wherein: The thickness of the underfill material is between 5 microns and 50 microns.

14. The microelectronic assembly of claim 12, wherein: The diameter of the via hole is between 10 microns and 200 microns.

15. The microelectronic assembly of claim 12, wherein: The thickness of the glass layer is between 25 micrometers and 2 millimeters.

16. The microelectronic assembly of claim 12, wherein: The underfill material includes epoxy, capillary underfill, non-conductive film (NCF), or molded underfill.

17. A microelectronic assembly according to any one of claims 12 to 16, wherein: The interconnect is a second interconnect, the dielectric layer is a second dielectric layer including a second conductive path, the surface is a second surface, and the glass layer further includes a first surface opposite the second surface, and the microelectronic assembly further includes: a first dielectric layer at the first surface of the glass layer, the first dielectric layer comprising a first conductive path; a first interconnect comprising solder or liquid metal ink between the first surface of the glass layer and the first dielectric layer, the first interconnect electrically coupling the via and the first conductive path; and The underfill material is located between the first surface of the glass layer and the first dielectric layer surrounding the first interconnect.

18. The microelectronic assembly of claim 17, further comprising: A circuit board is located at the first dielectric layer and electrically coupled to the first conductive path.

19. An integrated circuit (IC) package, comprising: a glass layer having a through glass via (TGV), the TGV comprising a conductive material; a substrate layer including a conductive path; as well as A hybrid bonding region is located between the glass layer and the substrate layer, wherein the hybrid bonding region includes a metal-metal bonding and a dielectric-dielectric bonding, and the TGV is electrically coupled to the conductive path through the metal-metal bonding.

20. The IC package of claim 19, wherein: The thickness of the hybrid junction region is between 5 nanometers and 25 micrometers.

21. The IC package of claim 19, wherein: The diameter of the TGV is between 10 and 200 microns.

22. The IC package according to any one of claims 19 to 21, wherein: The glass layer includes a first surface and an opposite second surface, the substrate layer is a first substrate layer including a first conductive path, the hybrid bonding region is a first hybrid bonding region having a first metal-metal bonding and a first dielectric-dielectric bonding, and the first hybrid bonding region is located between the first surface of the glass layer and the first substrate layer, and the IC package further includes: a second substrate layer including a second conductive path; and A second hybrid bonding region is located between the second surface of the glass layer and the second substrate layer, wherein the second hybrid bonding region includes a second metal-metal bond and a second dielectric-dielectric bond, and the TGV is electrically coupled to the second conductive path through the second metal-metal bond.

23. The IC package according to any one of claims 19 to 21, further comprising: A die is located on the substrate layer and electrically coupled to the conductive vias in the substrate layer.

24. The IC package of claim 23, further comprising: An interconnect die is at least partially located within the substrate layer and electrically coupled to the die.

25. The IC package of claim 23, further comprising: An insulating material surrounds the die.

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