High-reliability trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

Description

Technical Field

[0001] The invention relates to a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements are higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss. In fields such as aerospace, the high reliability of silicon carbide VDMOS has become the key to restricting its application. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a highly reliable trench gate silicon carbide VDMOS and a preparation method thereof, and to achieve the purpose of improving device reliability by optimizing the design of the gate structure and the source structure.

[0004] In a first aspect, the present invention provides a method for preparing a high-reliability trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first P-type well region and a protruding portion; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low resistance first region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low-resistance second region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low resistance zone 3, wherein the low resistance zone includes a low resistance zone 1, a low resistance zone 2, and a low resistance zone 3; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form an N-type source region; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a conductive area; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a protection zone; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the first P-type well region to form a groove and a second P-type well region, and oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0005] In a second aspect, the present invention provides a high-reliability trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a high-reliability trench gate silicon carbide VDMOS according to the first aspect.

[0006] The advantages of the present invention are: 1. The present invention leads the current of the source metal layer to the middle of the device, flows to the middle through the conductive area and then flows vertically, thereby realizing the gate control capability of the device; Second, the present invention wraps the gate structure and source structure of the device close to the drain by the first P-type well region and the second P-type well region, so that when the drain is subjected to a large voltage, the first P-type well region and the second P-type well region protect the gate and source of the device, thereby improving the reliability of the device; 3. The present invention constructs a two-layer structure of a conductive area and a protection area in the middle JFET area of ​​the device. The conductive area can introduce electrons from the device gate structure into the device JFET area, thereby reducing the on-resistance of the device. The protection area suppresses the voltage from the device drain to be distributed on the top of the device, thereby avoiding the voltage of the intermediate electric field from affecting the gate structure of the device and improving the reliability of the device. Fourth, the present invention constructs a second P-type well region directly below the insulating dielectric layer, and the second P-type well region can protect the electric field concentration at the corner of the device gate, further improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of a high-reliability trench-gate silicon carbide VDMOS of the present invention is shown in FIG.

[0009] Figure 2 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0011] Figure 4 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0012] Figure 5 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0013] Figure 6 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0017] Fig.10 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0018] Fig.11 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0019] Fig.12 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 one.

[0020] Fig.13 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 two.

[0021] Fig.14 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 three.

[0022] Fig.15 A cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10Four. DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] like Figures 1 to 15 As shown, the embodiment of the present application provides a method for preparing a high-reliability trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112, and epitaxially growing on the upper side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: forming a barrier layer 113 on the drift layer 102, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a first P-type well region 103 and a protruding portion 1021; Step 3, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the first P-type well region 103 to form a low resistance first region 114; Step 4, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the first P-type well region 103 to form a low-resistance second region 115; Step 5, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the first P-type well region 103, and form a low resistance third region 116, wherein the low resistance region 1031 includes a low resistance first region 114, a low resistance second region 115, and a low resistance third region 116; Step 6: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation into the drift layer 102 to form a P-type source region 106; Step 7, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form an N-type source region 107; Step 8: removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a conductive region 108; Step 9, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a protection zone 109; Step 10, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and etching the drift layer 102 and the first P-type well region 103 to form a groove 10311 and a second P-type well region 104, and oxidizing to form an insulating dielectric layer 105, wherein the insulating dielectric layer 105 is provided with a groove 1051; Step 11, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal, and forming a gate metal layer 110; Step 12: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a source metal layer 111, remove the barrier layer 113, and complete the preparation.

[0029] In this embodiment, preferably, the silicon carbide substrate 101 , the drift layer 102 , the low resistance region 1031 and the conductive region 108 are all N-type; and the protection region 109 is P-type.

[0030] In this embodiment, preferably, the doping concentration of the first P-type well region 103 is equal to the doping concentration of the low resistance region 1031 .

[0031] In this embodiment, preferably, the doping concentration of the conductive region 108 is less than the doping concentration of the protection region 109 .

[0032] In this embodiment, preferably, the doping concentration of the P-type source region 106 is greater than the doping concentration of the N-type source region 107 .

[0033] In this embodiment, preferably, the thickness of the conductive region 108 is 200 nm.

[0034] In this embodiment, preferably, the thickness of the protection zone 109 is 300 nm.

[0035] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101, A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a protrusion 1021 is provided on the drift layer 102; A first P-type well region 103, wherein the lower side of the first P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the first P-type well region 103 is connected to the outer side of the protrusion 1021; a low resistance region 1031 is provided in the first P-type well region 103, and a groove 10311 is provided in the low resistance region 1031; A second P-type well region 104, wherein the second P-type well region 104 is disposed in the groove 10311; An insulating dielectric layer 105, wherein the lower side of the insulating dielectric layer 105 is connected to the upper side of the second P-type well region 104, and the lower part of the insulating dielectric layer 105 is disposed in the groove 10311; a groove 1051 is disposed in the insulating dielectric layer 105; A P-type source region 106 , wherein the lower side of the P-type source region 106 is connected to the upper side of the first P-type well region 103 ; An N-type source region 107, wherein the lower side of the N-type source region 107 is connected to the upper side of the low resistance region 1031, the outer side of the N-type source region 107 is connected to the inner side of the P-type source region 106, and the inner side of the N-type source region 107 is connected to the outer side of the insulating dielectric layer 105; A conductive region 108, wherein the lower side of the conductive region 108 is connected to the upper side of the first P-type well region 103 and the upper side of the protrusion 1021, and the outer side of the conductive region 108 is connected to the inner side of the insulating dielectric layer 105; A protection zone 109, wherein the lower side of the protection zone 109 is connected to the upper side of the conductive zone 108, and the outer side of the protection zone 109 is connected to the inner side of the insulating dielectric layer 105; A gate metal layer 110, wherein the gate metal layer 110 is disposed in the groove 1051; A source metal layer 111 , wherein the source metal layer 111 is connected to the P-type source region 106 and the N-type source region 107 ; and a drain metal layer 112 , wherein the drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101 .

[0036] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 1-5e16cm -3 , the doping concentration of the N-type low resistance region 1031 is 1-5e17cm -3 The doping concentrations of the first P-type well region 103 and the second P-type well region 104 are both 1-5e17cm -3 , the doping concentration of the N-type source region 107 is 2-8e18cm -3 , the doping concentration of the P-type source region 106 is 1-5e19cm -3 , the doping concentration of the N-type conductive region 108 is 5-9e17cm -3 , the doping concentration of the P-type protection zone 109 is 1-5e18cm -3, the insulating dielectric layer 105 can be silicon dioxide; the doping concentration of the silicon carbide substrate 101 is to ensure the formation of low-resistance ohmic contact with the drain metal layer 112, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the first P-type well region 103 and the second P-type well region 104 is mainly considered in two aspects: one is to achieve the protection of the gate and source structure of the device, and the doping concentration must be high; the other is to ensure that the charge of the gate is small and the concentration must be low. A compromise is made between the two, and this concentration is selected; the doping concentration of the low-resistance region 1031 is mainly The purpose of the invention is to reduce the on-resistance of the device without affecting the protective effect of the first P-type well region 103 and the second P-type well region 104 on the device structure; the purpose of the N-type source region 107 and the P-type source region 106 is to reduce the ohmic contact resistance of the source of the device, and at the same time, the ion implantation due to too high concentration will not damage the device lattice and affect the stability of the device; the concentration of the conductive region 108 is to guide the electrons from the source of the device to the JFET region, thereby reducing the on-resistance of the device, but too high a concentration will affect the gate inversion region of the device, thereby affecting the gate control capability of the device; the doping concentration of the protection region 109 is to prevent the electric field from diffusing to the gate structure when the device is reversely withstand voltage, thereby protecting the gate structure; The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the N-type drift layer 102 is 30-100 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the first P-type well region 103 below the low resistance region 1031 is 1 μm, the thickness below the P-type source region 106 is 2 μm, and the thickness below the N-type conductive region 107 is 2 μm; the thickness of the second P-type well region 104 is 100 nm, and the thickness of the first P-type well region 103 between the low resistance region 1031 and the conductive region 108 is 200 nm; the thickness of the low resistance region 1031 below the N-type source region 107 is 1 μm, the thickness of the area directly below the second P-type well region 104 is 300nm, and the thickness of the area below the conductive region 108 is 900nm; the bottom thickness of the insulating dielectric layer is 50nm; the thickness of the N-type source region 107 and the P-type source region 106 are both 300nm, and the thickness of the source metal layer 111 is 200nm; the thickness of the conductive region 108 is 200nm; the thickness of the protection region 109 is 300nm; the width of the first P-type well region 103 of the device accounts for 60-70% of the total width of the device, which is to ensure that the on-resistance of the low-resistance region 1031 of the device is small enough to ensure the on-performance of the device; The present invention guides the current of the source metal layer 111 on both sides of the device to the middle of the device, flows to the middle through the N-type conductive region 108, and then flows vertically, so as to realize the gate control capability of the device; this method realizes the first P-type well region 103 and the second P-type well region 104 wrapping the gate structure and the source structure of the device close to the drain direction, so that when the drain is subjected to a large voltage, the first P-type well region 103 and the second P-type well region 104 realize the protection of the gate and source of the device, thereby improving the reliability of the device; In the middle JFET region of the device, a two-layer structure of an N-type conductive region 108 and a P-type protection region 109 is constructed. The N-type conductive region 108 can introduce electrons from the device gate structure into the device JFET region, thereby reducing the on-resistance of the device. The P-type protection region 109 suppresses the voltage caused by the device drain from being distributed at the top of the device, thereby avoiding the influence of the voltage of the intermediate electric field on the gate structure of the device and improving the reliability of the device. A second P-type well region 104 is constructed directly below the insulating dielectric layer 105 of the device. The second P-type well region 104 can protect the electric field concentration at the corner of the device gate and further improve the reliability of the device.

[0037] By designing the device structure, the first P-type well region 103 and the second P-type well region 104 can provide wrap-around protection for the device gate and source structure, thereby effectively suppressing device damage caused by drain voltage shock and improving the reliability of the device. At the same time, the P-type protection zone 109 completes the protection of the device gate structure from the perspective of the device conductive channel, thereby achieving high reliability characteristics of the device.

[0038] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-reliability trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first P-type well region and a protruding portion; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low resistance first region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low-resistance second region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a low resistance zone 3, wherein the low resistance zone includes a low resistance zone 1, a low resistance zone 2, and a low resistance zone 3; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form an N-type source region; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a conductive area; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a protection zone; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the first P-type well region to form a groove and a second P-type well region, and oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer, low resistance region and conductive region are all N-type; the protection region is P-type.

3. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first P-type well region is equal to the doping concentration of the low resistance region.

4. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the conductive region is lower than the doping concentration of the protection region.

5. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the N-type source region.

6. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the conductive region is 200 nm.

7. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the protection zone is 300 nm.

8. A high reliability trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 7.

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