Verification data processing method and equipment of memory and storage medium

Abstract

The embodiment of the invention provides a verification data processing method and equipment of a memory and a storage medium. When data in a target cache line is written into a plurality of data chips in a memory, the data in the target cache line can be coded according to a corresponding channel (data queue, DQ) region when the data is written into the data chips by adopting a coding mode corresponding to a target data verification algorithm, so that the data in the target cache line can be coded. And obtaining the first number of verification units and a plurality of information data units corresponding to the plurality of data chips. Wherein the target cache line is integrally coded, so that the data volume of the verification data can be effectively reduced. In the data reading stage, the information data units in the single channel area in any target data chip can be verified and / or corrected according to the first number of verification units, verification and / or correction of bounded errors in the isolation boundary are / is achieved under the condition that verification data is less, the cost of the memory is reduced, and meanwhile the memory performance is improved. The stability of the memory is ensured.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device and storage medium for processing verification data of a memory. Background Art

[0002] Internal memory (also known as memory, memory stick) is widely used in computer products to provide stable and secure data access services. With the development of computer technology, the related technologies of internal memory are constantly entering a new era. After the classic SDRAM (Synchronous Dynamic Random Access Memory) era, internal memory has entered the DDR SDRAM (Double Data Rate SDRAM) era. Among them, DDR SDRAM (hereinafter referred to as DDR) is a SDRAM with a double data transfer rate. Its data transfer speed is twice the system clock frequency. This data transfer speed makes the transmission performance of DDR SDRAM better than that of traditional SDRAM.

[0003] Generally, when selecting memory, a comprehensive evaluation of the optional memory can be conducted based on at least two aspects, namely, the cost and performance of the memory. Taking DDR5 (fifth generation DDR) as an example, the DDR5 JEDEC (Joint Electron Device Engineering Council) standard supports a variety of memory types, and different memory types correspond to different numbers of memory chips. The higher the number of chips, the higher the cost of the memory. Compared with higher-cost memory types, lower-cost memory types have poorer verification capabilities and are prone to memory downtime problems. Therefore, how to improve the verification performance of lower-cost memory has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] Multiple aspects of the present application provide a memory verification data processing method, device and storage medium, which are used to implement bounded error verification and / or error correction of the memory when the verification data is small, which is beneficial to reduce the cost of the memory while ensuring the stability of the memory.

[0005] An embodiment of the present application provides a verification data processing method for a memory, wherein the memory comprises: a plurality of data chips and at least one verification chip; the data transmission channel of any data chip is divided into a plurality of channel areas, and isolation boundaries are set between different channel areas; the method comprises: in response to a write data instruction, writing target data in a target cache line to a plurality of data chips in the memory; using an encoding method corresponding to a target data verification algorithm, encoding the target data in the target cache line according to the channel area corresponding to when the data is written to the data chip, to obtain a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips; writing the first number of verification units and the plurality of information data units corresponding to each of the plurality of data chips into the at least one verification chip, so that when the target data corresponding to the target cache line is read from the plurality of data chips, the target data is verified and / or error-corrected according to the data written in the at least one verification chip.

[0006] Optionally, the multiple information data units corresponding to any target data chip include: a second number of information data units corresponding to each of the multiple channel areas of the target data chip; the first number of verification units, used to verify and / or correct errors of the multiple information data units corresponding to each of the multiple data chips; the second number is smaller than the first number.

[0007] Optionally, it also includes: in response to a read data instruction, reading the target data corresponding to the target cache line from the multiple data chips, and reading the first number of verification units and the multiple information data units corresponding to each of the multiple data chips from the at least one verification chip; for any of the target data chips, using a decoding algorithm corresponding to the target data verification algorithm to decode the multiple information data units corresponding to the target data chip and the first number of verification units; based on the decoding result, verifying the target data in the target cache line; and when correctable errors exist in some of the multiple information data units corresponding to the target data chip, using the decoding result to correct errors in the data corresponding to the some of the information data units with correctable errors in the target cache line.

[0008] Optionally, an encoding method corresponding to a target data verification algorithm is adopted, and the target data in the target cache row is encoded according to the corresponding channel area when the data is written to the data chip, so as to obtain a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips, including: determining the number of data transmission channels contained in a single channel area according to the bit width information of the memory and the setting position of the isolation boundary; determining the number of target channels contained in a single information data unit according to the number of data transmission channels contained in the single channel area; determining the number of target bursts contained in a single information data unit according to the encoding unit length corresponding to the encoding method and the target number of channels; and establishing a connection relationship between the communication pin of the verification module corresponding to the target data verification method and the plurality of data transmission channels contained in each of the plurality of data chips according to the target number of channels, the target number of bursts and the set burst reading method.

[0009] Optionally, an encoding method corresponding to a target data verification algorithm is adopted to encode the target data in the target cache line according to a channel area corresponding to when the data is written into a data chip, so as to obtain a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips, including: utilizing the verification module to extract data from bursts generated by write operations of the target cache line on the plurality of data chips according to a connection relationship between a pre-established communication pin and a plurality of data transmission channels respectively included in the plurality of data chips, so as to obtain a plurality of information data units corresponding to each of the plurality of data chips; utilizing a preset generating polynomial to generate a first number of verification units according to the plurality of information data units corresponding to each of the plurality of data chips.

[0010] Optionally, determining the number of target channels included in a single information data unit according to the number of data transmission channels included in the single channel area includes: determining that the number of target channels included in the single information data unit is less than or equal to the number of data transmission channels included in the single channel area.

[0011] Optionally, after verifying the target data in the target cache line according to the result of the decoding, it also includes: if it is determined according to the result of the verification that an uncorrectable first error occurs in the target data chip, then according to the result of the verification, determining from the multiple information data units of the target data chip a target information data unit in which a correctable second error exists when the first error occurs; in the target data chip, obtaining a target storage address where the erroneous data corresponding to the second error is located; adding a risk mark to the target storage address, and writing the target storage address with the risk mark to a designated storage address segment in the memory; determining an error risk level according to the operation type of the memory when the first error occurs and / or the state of the processor corresponding to the memory; and sending an error handling event to the kernel according to the error risk level, so that the kernel reads the target storage address with the risk mark from the designated storage address segment, and performs a risk handling operation on the erroneous data in the target storage address according to the error risk level.

[0012] Optionally, the error risk level is determined based on the operation type of the memory and / or the state of the processor corresponding to the memory when the first error occurs, including: if when the first error occurs, the operation type of the memory is a read operation, and the processor is in a normal state, then the error risk level is determined to be: recoverable level; if when the first error occurs, the operation type of the memory is a non-read operation, then the error risk level is determined to be: no impact level.

[0013] Optionally, it also includes: updating first error statistics corresponding to the target data chip according to the error occurrence time of the first error; and updating second error statistics corresponding to each of the multiple channel areas in the target chip according to at least the channel area corresponding to the target verification unit and the error occurrence time of the second error; and performing abnormality prediction and / or performance analysis on the target data chip according to the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target chip.

[0014] Optionally, based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, an abnormality prediction is performed on the target data chip, including: determining multiple groups of training samples based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; any group of training samples includes: any uncorrectable type of historical first error corresponding to the target data chip and a correctable type of historical second error that occurred in the multiple channel areas in the target data chip before the historical error occurred; using the uncorrectable type of historical first error in the multiple groups of training samples as a supervisory signal, and performing supervised training on an error prediction model based on the multiple groups of training samples; the error prediction model is used to predict the probability of an uncorrectable error occurring in the target data chip based on the second error statistics of each of the multiple channel areas in the target data chip.

[0015] Optionally, multiple groups of training samples are determined based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, including: determining a first error sequence corresponding to the target data chip based on the updated first error statistics; the first error sequence includes: a plurality of historical first errors of an uncorrectable type arranged according to the error occurrence time; determining a second error sequence corresponding to each of the multiple channel areas in the target data chip based on the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; the second error sequence corresponding to any channel area includes: a plurality of historical second errors of a correctable type occurring in the channel area arranged according to the error occurrence time; for any historical first error in the first error sequence, determining the error occurrence time of the historical first error as the target error occurrence time; using a sliding time window, selecting a plurality of historical second errors located before the target error occurrence time in the first error sequence corresponding to each of the multiple channel areas in the target data chip as error samples corresponding to the historical first error; determining a group of training samples corresponding to the historical first error based on the historical first error and its error samples.

[0016] Optionally, a performance analysis of the target data chip is performed based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, including: determining the number of multi-bit errors corresponding to each of the multiple channel areas in the target data chip from the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; and determining the number of multi-bit errors corresponding to the target data chip from the updated first error statistics; accumulating the number of multi-bit errors corresponding to each of the multiple channel areas in the target data chip to obtain the total number of multi-bit errors corresponding to the multiple channel areas in the target data chip; determining the isolation success rate of the isolation boundary of the target data chip based on the ratio of the total number of multi-bit errors corresponding to the multiple channel areas in the target data chip to the number of multi-bit errors corresponding to the target data chip; and outputting the boundary isolation performance analysis information of the target data chip based on the isolation success rate.

[0017] Optionally, after performing abnormality prediction and / or performance analysis on the target data chip based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target chip, it also includes: obtaining a prediction result of abnormality prediction on the target data chip, and displaying the prediction result; and / or obtaining an analysis result of performance analysis on the target data chip, and displaying the analysis result; and / or sending a warning message to a designated terminal device based on the result of the abnormality prediction and / or the result of the performance analysis.

[0018] An embodiment of the present application also provides an electronic device, comprising: a memory, a storage controller and a processor; the memory is used to store one or more computer instructions; the storage controller and the processor are used to execute the one or more computer instructions to: execute the steps in the method provided in the embodiment of the present application.

[0019] The embodiment of the present application also provides a computer-readable storage medium storing a computer program, which can implement the steps in the method provided in the embodiment of the present application when the computer program is executed by a processor.

[0020] In the verification data processing method of the memory provided in the embodiment of the present application, when writing data in the target cache line to multiple data chips in the memory, the encoding method corresponding to the target data verification algorithm can be used, and the target data in the target cache line is encoded according to the channel area corresponding to the data chip when the data is written to the data chip, so as to obtain a first number of verification units and multiple information data units corresponding to each of the multiple data chips. Among them, encoding the target cache line as a whole can effectively reduce the amount of verification data. In the data reading stage, the information data unit in a single channel area in any target data chip can be verified and / or corrected according to the first number of verification units. When the verification data is small, the verification and / or correction of bounded errors within the isolation boundary is achieved, which is beneficial to reduce the cost of the memory while ensuring the stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A schematic flow chart of a method for processing verification data of a memory provided by an exemplary embodiment of the present application;

[0023] Figure 2 A schematic diagram of dividing the channel area of ​​a data chip with a bit width of 4 bits provided in an exemplary embodiment of the present application;

[0024] Figure 3 A schematic diagram of an encoding method of the RS algorithm provided by an exemplary embodiment of the present application;

[0025] Figure 4 A schematic diagram of extracting information data units of a data chip with a bit width of 4 bits provided by an exemplary embodiment of the present application;

[0026] Figure 5 A schematic diagram of extracting information data units of a data chip with a bit width of 4 bits provided by another exemplary embodiment of the present application;

[0027] Figure 6 A schematic diagram of bounded errors of a 9X4 internal memory and a 10X4 internal memory provided by another exemplary embodiment of the present application;

[0028] Figure 7 A schematic diagram of an application scenario provided for an exemplary embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two, but does not exclude the situation of including at least one.

[0032] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a product or system. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or system including the elements.

[0034] In order to solve the technical problem that low-cost memory types in the prior art have poor verification capabilities and easily cause memory crashes, a solution is provided in some embodiments of the present application. The technical solutions provided in each embodiment of the present application are described in detail below in conjunction with the accompanying drawings.

[0035] Figure 1 is a flow chart of a method for processing verification data of a memory provided by an exemplary embodiment of the present application. The method may include: Figure 1 Steps shown:

[0036] Step 101, in response to a write data instruction, write target data in a target cache row to multiple data chips in a memory; the memory includes: multiple data chips and at least one check chip; the data transmission channel of any data chip is divided into multiple channel areas, and isolation boundaries are set between different channel areas.

[0037] Step 102, using the encoding method corresponding to the target data verification algorithm, encode the target data in the target cache row according to the corresponding channel area when the data is written into the data chip, and obtain a first number of verification units and multiple information data units corresponding to each of the multiple data chips.

[0038] Step 103: write the first number of check units and the multiple information data units corresponding to each of the multiple data chips into the at least one check chip, so that when the target data corresponding to the target cache line is read from the multiple data chips, the target data is checked and / or error corrected according to the data written in the at least one check chip.

[0039] This embodiment is suitable for verifying the memory. The memory may include an internal memory or an external memory, such as a disk, a solid-state hard disk, etc., which is not limited in this embodiment. Generally, the memory includes multiple chips, and the multiple chips are packaged in a certain arrangement. The multiple chips of the memory can be divided into data chips and verification chips according to their functions. The data chip refers to a chip in the memory used to store the original data written to the memory, and the verification chip refers to a chip in the memory used to store the encoding data and verification data of the original data, so that when the original data is read, the original data read is verified according to the encoding data and verification data of the original data, and the erroneous part of the original data is corrected. Taking the memory as a DDR5 memory implemented as Nx4 type as an example, the DDR5 memory may include N memory chips, and the N memory chips include 8 data chips and N-8 verification chips, where N is a positive integer. If N=9, the DDR5 memory may include 8 data chips and 1 verification chip; if N=10, the DDR5 memory may include 8 data chips and 2 verification chips.

[0040] The following embodiments will take the internal memory (hereinafter referred to as memory, memory bar) as an example to illustrate the verification method of the memory. Taking the internal memory as an example, the access operation of the memory includes: data write operation and data read operation. When performing a data write operation on the memory, the encoding data and verification data of the original data to be written can be generated, and the encoding data and verification data of the original data can be stored in the verification chip in the memory. After the memory access is completed, the memory controller can verify and correct the content read from the memory based on the error checking and correction (Error Checking and Correcting, ECC) technology to improve the stability of the memory read operation. For example, when performing a data read operation on the memory, the target data can be read from the data chip, and the encoding data and verification data corresponding to the target data can be read from the specified chip. According to the encoding data and verification data corresponding to the target data, it can be verified whether the target data is wrong, and some erroneous data can be corrected.

[0041] Among them, the errors checked by the memory controller may include: correctable errors (corrected error, referred to as CE) and uncorrected errors (uncorrected error, referred to as UE). Among them, the correctable errors can be corrected by the memory controller based on the ECC algorithm. For a memory with an isolation boundary, correctable errors usually occur within the isolation boundary, also known as bounded errors; uncorrectable errors are usually cross-boundary errors. The error correction data (i.e., information data unit and check unit) corresponding to the ECC operation performed by the memory controller can be described as ECC error correction data, and the ECC error correction data is stored in the check chip.

[0042] The basic unit of memory access is a cache line. That is, when the computer writes data to the memory, the data in one cache line is written each time. The length of a single cache line can be 64 bytes or 32 bytes, and the subsequent embodiments will be illustrated by taking 64 bytes as an example. When reading data from the memory, the data corresponding to one cache line is read each time. The encoding operations of data in different cache lines are similar, and the following will be illustrated by taking the write operation of any target cache line as an example.

[0043] Among them, the memory access operation is implemented in a burst manner. Among them, a burst is a way of continuously transmitting data between adjacent storage units (columns) in the same row on a chip particle. The burst length (Burst Lengths, referred to as BL) is the number of storage units (columns) involved in a continuous transmission. Among them, the length of the burst is determined by the bit width of a single memory chip. Among them, the bit width of a memory chip refers to the number of data bits that the memory chip can transmit in one clock cycle. Among them, the number of data bits that a single memory chip can transmit in one clock cycle is determined by the number of data queues (Data Queue, DQ) contained in a single memory chip. Among them, a data queue represents a data transmission channel. In different bursts, data at the same bit position share a data transmission channel. For example, such as Figure 2 As shown, when the number of transmission channels included in a single memory chip is 4 (that is, the data transmission channels are DQ0, DQ1, DQ2, and DQ3), when the bit width of a single chip is 4 bits, a burst can transmit data of a length of 4 bits.

[0044] The larger the bit width of a single memory chip, the larger the amount of data transmitted by the single memory chip each time. Taking DDR5 memory as an example, the bit width of each memory chip in DDR5 is 4 bits. When DDR5 memory includes 8 memory chips for storing data, the bus bit width of the DDR5 chip is 64 bits. For a single memory chip, the width of a single burst generated by a memory access operation is the same as the bit width of a single memory chip. For example, when the bit width of a single chip is 4 bits, the length of a burst of a single chip is 4 bits.

[0045] Among them, in one memory access operation, a single memory chip can generate multiple bursts in batches. For example, taking the Nx4 type DDR5 memory as an example, in one memory access operation, a single memory chip can generate 16 bursts, each burst is 4 bits long, and the data length of 16 bursts is 64 bits. That is, in one memory access operation, a single data chip transmits 64 bits of data, and the 8 data chips in the memory transmit a total of 64 bytes of data. The burst generated by one memory access operation is used to transmit the data of a cache line. When writing data in the target cache line to the memory, the write operation of the data in the target cache line can trigger multiple chips in the memory to generate bursts separately. Among them, the data in the target cache line is described as target data.

[0046] In the memory, the data transmission channel of a single chip is divided into multiple channel areas, and isolation boundaries are set between different channel areas. The isolation boundary can be realized by setting an insulating material between adjacent channel areas. The isolation boundary is used to divide the memory chip into different channel areas, so that errors caused by memory access occur within the channel area, and no cross-border errors occur. Figure 2 As shown, when the number of transmission channels included in a single memory chip is 4, the data transmission channels DQ0 and DQ1 can be divided into the left channel area through the isolation boundary, and the data transmission channels DQ2 and DQ3 can be divided into the right channel area. Among them, the performance of the memory is correlated with the boundary isolation effect of the memory. If the probability of a cross-border error occurring in the memory during a read operation is low, the boundary isolation effect of the memory is good. On the contrary, if the probability of a cross-border error occurring in the memory during a read operation is high, the boundary isolation effect of the memory is poor. Among them, errors occurring within the isolation boundary are usually correctable errors. Therefore, in order to improve the verification and error correction performance of the memory, when the memory is read, the original data written (i.e., the target data in the target cache line) can be encoded according to the channel area corresponding to the data, and the encoding data and verification data of the original data transmitted in different channel areas can be obtained, and the encoding data and verification data of the original data transmitted in different channel areas can be used to verify the data read in each channel area. An exemplary description will be given below.

[0047] Optionally, the data transmission channels of a single chip can be evenly divided into multiple channel areas, and different channel areas contain the same number of transmission channels. For example, in a DDR5 memory, when a single chip contains 4 data transmission channels, the 4 data transmission channels can be divided into two channel areas, each channel area contains 2 data transmission channels.

[0048] When writing target data in a target cache line to multiple chips in a memory, the encoding method corresponding to the target data verification algorithm can be used to perform full cache line encoding on the target data in the target cache line. During the encoding process, the data in the target cache line written into the target data chip through the multiple channel areas can be encoded respectively according to the channel area corresponding to the data written into the data chip. Wherein, the encoding result of the target data in the target cache line includes: a first number of verification units and a plurality of information data units corresponding to each of the multiple data chips. Wherein, the multiple information data units corresponding to any target data chip include: a second number of information data units corresponding to each of the multiple channel areas of the target data chip. Wherein, the first number of verification units is used to verify and / or correct errors of the multiple information data units corresponding to each of the multiple data chips. Wherein, the second number is less than the first number. Wherein, in the process of encoding the target data in the target cache line, the data in the same information data unit obtained by encoding comes from the same channel area in the same data chip.

[0049] Optionally, the target verification algorithm can be an ECC algorithm based on RS coding (Reed-Solomon codes). RS coding is a forward error correction channel coding, which is effective for the polynomial generated by correcting the oversampled data. RS coding is a fixed-length code, which can rearrange the input data to be encoded into coding units of fixed length. The original data to be encoded is called the input symbol of RS coding, and the output coded data is called the output symbol of RS coding. The output symbol of RS coding has a certain length (i.e., the coding unit length), and one output symbol can be called a coding unit. Figure 3 As shown, RS encoding can encode input data into n encoding units. Among them, the n encoding units include k information data units and nk check units. During RS decoding, when n=k, the RS decoding algorithm can detect whether there are errors in any n information data units, and can correct up to n / 2 information data units with errors.

[0050] In this embodiment, the number of multiple information data units encoded by any target data chip can be a first number. That is, the number of multiple information data units encoded by any data chip is equal to the number of check units corresponding to the full cache line, so that the full amount of information data units corresponding to any target data chip can be checked, and up to half of the information data units corresponding to any target data chip can be corrected. In this embodiment, encoding is performed according to the channel area to which the data belongs, and information data units corresponding to different channel areas can be obtained. Furthermore, when any channel area in any target data chip corresponds to a second number of information data units, if the second number is less than or equal to half of the first number, the full amount of information data units corresponding to any channel area can be checked and corrected.

[0051] The following will provide a specific description in conjunction with the RS encoding algorithm.

[0052] In the process of RS encoding, the original data to be encoded (i.e., the target data in the target cache line) can be organized into multiple information data units (i.e., symbol), and a number of zeros are added after the multiple information data units to obtain a coded data polynomial. Among them, the position of the 0-added is used to reserve a place for the check code, and the number of 0s is corresponding to the number of check units. The coded data polynomial after 0-padded is divided by the generating polynomial, and the remaining polynomial is taken as the check polynomial. The check polynomial is added to the position of the zero-padded in the coded data polynomial to obtain the final check unit.

[0053] Among them, the RS encoding algorithm at least includes: RS-4 algorithm, RS-8 algorithm and RS-16 algorithm. Among them, the encoding unit length of the RS-4 algorithm is 4 bits; the encoding unit length of the RS-8 algorithm is 8 bits; the encoding unit length of the RS-16 algorithm is 16 bits. Among them, RS encoding algorithms with different encoding unit lengths are suitable for input data of different lengths. In the RS encoding algorithm, the range of the total encoded data length (that is, the information data unit and the check unit) is [0, 2^m-1], where m is the length of a single encoding unit. Among them, the maximum check data length corresponding to the target data check algorithm is greater than the sum of the lengths of the multiple information data units corresponding to the target cache line and multiple data chips.

[0054] For example, the coding unit length corresponding to the RS-4 algorithm is 4 bits, and the range of the total data length after encoding is [0, (2^4-1)*4] = [0, 60 bits], which is suitable for encoding input data less than 60 bits.

[0055] For example, the coding unit length corresponding to the RS-8 algorithm is 8 bits, and the range of the total data length after encoding is [0, (2^8-1)*8] = [0, 255B], which is suitable for encoding input data less than 255B.

[0056] For example, the coding unit length corresponding to the RS-16 algorithm is 16 bits, and the range of the total data length after encoding is [0, (2^16-1)*16] = [0, 131070B], which is suitable for encoding input data larger than 4KB.

[0057] In some optional embodiments, the memory is an Nx4 type DDR5 memory, which includes N memory chips, and the bit width of each memory chip is 4 bits, and the number of bursts generated by a memory access operation is 16, and a total of 64 bits of data are transmitted. In one memory access operation, the total length of the encoded data of the target cache line transmitted by 8 data chips is 64 bytes. That is, for the RS encoding algorithm, the order of magnitude of the data it needs to process is tens of bytes. Therefore, based on the above introduction to different RS encoding algorithms, it can be seen that the RS-8 algorithm can be used to encode the target data in the target cache line.

[0058] For a DDR5 memory of type Nx4, the N memory chips include 8 data chips for storing data and N-8 check chips for storing the coded data and check data of the original data. Among them, when the total length of the coded data and the check data of 64Bytes is less than the total storage length of a check chip, only one check chip is needed to verify part of the data stored in the 8 chips and correct at least part of the erroneous data stored in the 8 chips. That is, in some embodiments, N=9, and the memory is a 9x4 type DDR5 memory.

[0059] When encoding the original data written into the memory, for the RS-8 algorithm, the 64 bits of data generated by each data chip in a memory access operation can be encoded into 8 8-bit information data units. In order to achieve full verification of a single data chip, the target data in the target cache line can be encoded into 8 8-bit verification units. That is, the total length of the original data to be encoded is 64Bytes, and the verification data is 8Bytes. That is, the data length that the RS-8 algorithm needs to process in the decoding stage is 64Bytes+8Bytes=72Bytes. According to the maximum information data length used by the different types of RS decoding algorithms recorded above, the RS-8 algorithm can be used to encode the original data written into the memory. Accordingly, when performing a read operation on the memory, the RS-8 algorithm is used to decode and verify the data read from the memory. Furthermore, a verification chip can be used to verify the data in 8 data chips, thereby reducing the hardware cost of the memory.

[0060] In some exemplary embodiments, before encoding the original data written into the memory according to the corresponding channel area when the data is written, the number of data transmission channels contained in a single channel area can be determined according to the bit width information of the memory and the setting position of the isolation boundary in the chip. For example, taking a memory with a bit width of 4 bits as an example, the data channels contained in the memory are: DQ0, DQ1, DQ2, and DQ3; if the isolation boundary is set between DQ1 and DQ2, the data channel of the memory is divided into two channel areas, and the number of transmission channels contained in each channel area is 2. According to the number of data transmission channels contained in the single channel area, the number of target channels contained in a single information data unit can be determined. Optionally, it can be determined that the number of target channels contained in the single information data unit is less than or equal to the number of data transmission channels contained in the single channel area. Continuing to take a memory with a bit width of 4 bits as an example, when the data channel of the memory is divided into two channel areas, and the number of transmission channels contained in each channel area is 2, the number of transmission channels of a single information data unit can be 1 or 2.

[0061] After determining the target number of channels, the target number of bursts contained in a single information data unit can be determined based on the information data unit length corresponding to the encoding method of the target verification algorithm and the target number of channels. The target number of channels is the number of bits of data extracted from a single burst. The number of bursts contained in a single information data unit can be determined by dividing the information data unit length by the target number of channels. For example, when the information data unit length is 8 bits and the target number of channels is 2, the number of bursts contained in a single information data unit is 4. That is, the data of an information data unit consists of 4 (bursts)*2 (DQ) rectangular data blocks, such as Figure 4As shown. For another example, when the length of the information data unit is 8 bits and the number of target channels is 1, the number of bursts contained in a single information data unit is 8. That is, the data of an information data unit is composed of 8 (bursts)*1 (DQ) rectangular data blocks, as shown Figure 5 According to the target number of channels, the target number of bursts and the set burst reading mode, a connection relationship between the communication pins of the verification module corresponding to the target data verification method and the multiple data transmission channels respectively included in the multiple data chips in the memory can be established.

[0062] Accordingly, when encoding the target data in the target cache line, the verification module can be used to extract data from the burst generated by the write operation of the target data in the target cache line on the multiple data chips according to the connection relationship between the pre-established communication pins and the multiple data transmission channels, and obtain multiple information data units corresponding to each of the multiple data chips. Afterwards, a first number of verification units are generated according to the multiple information data units corresponding to each of the multiple data chips using a preset generator polynomial.

[0063] For example, in Figure 4 In the embodiment, the 8 bits of data corresponding to DQ0 and DQ1 in burst0, burst1, burst2 and burst3 can be read to obtain multiple information data units corresponding to the left channel area. For the left channel area, 16 bursts of data can be encoded into 4 8-bit information data units. Correspondingly, the 8 bits of data corresponding to DQ2 and DQ3 in burst0, burst1, burst2 and burst3 can be read to obtain multiple information data units corresponding to the right channel area. For the right channel area, 16 bursts of data can be encoded into 4 8-bit information data units. Thus, the data corresponding to a write operation on a single memory chip can be encoded into 8 8-bit information data units. After determining the information data units of the 8 data chips based on this implementation, 8 8-bit verification units can be generated according to the generating polynomials corresponding to the target verification algorithm and the information data units of the 8 data chips. The coded data and check data generated by one write operation of eight memory chips can be stored in one ECC chip to reduce the number of data chips required for the memory, thereby reducing the hardware cost required for the memory.

[0064] Based on the data encoding method described in the above embodiments, when a write operation occurs in the memory, the data written to the memory can be encoded to obtain an information data unit and a verification unit. Accordingly, when a read operation occurs in the memory, the information data unit and the verification unit corresponding to the data accessed by the read operation can be obtained from the memory, and verification and / or error correction operations can be performed on the read data according to the information data unit and the verification unit. The following will continue to illustrate the target cache line as an example. Among them, the target cache line can be any cache line.

[0065] Optionally, in response to a read instruction, the target data in the target cache line can be read from multiple data chips of the memory, and a first number of verification units and multiple information data units corresponding to each of the multiple data chips can be read from the at least one verification chip. For any of the target data chips, a decoding algorithm corresponding to the target data verification algorithm is used to decode the multiple information data units corresponding to the target data chip and the first number of verification units. According to the decoding result, the target data in the target cache line can be verified. When correctable errors exist in some of the multiple information data units corresponding to the target data chip, the decoding result can be used to perform error correction on the data corresponding to the partial information data units with correctable errors in the target data in the target cache line, wherein the number of partial information data units with correctable errors is less than or equal to the second number, and the second number is half of the first number. That is, when there are 8 8-bit verification units, all information data units in a single data chip can be verified, and up to 4 information data units can be corrected. If a single data chip contains the following: Figure 2 In the two channel areas shown in the figure, when no cross-border error occurs in a single data chip, eight 8-bit check units can correct the four information data units in the left channel area of ​​a single data chip, or can correct the four information data units in the right channel area of ​​a single data chip, thereby achieving full error correction of the entire data chip under the condition of relatively ideal boundary isolation effect.

[0066] After obtaining the verification result based on the above-mentioned implementation method, the type of error that occurred in any data chip can be determined according to the result of the verification. Among them, the error type of any data chip includes correctable error (CE) and uncorrectable error (UE). In some cases, the uncorrectable error in the memory is caused by the failure of the isolation boundary, so that correctable errors occur simultaneously in different channel areas. Therefore, when an uncorrectable error occurs in the memory, the memory controller can determine the information data unit in which the correctable error occurs simultaneously from multiple channel areas as the information data unit that causes the uncorrectable error. Continuing to take the target data chip as an example, optionally, if it is determined according to the result of the verification that an uncorrectable type of error occurs in the target data chip (hereinafter described as the first error for ease of distinction), then according to the result of the verification, a target information data unit in which a correctable type of error (hereinafter described as the second error for ease of distinction) occurs when the error occurs can be determined from multiple information data units of the target data chip.

[0067] After determining the target information data unit, the memory controller can obtain the target storage address where the error data corresponding to the first error is located in the target data chip. The memory controller can add a risk tag (such as a poison tag) to the target storage address and write the target storage address into a designated storage address segment in the memory. The designated storage address segment can be pre-agreed by the memory controller and the processor, or it can be set by the memory controller by default and synchronized to the processor. The designated storage address segment is set as a storage area that is inaccessible to other processes and cannot be applied for.

[0068] The memory controller may determine the error risk level according to the operation type of the memory and / or the state of the processor corresponding to the memory when the first error of the uncorrectable type occurs. Optionally, if the operation type of the memory is a read operation when the first error of the uncorrectable type occurs, and the processor is in a normal state, the error risk level may be determined as a recoverable level to identify the first error as an uncorrectable error that can be recovered by software. If the operation type of the memory is a non-read operation when the first error of the uncorrectable type occurs, the error risk level may be determined as a no-impact level to identify the first error as an uncorrectable error that does not need to be recovered temporarily.

[0069] After determining the risk level based on the above implementation, the memory controller can send an error handling signal to the processor according to the error risk level. After receiving the error handling signal, the processor can read the target storage address with the risk mark added according to the specified storage address segment, and generate an error handling event according to the target storage address with the risk mark added. The processor can send an error handling event to the Basic Input Output System (BIOS). After receiving the error handling event, the BIOS can perform corresponding operations and send the error handling event to the kernel so that the kernel performs error recovery operations. If the error type is an uncorrectable type, the kernel can end the process to which the address corresponding to the uncorrectable type error (i.e., the target storage address with the risk mark added) belongs.

[0070] Optionally, if the error risk level is: no impact level, the kernel can read the target storage address with the risk tag added from the specified storage address segment according to the error handling event, and read the error data from the target storage address with the risk tag added. The kernel can monitor the access operation to the data page where the error data is located through the synchronization interface. If the access operation to the data page where the error data is located is monitored, the data page where the error data is located can be isolated and the process can be terminated to reduce the impact of the uncorrectable error, thereby reducing the risk of the entire device where the memory is located being down.

[0071] Optionally, if the error risk level is: recoverable level, the kernel can read the target storage address with risk mark added from the specified storage address segment according to the error handling event, and read the error data from the target storage address with risk mark added. The kernel can lock the memory resources through the synchronization interface, isolate the data page where the error data is located, and end the process using the data page to reduce the impact of uncorrectable errors, thereby reducing the risk of the entire device where the memory is located being down.

[0072] In some optional embodiments, after respectively verifying the plurality of information data using the target data verification algorithm, the performance of the memory may be further monitored and optimized based on the verification results, which will be exemplified below.

[0073] Optionally, if it is determined based on the verification result that an uncorrectable first error of the target data chip occurs, the first error statistics corresponding to the target data chip can be updated based on the error occurrence time of the first error, and the second error statistics corresponding to each of the multiple channel areas in the target data chip can be updated based on at least the channel area corresponding to the target information data unit and the error occurrence time of the second error.

[0074] The first error statistics corresponding to the target data chip may include: uncorrectable errors of the target data chip in the historical period and their corresponding error occurrence time. For ease of description, the uncorrectable errors of the target data chip in the historical period are described as the historical first errors.

[0075] The second error statistics of any channel area in the target data chip may at least include: the correctable type of errors that occurred in the channel area in the historical period and the time when the errors occurred. In some optional embodiments, the second error statistics of any channel area may also include: the accumulated number of errors in the channel area, the accumulated number of error addresses, the error occurrence time of any error, and the data length corresponding to any error. This embodiment includes but is not limited to this. The memory controller can perform abnormal prediction and / or performance analysis on the target data chip based on the updated second error statistics corresponding to each of the multiple channel areas in the target data chip and the updated first error statistics corresponding to the target data chip. The following will be exemplified separately.

[0076] In some optional embodiments, multiple groups of training samples can be determined based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip. Wherein, any group of training samples includes: any uncorrectable historical first error corresponding to the target data chip and a correctable historical second error that occurred in multiple channel areas in the target data chip before the historical error occurred. After determining multiple groups of training samples, the uncorrectable historical first errors in the multiple groups of training samples can be used as supervisory signals, and supervised training can be performed on the error prediction model based on the multiple groups of training samples. Wherein, the error prediction model is used to predict the probability of an uncorrectable error occurring in the target data chip based on the error statistics of each of the multiple channel areas in the target data chip, so as to perform load migration on the target data chip based on the predicted results, thereby avoiding the risk of downtime in advance.

[0077] The following will take the generation process of any set of training samples as an example for illustrative explanation.

[0078] Optionally, the first error sequence corresponding to the target data chip can be determined according to the updated first error statistics, wherein the first error sequence may include: multiple historical first errors of uncorrectable type arranged according to the time of error occurrence. Wherein, the historical first errors in the second error sequence can be described as error true values. Accordingly, the second error sequence corresponding to each of the multiple channel areas in the target data chip can be determined according to the updated second error statistics corresponding to each of the multiple channel areas in the target data chip. Wherein, the second error sequence corresponding to any channel area includes: multiple historical second errors of correctable type that occurred in the channel area arranged according to the time of error occurrence. Wherein, each correctable error in the second error sequence can be described as an error sample. Each error sample carries a corresponding statistical feature. Wherein, according to the second error statistics of any channel area, the statistical data features of each error sample can be determined, and the statistical data features corresponding to each error sample may include: at least one of the number of errors accumulated in the channel area when the error occurs, the number of error addresses accumulated in the channel area when the error occurs, and the data length corresponding to the error.

[0079] Among them, usually, the correctable type of error occurs before the uncorrectable type of error. Therefore, for each error true value in the first error sequence, the corresponding error occurrence time can be obtained as the target error occurrence time, and the error sample located before the target error occurrence time can be obtained from the second error sequence as the error sample corresponding to the error true value. Taking any historical first error in the first error sequence as an example, optionally, the error occurrence time of the historical first error is determined as the target error occurrence time, and a sliding time window is used to select multiple historical second errors located before the target error occurrence time in the first error sequence corresponding to each of the multiple channel areas as the error samples corresponding to the historical first error. According to the historical first error and its error samples, a group of training samples corresponding to the historical first error is determined. For example, the memory is a 9x4 type DDR5 memory, and the 4 data transmission channels contained in the memory are divided into a first channel area composed of DQ0 and DQ1, and a second channel area composed of DQ2 and DQ3. Assuming that the target error occurrence time of the error true value a in the first error sequence is Ta, a sliding time window can be used to select multiple groups of error samples located before the target error occurrence time Ta in the first error sequence in the first channel area as a group of error samples of the error sample a; and select multiple groups of error samples located before the target error occurrence time Ta in the first error sequence in the second channel area as another group of error samples of the error sample a.

[0080] Based on the above implementation, multiple groups of error samples corresponding to each error true value in the first error sequence can be obtained, and each error true value and its corresponding multiple groups of error samples can be input into the error prediction model. The error prediction model can learn the intrinsic connection between the error sample and the error true value under the supervision of the error true value, so as to learn to predict the probability of uncorrectable errors based on the input correctable error statistics. Taking any error true value as an example, during the training process, multiple groups of error samples corresponding to the error true value can be input into the prediction model, and the error prediction values ​​output by the prediction model for the multiple groups of error samples can be obtained. The error prediction value is used to represent the predicted probability of uncorrectable errors. According to the gap between the error prediction values ​​corresponding to each of the multiple groups of error samples and the error true value, the prediction loss of the prediction model can be calculated. If the prediction loss of the model is greater than the set threshold, the parameters of the prediction model can be adjusted, and the iterative training is repeated until the training loss of the prediction model gradually converges to the set threshold range.

[0081] When the training loss of the prediction model is less than or equal to the set threshold, the prediction model can be output and run online. In actual application scenarios, each time a correctable error occurs in any channel area, the probability of an uncorrectable error occurring in the target data chip can be predicted based on the error statistics corresponding to the channel area and its adjacent channel areas. Based on the probability of uncorrectable errors occurring in multiple target data chips, the probability of uncorrectable errors occurring in the memory as a whole can be calculated. If the probability of an uncorrectable error occurring in the memory is greater than the set probability threshold, the task that uses the memory can be migrated to other devices to reduce the impact on the task.

[0082] Generally, the errors in the memory include single-bit errors and multi-bit errors. A multi-bit error means that the data where the error occurs is 1 bit. A multi-bit error means that the data where the error occurs is greater than or equal to two bits. A single-bit error cannot exceed the isolation boundary, so it is not used to calculate the isolation success rate. The following continues to take the target data chip as an example.

[0083] In other optional embodiments, the number of multi-bit errors corresponding to each of the multiple channel regions in the target data chip can be determined from the second error statistics data corresponding to each of the multiple channel regions in the target data chip after the update; and the number of multi-bit errors corresponding to the target data chip can be determined from the first error statistics data corresponding to the updated target data chip. The number of multi-bit errors corresponding to each of the multiple channel regions in the target data chip is accumulated to obtain the total number of multi-bit errors corresponding to the multiple channel regions in the target data chip. According to the ratio of the total number of multi-bit errors corresponding to the multiple channel regions in the target data chip to the number of multi-bit errors occurring in the target data chip, the isolation success rate of the isolation boundary of the target data chip is determined. Among them, the isolation success rate is used to evaluate the isolation effect of the isolation boundary of different channel regions in the target data chip. The higher the isolation success rate, the better the isolation effect of the isolation boundary and the stronger the stability of the target data chip. Taking the 9x4 type DDR5 memory as an example, the isolation success rate can be expressed as: (E(DQ01)+E(DQ23)) / E0. Among them, E(DQ01) is the number of correctable errors in the channel area where DQ0 and DQ1 are located, E(DQ23) is the number of multi-bit correctable errors in the channel area where DQ2 and DQ3 in the target data chip are located, and E0 is the total number of multi-bit errors occurring in the target data chip.

[0084] According to the isolation success rate, the boundary isolation performance analysis information of the target data chip is output. The boundary isolation performance analysis information can be used as a reference for selecting the target data chip. For example, when selecting a 9x4 type DDR5 memory for a computer device, a memory model with the best boundary isolation between the two transmission channels can be selected, thereby greatly reducing the probability of uncorrectable errors in the 9X4 type memory from the source and improving the stability of the computer device.

[0085] like Figure 6 As shown, taking DDR5 memory as an example, for 10x4 memory bars, the expected fault boundary is 2DQ, and for 9x4 memory bars, the expected fault boundary is 1DQ. In some scenarios, for 9x4 type memory, information data units can be extracted in an 8burst*1DQ manner to achieve the expectation of a fault boundary of 1DQ. In other scenarios, for 9x4 type memory, information data units can be extracted in a 4burst*2DQ manner to achieve the expectation of a fault boundary of 2DQ. When the fault boundary isolation success rate of 2DQ of a 9x4 memory bar reaches 100%, the stability of the 9x4 memory can be close to that of the 10x4 memory.

[0086] In some optional embodiments, after performing abnormal prediction and / or performance analysis on the target data chip based on the above-mentioned embodiments, the corresponding results may be output. Optionally, the prediction result of abnormal prediction of the target data chip may be obtained and the prediction result may be displayed. Optionally, the analysis result of performance analysis of the target data chip may be obtained and the analysis result may be displayed. Optionally, an early warning message may be sent to a designated terminal device based on the result of the abnormal prediction and / or the result of the performance analysis. The above-mentioned optional embodiments may be executed separately or in combination, and this embodiment does not limit them.

[0087] The verification data processing method of the memory provided in the embodiment of the present application can be applied in cloud computing scenarios. With the development of cloud computing, the shared cloud IAAS (Infrastructure as a service) service can provide cloud customers with flexible computing power, convenient and cost-effective use experience. Figure 7 The verification data processing method provided in this application is further illustrated, such as Figure 7 As shown, the method includes modules such as hardware chip requirements, DDR platform reporting, key data capabilities, memory bar selection, and stability management. Based on the above modules, the memory access operations of the computing nodes in the cloud computing platform can be monitored, verified, and corrected, thereby improving the stability of the cloud computing nodes. Among them, the hardware chip requirement module is used to organize and customize the information data unit according to the channel area during data transmission when determining the use of the RS-8 algorithm of the full cache line. When the bounded fault of a single chip is 100%, in an ideal state, the errors of 4 information data units in a single channel area of ​​a single data chip can be completely corrected by 8 verification units, and then a single verification chip can completely correct the single data chip (single device data correction, SDDC). When the bounded fault of a single chip is less than 100%, the UE can be reduced by selecting the memory bar. Among them, the DDR platform reporting module is used to report different types of faults. The key data capability module is used to monitor bounded faults and provide the monitoring results to the stability management module. The stability management module can establish a fault prediction model based on fault monitoring data to predict fault risks. When a fault occurs, the stability management module can perform fault isolation. The specific method of fault isolation may include: using firmware / hardware to mark the address where the UE error occurs as a risk address, and sending a recoverable UE event to the kernel so that the kernel can perform error recovery.

[0088] Based on this embodiment, the cost of storage can be further optimized and the cost-effectiveness can be improved without sacrificing stability, performance and security, thereby enhancing the service capabilities of the shared cloud.

[0089] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 101 to 104 can be device A; for another example, the execution subject of steps 101 and 102 can be device A, and the execution subject of step 103 can be device B; and so on.

[0090] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0091] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0092] Figure 8 A schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present application is shown. Figure 8 As shown, the electronic device includes: a memory 801 , a processor 802 , a storage controller 803 and a verification module 804 .

[0093] The memory 801 is used to store computer programs and can be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application program or method operating on the electronic device.

[0094] Among them, the memory 801 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as DDR5 memory, static random access memory (Static Random-Access Memory, SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, disk or optical disk. Among them, the storage controller 803 is used to control the memory 801 and process the data exchange between the memory 801 and the processor 802. When the memory 801 is implemented as an internal memory, the storage controller 803 can be implemented as a memory controller.

[0095] The memory 801 includes: a plurality of data chips and at least one verification chip; the data transmission channel of any data chip is divided into a plurality of channel areas, and isolation boundaries are set between different channel areas.

[0096] Among them, the storage controller 803 is used to: respond to a write data instruction, write the target data in the target cache line to multiple data chips in the memory; use the encoding method corresponding to the target data verification algorithm, and encode the target data in the target cache line according to the corresponding channel area when the data is written to the data chip, so as to obtain a first number of verification units and a plurality of information data units corresponding to each of the multiple data chips, and write the first number of verification units and the plurality of information data units corresponding to each of the multiple data chips into the at least one verification chip, so that when the target data corresponding to the target cache line is read from the multiple data chips, the target data can be verified and / or error-corrected according to the data written in the at least one verification chip.

[0097] Optionally, the multiple information data units corresponding to any target data chip include: a second number of information data units corresponding to each of the multiple channel areas of the target data chip; the first number of verification units, used to verify and / or correct errors of the multiple information data units corresponding to each of the multiple data chips; the second number is smaller than the first number.

[0098] Optionally, the storage controller 803 is also used to: respond to a read data instruction, read the target data corresponding to the target cache line from the multiple data chips, and read the first number of verification units and the multiple information data units corresponding to each of the multiple data chips from the at least one verification chip; for any of the target data chips, use a decoding algorithm corresponding to the target data verification algorithm to decode the multiple information data units corresponding to the target data chip and the first number of verification units; verify the target data in the target cache line according to the decoding result; and, when some of the multiple information data units corresponding to the target data chip have correctable errors, use the decoding result to perform error correction on the data corresponding to the partial information data units with correctable errors in the target cache line. Optionally, the number of the partial information data units with correctable errors is less than or equal to the second number; the second number is half of the first number.

[0099] Optionally, before the storage controller 803 adopts the encoding method corresponding to the target data verification algorithm and encodes the target data in the target cache line according to the channel area corresponding to when the data is written to the data chip, and obtains the first number of verification units and the multiple information data units corresponding to each of the multiple data chips, it is also used to: determine the number of data transmission channels contained in a single channel area according to the bit width information of the memory and the setting position of the isolation boundary; determine the number of target channels contained in a single information data unit according to the number of data transmission channels contained in the single channel area; determine the number of target bursts contained in a single information data unit according to the encoding unit length corresponding to the encoding method and the target number of channels; establish a connection relationship between the communication pin of the verification module corresponding to the target data verification method and the multiple data transmission channels contained in each of the multiple data chips according to the target number of channels, the target number of bursts and the set burst reading method; accordingly,

[0100] Optionally, when the storage controller 803 adopts the encoding method corresponding to the target data verification algorithm and encodes the target data in the target cache row according to the channel area corresponding to when the data is written to the data chip, and obtains a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips, it is specifically used to: utilize the verification module to extract data from the bursts generated by the write operation of the target data in the target cache row on the plurality of data chips according to the connection relationship between the pre-established communication pins and the plurality of data transmission channels respectively contained in the plurality of data chips, and obtain a plurality of information data units corresponding to each of the plurality of data chips; utilize a preset generating polynomial to generate a first number of verification units according to the plurality of information data units corresponding to each of the plurality of data chips.

[0101] Optionally, when the storage controller 803 determines the number of target channels included in a single information data unit based on the number of data transmission channels included in the single channel area, it is specifically used to: determine that the number of target channels included in the single information data unit is less than or equal to the number of data transmission channels included in the single channel area.

[0102] Optionally, after verifying the target data in the target cache line according to the decoding result, the storage controller 803 is also used to: if it is determined according to the verification result that the target data chip has an uncorrectable first error, then, according to the verification result, determine from the multiple information data units of the target data chip a target information data unit in which a correctable second error exists when the first error occurs; in the target data chip, obtain the target storage address where the erroneous data corresponding to the second error is located; add a risk mark to the target storage address, and write the target storage address with the risk mark into a designated storage address segment in the memory; determine the error risk level according to the operation type of the memory when the first error occurs and / or the state of the processor corresponding to the memory; and send an error handling event to the kernel according to the error risk level, so that the kernel reads the target storage address with the risk mark from the designated storage address segment, and performs a risk handling operation on the erroneous data in the target storage address according to the error risk level.

[0103] Optionally, when the storage controller 803 determines the error risk level based on the operation type of the memory and / or the state of the processor corresponding to the memory when the first error occurs, it is specifically used to: if when the first error occurs, the operation type of the memory is a read operation, and the processor is in a normal state, then the error risk level is determined to be: recoverable level; if when the first error occurs, the operation type of the memory is a non-read operation, then the error risk level is determined to be: no impact level.

[0104] Optionally, the processor 802 is specifically used to: execute computer instructions in the memory 801 to: update first error statistics corresponding to the target data chip according to the error occurrence time of the first error; and update second error statistics corresponding to each of the multiple channel areas in the target chip according to at least the channel area corresponding to the target verification unit and the error occurrence time of the second error; perform abnormality prediction and / or performance analysis on the target data chip according to the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target chip.

[0105] Optionally, when the processor 802 performs an abnormality prediction on the target data chip based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, the processor 802 is specifically used to: determine multiple groups of training samples based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; any group of training samples includes: any uncorrectable type of historical first error corresponding to the target data chip and a correctable type of historical second error that occurred in multiple channel areas in the target data chip before the historical error occurred; using the uncorrectable type of historical first error in the multiple groups of training samples as a supervisory signal, and performing supervised training on an error prediction model based on the multiple groups of training samples; the error prediction model is used to predict the probability of an uncorrectable error occurring in the target data chip based on the second error statistics of each of the multiple channel areas in the target data chip.

[0106] Optionally, when the processor 802 determines multiple groups of training samples based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, it is specifically used to: determine the first error sequence corresponding to the target data chip based on the updated first error statistics; the first error sequence includes: multiple historical first errors of an uncorrectable type arranged according to the error occurrence time; determine the second error sequence corresponding to each of the multiple channel areas in the target data chip based on the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; the second error sequence corresponding to any channel area includes: multiple historical second errors of a correctable type that occurred in the channel area arranged according to the error occurrence time; for any historical first error in the first error sequence, determine the error occurrence time of the historical first error as the target error occurrence time; using a sliding time window, in the first error sequence corresponding to each of the multiple channel areas in the target data chip, select multiple historical second errors located before the target error occurrence time as error samples corresponding to the historical first error; and determine a group of training samples corresponding to the historical first error based on the historical first error and its error samples.

[0107] Optionally, when the processor 802 performs performance analysis on the target data chip based on the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip, the processor 802 is specifically used to: determine the number of multi-bit errors corresponding to each of the multiple channel areas in the target data chip from the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; and determine the number of multi-bit errors corresponding to the target data chip from the updated first error statistics; accumulate the number of multi-bit errors corresponding to each of the multiple channel areas in the target data chip to obtain the total number of multi-bit errors corresponding to the multiple channel areas in the target data chip; determine the isolation success rate of the isolation boundary of the target data chip based on the ratio of the total number of multi-bit errors corresponding to the multiple channel areas in the target data chip to the number of multi-bit errors corresponding to the target data chip; and output the boundary isolation performance analysis information of the target data chip based on the isolation success rate.

[0108] Optionally, after performing abnormality prediction and / or performance analysis on the target data chip according to the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target chip, the processor 802 is also used to: obtain a prediction result of abnormality prediction on the target data chip and display the prediction result; and / or obtain an analysis result of performance analysis on the target data chip and display the analysis result; and / or send an early warning message to a designated terminal device based on the result of the abnormality prediction and / or the result of the performance analysis.

[0109] Further, if Figure 8 As shown, the electronic device also includes: a power supply component 805 and other components. Figure 8 Only some components are shown schematically, which does not mean that the electronic device only includes Figure 8 Components shown.

[0110] The power supply component 805 is used to provide power to various components of the device where the power supply component is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing and distributing power to the device where the power supply component is located.

[0111] In this embodiment, when writing target data in a target cache line to multiple data chips in a memory, an encoding method corresponding to a target data verification algorithm may be used, and the target data in the target cache line may be encoded according to the channel area corresponding to when the data is written to the data chip, to obtain a first number of verification units and multiple information data units corresponding to each of the multiple data chips. Among them, encoding the target data in the target cache line as a whole can effectively reduce the amount of verification data. In the data reading stage, the information data units in a single channel area in any target data chip may be verified and / or error corrected according to the first number of verification units. When there is less verification data, the verification and / or error correction of bounded errors within the isolation boundary is achieved, which is beneficial to reduce the cost of the memory while ensuring the stability of the memory.

[0112] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement each step that can be executed by an electronic device in the above method embodiment.

[0113] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM (Compact Disc Read-Only Memory, read-only optical disc read-only memory), optical storage, etc.) containing computer-usable program codes.

[0114] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0115] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0116] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0117] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interface, network interface and memory.

[0118] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0119] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, Parallel Random Access Machine (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, Digital Video Disc (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0120] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0121] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for processing verification data of a memory, characterized in that: The memory includes: a plurality of data chips and at least one verification chip; the data transmission channel of any data chip is divided into a plurality of channel areas, and isolation boundaries are set between different channel areas; the method includes: In response to a write data instruction, write target data in a target cache line to a plurality of data chips in a memory; Adopting an encoding method corresponding to a target data verification algorithm, encoding the target data in the target cache line according to a channel area corresponding to when the data is written into a data chip, to obtain a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips; The first number of check units and the multiple information data units corresponding to each of the multiple data chips are written into the at least one check chip, so that when the target data corresponding to the target cache line is read from the multiple data chips, the target data is checked and / or error corrected according to the data written in the at least one check chip.

2. The method according to claim 1, characterized in that The multiple information data units corresponding to any target data chip include: a second number of information data units corresponding to each of the multiple channel areas of the target data chip; the first number of verification units, used to verify and / or correct errors of the multiple information data units corresponding to each of the multiple data chips; the second number is smaller than the first number.

3. The method according to claim 2, characterized in that Also includes: In response to a read data instruction, read the target data corresponding to the target cache line from the multiple data chips, and read the first number of check units and the multiple information data units corresponding to each of the multiple data chips from the at least one check chip; For any of the target data chips, a decoding algorithm corresponding to the target data verification algorithm is used to decode a plurality of information data units corresponding to the target data chip and the first number of verification units; According to the decoding result, verifying the target data in the target cache line; as well as, When some of the information data units among the multiple information data units corresponding to the target data chip have correctable errors, error correction is performed on data in the target data corresponding to the some of the information data units having the correctable errors using the decoding result.

4. The method according to claim 3, characterized in that The method comprises: adopting an encoding method corresponding to a target data verification algorithm, encoding the target data in the target cache line according to a channel area corresponding to when the data is written into a data chip, and obtaining a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips, including: Determining the number of data transmission channels included in a single channel area according to the bit width information of the memory and the setting position of the isolation boundary; Determining the number of target channels included in a single information data unit according to the number of data transmission channels included in the single channel area; Determining a target burst quantity contained in a single information data unit according to a coding unit length corresponding to the coding mode and the target number of channels; According to the target number of channels, the target number of bursts and the set burst reading mode, a connection relationship between the communication pins of the verification module corresponding to the target data verification method and the multiple data transmission channels respectively included in the multiple data chips is established.

5. The method according to claim 4, characterized in that Adopting the encoding method corresponding to the target data verification algorithm, encoding the target data in the target cache line according to the channel area corresponding to when the data is written into the data chip, and obtaining a first number of verification units and a plurality of information data units corresponding to each of the plurality of data chips, including: Utilizing the verification module, according to the pre-established connection relationship between the communication pins and the multiple data transmission channels respectively included in the multiple data chips, data extraction is performed on the bursts generated by the write operation of the target data in the target cache line on the multiple data chips to obtain multiple information data units corresponding to the multiple data chips respectively; A first number of check units are generated according to a plurality of information data units corresponding to each of the plurality of data chips using a preset generating polynomial.

6. The method according to claim 4, characterized in that Determining the number of target channels included in a single information data unit according to the number of data transmission channels included in the single channel area includes: It is determined that the number of target channels included in a single information data unit is less than or equal to the number of data transmission channels included in a single channel area.

7. The method according to any one of claims 3 to 6, characterized in that: After verifying the target data in the target cache line according to the decoding result, the method further includes: If it is determined according to the verification result that the target data chip has a first error of an uncorrectable type, then according to the verification result, a target information data unit having a second error of a correctable type when the first error occurs is determined from a plurality of information data units of the target data chip; In the target data chip, obtaining a target storage address where error data corresponding to the second error is located; Adding a risk mark to the target storage address, and writing the target storage address with the risk mark into a designated storage address segment in the memory; determining an error risk level according to an operation type of the memory and / or a state of a processor corresponding to the memory when the first error occurs; According to the error risk level, an error handling event is sent to the kernel, so that the kernel reads the target storage address with the risk mark added from the specified storage address segment, and performs a risk handling operation on the error data in the target storage address according to the error risk level.

8. The method according to claim 7, characterized in that Determining an error risk level according to an operation type of the memory and / or a state of a processor corresponding to the memory when the first error occurs includes: If, when the first error occurs, the operation type of the memory is a read operation, and the processor is in a normal state, the error risk level is determined to be: a recoverable level; If the operation type of the memory is a non-read operation when the first error occurs, the error risk level is determined to be: no impact level.

9. The method according to claim 7, characterized in that: Also includes: updating first error statistical data corresponding to the target data chip according to the error occurrence time of the first error; as well as, At least according to the channel area corresponding to the target verification unit and the error occurrence time of the second error, updating the second error statistical data corresponding to each of the plurality of channel areas in the target chip; According to the updated first error statistical data and the updated second error statistical data corresponding to each of the plurality of channel regions in the target chip, abnormality prediction and / or performance analysis is performed on the target data chip.

10. The method according to claim 9, characterized in that According to the updated first error statistics data and the updated second error statistics data corresponding to each of the plurality of channel regions in the target data chip, an abnormality prediction is performed on the target data chip, including: Determine multiple groups of training samples according to the updated first error statistics and the updated second error statistics corresponding to each of the multiple channel areas in the target data chip; any group of training samples includes: any uncorrectable historical first error corresponding to the target data chip and correctable historical second errors that occurred in the multiple channel areas in the target data chip before the historical error occurred; The error prediction model is supervisedly trained based on the multiple groups of training samples using the historical first errors of the uncorrectable type in the multiple groups of training samples as a supervisory signal; the error prediction model is used to predict the probability of uncorrectable errors occurring in the target data chip based on the second error statistics of each of the multiple channel areas in the target data chip.

11. The method according to claim 10, characterized in that Determining a plurality of groups of training samples according to the updated first error statistics data and the updated second error statistics data corresponding to each of the plurality of channel regions in the target data chip, comprising: Determine a first error sequence corresponding to the target data chip according to the updated first error statistical data; the first error sequence includes: a plurality of historical first errors of an uncorrectable type arranged according to the time of error occurrence; Determine the second error sequences corresponding to the plurality of channel areas in the target data chip according to the updated second error statistics data corresponding to the plurality of channel areas in the target data chip; the second error sequence corresponding to any channel area includes: a plurality of correctable historical second errors of the channel area arranged according to the time of error occurrence; For any historical first error in the first error sequence, determining an error occurrence time of the historical first error as a target error occurrence time; Using a sliding time window, in the first error sequences corresponding to the plurality of channel areas in the target data chip, multiple historical second errors located before the time when the target error occurred are selected as error samples corresponding to the historical first errors; According to the first historical error and its error samples, a group of training samples corresponding to the first historical error is determined.

12. The method according to claim 9, characterized in that According to the updated first error statistics data and the updated second error statistics data corresponding to each of the plurality of channel regions in the target data chip, the target data chip is subjected to performance analysis, including: Determine the number of multi-bit errors corresponding to each of the plurality of channel regions in the target data chip from the updated second error statistics corresponding to each of the plurality of channel regions in the target data chip; and determine the number of multi-bit errors corresponding to the target data chip from the updated first error statistics; Accumulating the number of multi-bit errors corresponding to each of the plurality of channel regions in the target data chip to obtain a total number of multi-bit errors corresponding to the plurality of channel regions in the target data chip; Determining an isolation success rate of the isolation boundary of the target data chip according to a ratio of a total number of multi-bit errors corresponding to a plurality of channel regions in the target data chip to a number of multi-bit errors corresponding to the target data chip; According to the isolation success rate, boundary isolation performance analysis information of the target data chip is output.

13. The method according to claim 7, characterized in that After performing abnormality prediction and / or performance analysis on the target data chip according to the updated first error statistics data and the updated second error statistics data corresponding to each of the plurality of channel regions in the target chip, the method further includes: Obtaining a prediction result of abnormality prediction for the target data chip and displaying the prediction result; and / or, Obtaining analysis results of the performance analysis of the target data chip and displaying the analysis results; and / or, According to the result of the abnormality prediction and / or the result of the performance analysis, a warning message is sent to a designated terminal device.

14. An electronic device, characterized in that: include: memories, storage controllers, and processors; The memory is used to store one or more computer instructions; The storage controller and the processor are configured to execute the one or more computer instructions for: performing the steps in the method of any one of claims 1-13.

15. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it can implement the memory verification data processing method described in any one of claims 1 to 13.

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