An open-closed loop smooth switching system based on charge pump phase-locked loop

Abstract

The present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, comprising: a reference clock fault detection module connected to the charge pump phase-locked loop, which detects whether a reference clock fault has occurred and provides reference clock fault indication control; a PLL lock detection module, which performs phase-locked loop lock indication control based on the phase difference between the reference clock's frequency-divided signal and the charge pump output clock's frequency-divided signal; an ADC / DAC control module, which performs auxiliary hold of the charge pump open loop and auxiliary release of the charge pump phase-locked loop from open loop to closed loop; and a PLL control state machine module, which controls the state machine to select clocks, enter hold state, and exit hold state. The present invention can identify fault information as early as possible, realize open-closed loop conversion of the charge pump phase-locked loop, and enter or exit hold state. Furthermore, the deviation between the charge pump's reacquired reference clock and the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting subsequent circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of clock chips, and in particular to an open-closed loop smooth switching system based on a charge pump phase-locked loop. Background Art

[0002] A charge pump phase-locked loop (PLL) is a widely used PLL architecture in modern communication systems, offering advantages such as high speed, low power consumption, low jitter, and low cost. It primarily consists of a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). This PLL is widely used in circuits such as frequency synthesis and clock recovery. Its basic principle is to control the on / off state of the charge pump using the phase and frequency differences between an external reference signal and the output signal of a frequency divider. Under the control of the phase detector, the charge pump distributes charge to the loop filter, thereby adjusting the VCO output frequency to synchronize it with the reference frequency.

[0003] Charge pump phase-locked loops (PLLs) are widely used in many fields, including communications and microprocessors, due to their advantages such as high open-loop gain, high acquisition speed, high stability, and zero static phase error. When the active reference clock of a charge pump phase-locked loop (PLL) fails and disappears, and the PLL remains in an open loop, existing solutions often result in excessive frequency deviations in the PLL's output clock. These deviations can cause FIFO overflows in downstream circuits and communication links, or the PLL itself to lose lock. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide an open-closed loop smooth switching system based on a charge pump phase-locked loop, which can identify fault information as early as possible and put the charge pump into the three-state in advance. At this time, the charge pump PLL is switched from the closed loop to the open loop state. When the reference clock is stable, the present invention controls the charge pump phase-locked loop to exit the holding state. At this time, the PLL is switched from the open loop state to the closed loop state. In the process, the charge pump re-acquires the reference clock (from open loop to closed loop) and the deviation from the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting the subsequent circuits.

[0005] To achieve the above-mentioned object, the present invention provides the following solution: an open-closed loop smooth switching system based on a charge pump phase-locked loop, comprising a reference clock fault detection module, a PLL lock detection module, an ADC / DAC control module and a PLL control state machine module connected to the charge pump phase-locked loop;

[0006] The reference clock fault detection module is used to detect whether a reference clock fault occurs and to perform reference clock fault indication control;

[0007] The PLL lock detection module is used to perform lock indication control of the phase-locked loop according to the phase difference between the frequency-divided signal of the reference clock and the frequency-divided signal of the charge pump phase-locked loop output clock;

[0008] The ADC / DAC control module is used to assist in maintaining the charge pump open loop and assist in releasing the charge pump phase-locked loop from open loop to closed loop;

[0009] The PLL control state machine module is used to control the state machine to perform clock selection, enter the hold state and exit the hold state, thereby realizing the control of the open-loop and closed-loop indication of the charge pump phase-locked loop.

[0010] Optionally, the reference clock fault detection module includes:

[0011] A clock constraint unit, configured to set a reference clock frequency greater than 1 / 2 times the main clock frequency as a first clock constraint, and a main clock frequency greater than 1 / 2 times the reference clock frequency as a second clock constraint;

[0012] A fault judgment unit is used to judge whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges. If not, the reference clock is judged to be faulty and the clock fault signal of the corresponding channel is set to 1;

[0013] The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning indicating that the master clock frequency is too low is issued.

[0014] Optionally, the PLL lock detection module includes:

[0015] a phase-locked loop locking unit, configured to, when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is less than 4 ns, determine whether a flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is a continuous low-level signal during a period in which a lock counter continuously counts 2^n divided clock cycles of the reference clock, and, if so, issue a phase-locked loop locking indication;

[0016] The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns, and the flag signal of the excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal. The lock counter is cleared and the charge pump phase-locked loop returns to the re-lock counting state.

[0017] Optionally, the ADC / DAC control module includes:

[0018] The first auxiliary unit is used to sample the oscillator control voltage value during the closed loop period of the charge pump phase-locked loop;

[0019] The second auxiliary unit is used to use the oscillator control voltage value sampled by the DAC output after the charge pump switches from closed loop to open loop to maintain the frequency stability of the oscillator.

[0020] Optionally, the PLL control state machine module includes:

[0021] The idle unit is used to receive the startup signal of the entire system and enter the initialization state;

[0022] An initialization unit, configured to preload a configuration, initialize the control signal output by the state machine master clock to the analog terminal according to the register configuration, and reset each counter in the state machine to 0;

[0023] a lock counting state unit, configured to determine whether a phase difference between a divided clock signal of a reference clock and a divided clock signal of a PLL output clock is continuously less than 4 ns during a period in which a lock counter continuously counts 2^n divided clock cycles of the reference clock; if so, the clock lock flag output by the PLL lock detection module is 1, and the PLL enters a locked state;

[0024] A locking unit, configured to exit the locked state when a higher priority reference clock recovers to a fault-free state or the clock is locked; and to give priority to recovering the higher priority reference clock when both the higher priority reference clock and the clock are locked simultaneously;

[0025] A first hold state unit is configured to restore the hold state entered by a higher priority clock, output a control signal from a CP terminal to restore the hold state of the higher priority clock, maintain the CP in a tri-state, maintain the PLL in an open-loop state, and then select a reference clock from high to low according to a preset clock priority table to exit the hold state;

[0026] The second holding state unit is used to enter the holding state when the clock fault signal jumps to 1, keep the CP in a tri-state, and output the CP terminal control signal to select other reference clocks and exit the holding state;

[0027] Reset divider unit, used to reset the R1 / N1 divider state and control the reset of the R1 / N1 divider when the charge pump phase-locked loop switches from open loop to closed loop;

[0028] The DAC auxiliary release unit is used to use the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, draining the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC, thereby reducing the impact on the output frequency of the charge pump phase-locked loop and completing the DAC auxiliary release of the charge pump phase-locked loop from open loop to closed loop.

[0029] Optionally, the state machine main clock is the main frequency of the entire digital circuit, and the control signal output by the state machine to the analog end includes a charge pump control signal, a DAC analog circuit control signal, and an R1 / N1 divided reset signal.

[0030] Optionally, the locking unit includes:

[0031] The priority recovery subunit is used to preset the clock priority control circuit, monitor in real time whether a higher priority clock is recovered, and if so, enter the holding state of the higher priority clock to complete the switching of the higher priority reference clock;

[0032] The clock lock subunit is used to enter the holding state of the current clock fault when the flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is at a high level, the clock lock flag is locked and set to 0, or the clock fails and the clock fault signal is 1.

[0033] Optionally, the PLL control state machine module further includes:

[0034] a clock selection unit, configured to determine whether the current clock has recovered after a configured clock recovery wait time, and if so, continue to use the current clock; if not, select a reference clock with a higher priority and no fault according to the clock priority table; and when all clocks are unavailable, maintain the current clock in a fault hold state until a reference clock is recovered;

[0035] The hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

[0036] Optionally, the waiting for zero phase error mode waits for the low phase error flag output by the charge pump phase-locked loop to return to 0, and then the charge pump exits the hold state;

[0037] The DAC auxiliary release mode waits for the clock fault signal of the corresponding channel to be 0, resets the R1 / N1 divider, and diverts the large charge applied to the loop filter potential to the linear regulator through the low-impedance path inside the DAC, thereby reducing the impact on the output frequency of the charge pump phase-locked loop, and completing the DAC auxiliary release state exit mode.

[0038] The present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, which discloses the following technical effects:

[0039] 1. The present invention supports automatic switching of the reference clock of the charge pump phase-locked loop (PLL). For example, four reference clocks can be configured, and each clock can be enabled or disabled by the user. The priority of the reference clock can also be set. If the current clock fails, the system can switch to the next priority reference clock. If a higher priority clock recovers, the system can also automatically switch back to the higher priority clock.

[0040] 2. The number of clock cycles (used as a lock indicator) at which the PFD phase error is below the threshold during the lock detection process of the present invention is user-configurable.

[0041] 3. The reference clock fault detection module (LOSDetector module) of the present invention will identify the reference clock fault information as early as possible and enter the hold state through the PLL control state machine (PLL1 FSM module) before the PLL phase detector PFD1 or charge pump CP1 is affected.

[0042] 4. The present invention is in the hold state (clock failure, PLL open loop), because the state is entered due to clock failure, the user can configure to wait for the clock to recover (time is configurable). If the clock recovers, continue to use this reference clock. If not, select the next priority clock according to the priority table configured in advance by the user.

[0043] 5. The present invention proposes two methods for smoothly exiting the PLL open-loop hold state (waiting for zero phase error and DAC auxiliary release) to control the charge pump phase-locked loop PLL to exit the tri-state, so as to minimize the phase / frequency drop when the PLL is converted from open-loop to closed-loop.

[0044] 6. The core of the present invention is that after the PLL re-switches the reference clock, the frequency deviation caused by the closed-loop re-lock is reduced to less than 0.15ppm, and the reference clock switching is completed smoothly without affecting the subsequent circuits.

[0045] 7. The present invention supports enabling the DAC circuit to hold when the PLL is in the open-loop hold state, so that the CP terminal voltage is maintained at the average value during the previous closed-loop state.

[0046] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 A schematic diagram of the system architecture provided by an embodiment of the present invention;

[0049] Figure 2 A circuit diagram of a charge pump and an open-closed loop smooth switching system provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of the state transition of a PLL control state machine provided in an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the clock selection design process provided by an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of the clock selection logic flow provided by an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of the state transition design process of a digital circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0055] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] like Figure 1-2 As shown, the present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, including a reference clock fault detection module (LOSDetector), a PLL lock detection module (Lock_detect), an ADC / DAC control module (DAC_ctrl) and a PLL control state machine module (PLL1 FSM) connected to the charge pump phase-locked loop.

[0057] 1. Reference clock failure detection module (LOSDetector)

[0058] Used to detect whether the reference clock has failed and control the clock failure flag. The reference clock failure detection module includes:

[0059] The fault judgment unit is used to determine whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges (within three master clock cycles). If not, the reference clock is judged to be faulty and the clock fault signal (los_clkx (x = 0 or 1 or 2 or 3) of the corresponding channel is set to 1.

[0060] The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning indicating that the master clock frequency is too low is issued.

[0061] The clock constraints of this module design are: 2 times the reference clock frequency (f_clkinx / 2) < the state machine main clock frequency (f_mainclk) < 2 times the reference clock frequency (f_clkinx*2)

[0062] 2. PLL lock detection module (Lock_detect)

[0063] It is used to determine the phase difference between the divided frequency signal of the reference clock and the divided frequency signal of the charge pump phase-locked loop output clock, and to control the lock indication of the phase-locked loop based on the determination result. The PLL lock detection module includes:

[0064] The phase-locked loop (PLL) lock unit is designed to prevent the phase detector from outputting a high-level signal (ph_err) indicating an excessive phase difference between the fref and fdiv clocks when the phase difference between the divided reference clock (fref signal) and the divided PLL output clock (fdiv) is less than 4ns. The lock counter continuously counts 2^n cycles of the divided reference clock (fref signal) to determine whether the excessive phase difference between the divided reference clock (fref) and the divided PLL output clock (fdiv) remains low. If so, a PLL lock indication is issued. The number of consecutive counting cycles is configurable based on the PLL loop lock time, which is determined by the loop bandwidth and parameters of the PLL analog circuit.

[0065] The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns. The flag signal of excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal, and the lock counter is cleared and the charge pump returns to the re-lock counting state.

[0066] 3. ADC / DAC control module (DAC_ctrl)

[0067] It is used to sample the voltage value of the charge pump phase-locked loop, assist in holding the open loop, and assist in releasing the open loop to the closed loop. The ADC / DAC control module includes:

[0068] The first auxiliary unit is used to sample the oscillator control voltage value during the closed-loop period of the charge pump.

[0069] The second auxiliary unit is used to use the oscillator control voltage value sampled by the DAC output to maintain the frequency stability of the oscillator after the charge pump switches from closed loop to open loop when a reference clock failure occurs.

[0070] 4. PLL control state machine module (PLL1 FSM)

[0071] Figure 3 This is the state transition diagram of the PLL control state machine, such as Figure 3 As shown, the PLL control state machine is used to control the state jump of the charge pump to enter and exit the clock selection hold state. The PLL control state machine module includes:

[0072] 4.1 Idle Unit IDLE

[0073] Idle state, receives the startup signal of the entire system, and enters the initialization state.

[0074] 4.2 Initialization Unit INIT

[0075] Initialization state (pre-load configuration), according to the register configuration, initialize the control signal output by the state machine FSM to the analog terminal, and reset the values ​​of each counter in the state machine FSM to 0;

[0076] The state machine's master clock is the main frequency of the entire digital circuit. The reference clock fault detection module (LOSDetector), PLL lock detection module (Lock_detect), ADC / DAC control module (DAC_ctrl), and PLL control state machine module (PLL1 FSM) all operate at this frequency. The control signals output by the state machine to the analog terminal include charge pump control signals en_up / en_dn, reset signals for the R1 / N1 divider, and DAC analog circuit control signals.

[0077] 4.3 Locking Count State Unit LOCKING

[0078] It is used to determine whether the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is continuously less than 4ns during the period when the lock counter continuously counts 2^n divided clock cycles of the reference clock. If so, the clock lock flag output by the PLL lock detection module is 1 and the system enters the locked state.

[0079] The lock count state is entered when the clock fault signal (los_clkx) of the corresponding channel is 0 (guaranteed by design). A transition of los_clkx to 1 is an extreme case. A transition to 1 can cause the device to enter the HOLDOVER_ERR state or remain in this state, depending on user configuration. The LOCKED state is entered when the clock lock flag (ld_flag) output by the PLL lock detection module (lock_detect module) is 1.

[0080] 4.4 Locking unit LOCKED

[0081] Locked state. When a higher priority reference clock exists or the clock is out of lock, it will exit the locked state. When a higher priority reference clock and clock out of lock exist at the same time, the higher priority reference clock will be restored first. The locking unit includes:

[0082] 1) Priority recovery subunit

[0083] This state has a built-in clock priority control circuit, which can monitor in real time whether a higher priority clock is recovered. If so, the circuit enters the higher priority hold state HOLDOVER_PRE to complete the switching of the higher priority reference clock.

[0084] 2) Clock lock subunit

[0085] At this point, the analog PFD outputs a square wave pulse, ph_err (a signal indicating a large phase difference between the fref and fdiv clocks), resetting the lock counter module (lock_detect module). The flag (ld_flag) output by this module is set to 0, indicating a loss of lock. Alternatively, if a clock failure occurs and the reference clock failure detection module (los_detect module) outputs a clock failure signal (los_clkinx) of the corresponding channel to 1, the device enters the HOLDOVER_EER hold state. Users can also configure the device to not enter the hold state and return to the LOCKING state.

[0086] 4.5 First Hold State Unit HOLDOVER_PRE

[0087] Figure 4 Design a flow chart for clock selection, such as Figure 4As shown, the first holding state unit is used to enter and maintain the restoration of a higher priority state. The restoration of the higher priority holding state outputs a control signal from the CP end, keeps the CP in a tri-state, keeps the PLL in an open-loop state, and then selects the clock from high to low according to the preset clock priority table to jump out of the state.

[0088] Because a higher-priority clock must be recovered when entering this state (the corresponding channel's clock failure signal los_clkinx = 0), this state can be exited by selecting a clock from high to low according to the priority table. In this state, the control signals output from the CP terminal (en_up set to 0, en_dn set to 0) keep the CP in tri-state, and the PLL is in open-loop state.

[0089] 4.6 Second Hold State Unit HOLDOVER_EER

[0090] When the clock fault signal jumps to 1, it enters and maintains the current clock fault state, keeps the CP in tri-state, sets the output CP control signal en_up to 0, sets en_dn to 0, keeps the CP in tri-state, keeps the PLL in open-loop state, selects other fault-free clocks according to the configuration, and exits the hold state.

[0091] Among them, HOLDOVER_EER can wait for the clock to recover, and HOLDOVER_PRE state is entered to switch to a higher priority clock without waiting time.

[0092] 4.7 Reset divider unit HOLDQUIT_RES

[0093] Used to reset the R1 / N1 divider state, and after resetting the divider, control the charge pump from open loop to closed loop.

[0094] 4.8DAC auxiliary release unit HOLDQUIT_DAC

[0095] It is used to use the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, and drain the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC, so as to reduce the impact on the output frequency of the charge pump phase-locked loop, and complete the DAC-assisted release of the charge pump phase-locked loop from open loop to closed loop.

[0096] 4.9 Clock Selection Unit

[0097] Figure 5 Select the logic flow chart for the clock, such as Figure 5As shown, if the hold state is entered due to a clock failure, the user can configure a wait time for the clock to recover (the time is configurable). After waiting for the configured time, the current clock is determined to have recovered. If it is, the current clock will continue to be used. If it is not, a higher-priority, healthy clock will be selected according to the clock priority table. If all clocks are unavailable, the current hold state will be maintained until a clock recovers.

[0098] 4.10 Exiting the Unit in Hold State

[0099] Figure 6 Design a flow chart for the state flow of a digital circuit, such as Figure 6 As shown, the hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

[0100] 1) Waiting for zero phase error mode

[0101] Wait for the corresponding channel's clock fault signal (los_clkx) to reach 0 and for the PFD to reach a low phase error. The PLL will output a low phase error flag (cycleslip). Cycleslip occurs because of the frequency difference between fref and fdiv. Whether fref is slightly greater than fdiv or slightly less than fdiv, the rising edges of both frequencies will progress from slightly lagging (or leading) to slightly advancing (or lagging). This process is the pulse width of the cycleslip. Therefore, waiting for cycleslip to return to 0 before exiting the PLL hold state can briefly charge the ADC / DAC control module's hold voltage (vtune voltage) (or help the vtune voltage release a small amount of charge for a short period of time), helping the fdiv frequency converge more quickly to the fref frequency in the subsequent lock cycle.

[0102] 2) DAC assisted release method

[0103] Wait for the corresponding channel's clock fault signal (los_clkx) to reach 0, reset the R1 / N1 divider, and release the DAC auxiliary. This DAC auxiliary release exit method diverts the high charge applied to the loop filter potential through a low-impedance path within the DAC to the linear regulator, minimizing its impact on the charge pump PLL output frequency (f_vcxo). The impedance of this diversion path is increased bit by bit using the frequency tap of fref.

[0104] Therefore, the present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, which can monitor the active reference clock of the charge pump phase-locked loop, identify fault information as early as possible, and put the charge pump into the three-state in advance. At this time, the PLL switches from the closed loop to the open loop state. When the reference clock is stable, the present invention controls the charge pump phase-locked loop to exit the holding state. At this time, the PLL switches from the open loop state to the closed loop state. In the process, the charge pump re-acquires the reference clock (from open loop to closed loop) and the deviation from the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting the subsequent circuits.

[0105] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0106] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. An open-closed loop smooth switching system based on a charge pump phase-locked loop, characterized in that: It includes a reference clock fault detection module connected to the charge pump phase-locked loop, a PLL lock detection module, an ADC / DAC control module and a PLL control state machine module; The reference clock fault detection module is used to detect whether a reference clock fault occurs and to perform reference clock fault indication control; The PLL lock detection module is used to perform lock indication control of the phase-locked loop according to the phase difference between the frequency-divided signal of the reference clock and the frequency-divided signal of the charge pump phase-locked loop output clock; The ADC / DAC control module is used to assist in maintaining the charge pump open loop and assist in releasing the charge pump phase-locked loop from open loop to closed loop; The PLL control state machine module is used to control the state machine to perform clock selection, enter the hold state, and exit the hold state, thereby realizing the control of the open-loop and closed-loop indication of the charge pump phase-locked loop; The PLL control state machine module includes: The idle unit is used to receive the startup signal of the entire system and enter the initialization state; An initialization unit, configured to preload a configuration, initialize the control signal output by the state machine master clock to the analog terminal according to the register configuration, and reset each counter in the state machine to 0; a lock counting state unit, configured to determine whether a phase difference between a divided clock signal of a reference clock and a divided clock signal of a PLL output clock is continuously less than 4 ns during a period in which a lock counter continuously counts 2^n divided clock cycles of the reference clock; if so, the clock lock flag output by the PLL lock detection module is 1, and the PLL enters a locked state; A locking unit, configured to exit the locked state when a higher priority reference clock recovers to a fault-free state or the clock is locked; and to give priority to recovering the higher priority reference clock when both the higher priority reference clock and the clock are locked simultaneously; A first hold state unit is configured to restore the hold state entered by a higher priority clock, output a control signal from a CP terminal to restore the hold state of the higher priority clock, maintain the CP in a tri-state, maintain the PLL in an open-loop state, and then select a reference clock from high to low according to a preset clock priority table to exit the hold state; The second holding state unit is used to enter the holding state when the clock fault signal jumps to 1, keep the CP in a tri-state, and output the CP terminal control signal to select other reference clocks and exit the holding state; Reset divider unit, used to reset the R1 / N1 divider state and control the reset of the R1 / N1 divider when the charge pump phase-locked loop switches from open loop to closed loop; The DAC auxiliary release unit is used to use the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, draining the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC to reduce the impact on the output frequency of the charge pump phase-locked loop, completing the DAC auxiliary release of the charge pump phase-locked loop from open loop to closed loop; The PLL control state machine module also includes: a clock selection unit, configured to determine whether the current clock has recovered after a configured clock recovery wait time, and if so, continue to use the current clock; if not, select a reference clock with a higher priority and no fault according to the clock priority table; and when all clocks are unavailable, maintain the current clock in a fault hold state until a reference clock is recovered; The hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

2. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 1, characterized in that: The reference clock fault detection module includes: A clock constraint unit, configured to set a reference clock frequency greater than 1 / 2 times the main clock frequency as a first clock constraint, and a main clock frequency greater than 1 / 2 times the reference clock frequency as a second clock constraint; A fault judgment unit is used to judge whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges. If not, the reference clock is judged to be faulty and the clock fault signal of the corresponding channel is set to 1; The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning indicating that the master clock frequency is too low is issued.

3. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 2, characterized in that: The PLL lock detection module includes: a phase-locked loop locking unit, configured to, when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is less than 4 ns, determine whether a flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is a continuous low-level signal during a period in which a lock counter continuously counts 2^n divided clock cycles of the reference clock, and, if so, issue a phase-locked loop locking indication; The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns, and the flag signal of the excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal. The lock counter is cleared and the charge pump phase-locked loop returns to the re-lock counting state.

4. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 3, characterized in that: The ADC / DAC control module includes: The first auxiliary unit is used to sample the oscillator control voltage value during the closed loop period of the charge pump phase-locked loop; The second auxiliary unit is used to use the oscillator control voltage value sampled by the DAC output after the charge pump switches from closed loop to open loop to maintain the frequency stability of the oscillator.

5. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 4, characterized in that: The state machine master clock is the main frequency of the entire digital circuit. The control signal output by the state machine to the analog terminal includes a charge pump control signal, a DAC analog circuit control signal, and a reset signal of R1 / N1 division.

6. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 5, characterized in that: The locking unit comprises: The priority recovery subunit is used to preset the clock priority control circuit, monitor in real time whether a higher priority clock is recovered, and if so, enter the holding state of the higher priority clock to complete the switching of the higher priority reference clock; The clock lock subunit is used to enter the holding state of the current clock fault when the flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is at a high level, the clock lock flag is locked and set to 0, or the clock fails and the clock fault signal is 1.

7. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 6, characterized in that: The waiting for zero phase error mode waits for the low phase error flag output by the charge pump phase-locked loop to return to 0, and then the charge pump exits the hold state; The DAC auxiliary release mode waits for the clock fault signal of the corresponding channel to be 0, resets the R1 / N1 divider, and diverts the large charge applied to the loop filter potential to the linear regulator through the low-impedance path inside the DAC, thereby reducing the impact on the output frequency of the charge pump phase-locked loop, and completing the DAC auxiliary release state exit mode.

Images