Data processing method and device

Abstract

The embodiment of the invention discloses a data processing method which is applied to the field of optical communication. The method comprises the steps of obtaining first data; obtaining a first bit set according to the first data and the added bits; the first bit set is subjected to forward error correction (FEC) coding and interleaving to obtain a pre-framing bit set, in the first bit set, each a bits are subjected to FEC coding to obtain b coded bits, a and b are positive integers, b / a is any one of 96 / 79, 80 / 63 and 112 / 95, and the pre-framing bit set is used for generating a superframe. The superframe formed according to the invention has stronger error correction capability, and can be suitable for transmission systems of 800Gbit / s, 1.6 Tbit / s and even higher speed.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical communications, and in particular to a data processing method and related devices for optical communications. Background Art

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing toward high-capacity, packet-based, and intelligent technologies. Coherent optical communication systems utilize the amplitude, phase, polarization, and frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems typically employ efficient forward error correction (FEC) codes to combat optical impairments during transmission and maintain sufficiently low bit error rates over long distances.

[0003] For future metropolitan area telecom transmission and metropolitan area Data Center Interconnect (DCI) interconnection scenarios, such as 1.6T-ZR, the baud rate will reach 240GBit / s and above, taking into account hexadecimal dual polarization 16-state Quadrature Amplitude Modulation (DP-16QAM). Existing data processing and transmission methods using CFEC or OFEC encoding are not suitable for future high baud rate scenarios, which is an urgent problem that needs to be solved. Summary of the Invention

[0004] The embodiments of the present application provide a data processing method and related devices for use in the field of optical communications, which solve the problem that the encoding processing of the existing technology cannot be used in future high baud rate scenarios (for example, 800Gbit / s, 1.6Tbit / s, or even higher).

[0005] In a first aspect, an embodiment of the present application provides a data processing method, comprising: obtaining first data; obtaining a first bit set based on the first data and added bits; performing forward error correction (FEC) encoding and interleaving on the first bit set to obtain a pre-framing bit set, wherein in the first bit set, each a bit is FEC-encoded to obtain b coded bits, where a and b are both positive integers, and b / a is any one of 96 / 79, 80 / 63, and 112 / 95, and the pre-framing bit set is used to generate a superframe. Data processed by the data processing method of the present application has stronger error correction capabilities and is applicable to transmission systems at 800Gbit / s, 1.6Tbit / s, or even higher rates.

[0006] In combination with the first aspect, in a first possible implementation of the first aspect, each a bit is FEC encoded to obtain b encoded bits, specifically including: among the a bits, each k bit is FEC encoded to obtain n FEC bits, where k is a positive integer, n is a positive integer greater than k, a=c×k, b=c×n, and c is a positive integer.

[0007] In combination with the first possible implementation of the first aspect, in a second possible implementation of the first aspect, c is an integer multiple of 16, so that the solution is easy to implement in hardware and has low complexity.

[0008] In combination with any of the foregoing possible implementations of the first aspect, in a third possible implementation of the first aspect, the first data includes r rows and q columns of bits, where r is a positive integer and q is an integer multiple of 257. Optionally, q is any one of 2056, 4112, 8224, or 10280. Typically, Ethernet data frames are encoded at a granularity of 257 bits, and the solution of the embodiments of the present application can better adapt to Ethernet data frames.

[0009] In combination with any of the above possible implementations of the first aspect, in a fourth possible implementation of the first aspect, the performing forward error correction (FEC) encoding and interleaving on the first bit set to obtain a pre-framing bit set specifically includes: distributing the first bit set to obtain 2Q sub-bit sets, performing FEC encoding on any of the sub-bit sets to obtain 2Q coded bit sets, where Q is a positive integer greater than 0; and interleaving the 2Q coded bit sets to obtain the pre-framing bit set. This embodiment of the present application uses 2Q FEC codes, and then one interleaving process can be performed for every two FEC codes, which facilitates compatibility with existing 400 Gbit / s systems and is applicable to systems with 800 Gbit / s, 1.6 Tbit / s, and even higher transmission rates.

[0010] In combination with the fourth possible implementation of the first aspect, in the fifth possible implementation of the first aspect, the encoded bit set is represented as a matrix including n / a square matrices in each row, and each square matrix includes a rows × a columns of bits, wherein the bit sequence in the i-th row of the W-th row square matrix includes a first check bit, and W is a positive integer; when W is an even number, the first check bit is formed by at least using the i-th column bit in the 0th square matrix in the W-Δ-2n / a+1th row; when W is an odd number, the first check bit is formed by at least using the i-th column bit in the 0th square matrix in the W-Δ-2n / a-1th row, wherein a is a positive integer, n is an integer multiple of a, and Δ is a positive integer.

[0011] In combination with the fourth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row of the square matrix in the W-th row includes the first check bit, and W is a positive integer;

[0012] When W is an even number, the first parity bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-11th row, the i-th column bit in the 1st square matrix in the W-Δ-9th row, the i-th column bit in the 2nd square matrix in the W-Δ-7th row, the i-th column bit in the 3rd square matrix in the W-Δ-5th row, the i-th column bit in the 4th square matrix in the W-Δ-3th row, and the i-th column bit in the 5th square matrix in the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer;

[0013] When W is an odd number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-13th row, the i-th column bit in the 1st square matrix in the W-Δ-11th row, the i-th column bit in the 2nd square matrix in the W-Δ-9th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0014] In addition, it may also be that: when W is an odd number, the first parity bit is formed using at least the i-th column bit in the 0th square matrix of the W-Δ-11th row, the i-th column bit in the 1st square matrix of the W-Δ-9th row, the i-th column bit in the 2nd square matrix of the W-Δ-7th row, the i-th column bit in the 3rd square matrix of the W-Δ-5th row, the i-th column bit in the 4th square matrix of the W-Δ-3th row, and the i-th column bit in the 5th square matrix of the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer;

[0015] When W is an even number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-13th row, the i-th column bit in the 1st square matrix in the W-Δ-11th row, the i-th column bit in the 2nd square matrix in the W-Δ-9th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0016] In combination with the fourth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, the encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row of the W-th row of the square matrix includes the first check bit, and W is a positive integer;

[0017] When W%3 is 0 or 1, the first parity bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-17th row, the i-th column bit in the 1st square matrix in the W-Δ-14th row, the i-th column bit in the 2nd square matrix in the W-Δ-11th row, the i-th column bit in the 3rd square matrix in the W-Δ-8th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-2th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer;

[0018] When W%3 is 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-20th row, the i-th column bit in the 1st square matrix in the W-Δ-17th row, the i-th column bit in the 2nd square matrix in the W-Δ-14th row, the i-th column bit in the 3rd square matrix in the W-Δ-11th row, the i-th column bit in the 4th square matrix in the W-Δ-8th row, and the i-th column bit in the 5th square matrix in the W-Δ-5th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0019] In combination with the fourth possible implementation manner of the first aspect, in an eighth possible implementation manner of the first aspect, the encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row of the square matrix in the W-th row includes the first check bit, and W is a positive integer;

[0020] When W%3 is 0, the first parity bit is formed using at least the i-th column bit in the 0th square matrix of the W-Δ-16th row, the i-th column bit in the 1st square matrix of the W-Δ-13th row, the i-th column bit in the 2nd square matrix of the W-Δ-10th row, the i-th column bit in the 3rd square matrix of the W-Δ-7th row, the i-th column bit in the 4th square matrix of the W-Δ-4th row, and the i-th column bit in the 5th square matrix of the W-Δ-1st row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer;

[0021] When W%3 is 1 or 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix of the W-Δ-19th row, the i-th column bit in the 1st square matrix of the W-Δ-16th row, the i-th column bit in the 2nd square matrix of the W-Δ-13th row, the i-th column bit in the 3rd square matrix of the W-Δ-10th row, the i-th column bit in the 4th square matrix of the W-Δ-7th row, and the i-th column bit in the 5th square matrix of the W-Δ-4th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0022] By adopting the encoding method in the above embodiment, the encoded data can have stronger error correction performance and a better decoding error floor, and can be applied to 800Gbit / s, 1.6Tbit / s, or even higher-speed transmission systems.

[0023] In conjunction with any of the foregoing possible implementations of the first aspect, in a ninth possible implementation of the first aspect, the added bits include padding bits. Optionally, the added bits also include cyclic redundancy check (CRC) bits, where the CRC uses any one of CRC-16, CRC-24, CRC-32, and CRC-48. Using the above CRC checksum can ensure sufficient error detection capability, facilitating accurate reception.

[0024] In combination with any of the above possible implementations of the first aspect, in a tenth possible implementation of the first aspect, q=10280, n=96, k=79, wherein the pre-framing bit set uses dual-polarization quadrature phase shift keying DP-QPSK modulation to generate the superframe, then the interleaving granularity is L×n, the number of symbols before framing M, r and the number of bits included in the first data d in , the number of bits d included in the first bit set scr , the number of bits added d CP The relationship is shown in any of the following table:

[0025]

[0026]

[0027] The solution of the embodiment of the present application adopts a coding scheme of k=79 and n=96, which has a sufficiently high error correction capability and can be applied to 800Gbit / s, 1.6Tbit / s, or even higher-speed transmission systems. In addition, the number of added bits (d CP ) are not many, and the redundancy introduced by inserting CRC check bits and / or padding can be lower.

[0028] In combination with any of the above-mentioned possible implementations of the first aspect, in an eleventh possible implementation of the first aspect, before forward error correction FEC encoding and interleaving of the first bit set, the method also includes: scrambling the first bit set so that 0 and 1 in the scrambled bit data tend to be more equally probable, thereby achieving DC balance and facilitating reception at the receiving end.

[0029] In a second aspect, the present application provides a chip comprising a processor and a communication interface, wherein the processor is connected to the communication interface via a line and is configured to execute any possible implementation method of the first aspect.

[0030] In a third aspect, the present application provides a data processing device, comprising a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute the instructions, so that the data processing device executes any possible implementation method as in the first aspect.

[0031] In a fourth aspect, the present application provides a computer storage medium storing a software program, which, when read and executed by one or more processors, implements any possible implementation method of the first aspect.

[0032] In a fifth aspect, the present application provides a communication system, comprising a data processing device as shown in the third aspect, and a receiving device, wherein the receiving device is used to receive the superframe, decode it, and restore the original data.

[0033] The above beneficial effects have been described in the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is the structural block diagram of the communication system;

[0035] Figure 2 Flowchart of the data processing method provided by this application;

[0036] Figure 3 is the received data sequence represented in matrix form;

[0037] Figure 4 This is a functional diagram of a transmitting signal processor in an embodiment of the present application;

[0038] Figure 5 Flowchart of FEC encoding and interleaving processing provided in an embodiment of the present application;

[0039] FIG6( a ) is a schematic diagram of an FEC encoding method provided by this application;

[0040] FIG6( b ) is a schematic diagram of another FEC encoding method provided by this application;

[0041] FIG6( c ) is a schematic diagram of another FEC encoding method provided by this application;

[0042] FIG7( a ) is a schematic diagram of another FEC encoding method provided by the present application;

[0043] FIG7( b ) is a schematic diagram of another FEC encoding method provided by this application;

[0044] Figure 8 A schematic diagram of another FEC encoding method provided by this application;

[0045] FIG9( a ) is a flow chart of an interleaving process provided in an embodiment of the present application;

[0046] FIG9( b ) is an example diagram of intra-matrix interleaving provided by an embodiment of the present application;

[0047] FIG9( c ) is a schematic diagram of inter-matrix interleaving provided in an embodiment of the present application;

[0048] FIG10( a ) is a flowchart of a process for generating a superframe according to an embodiment of the present application;

[0049] FIG10( b ) is a flowchart of another process for generating a superframe according to an embodiment of the present application;

[0050] Figure 11 A data processing flow chart under a specific condition provided in an embodiment of the present application;

[0051] Figure 12 A data processing flow chart under another specific condition provided in an embodiment of the present application;

[0052] Figure 13 A schematic structural diagram of a data processing device in an embodiment of the present application;

[0053] Figure 14 Schematic diagram of the structure of the decoding device in the embodiment of the present application;

[0054] Figure 15 This is another structural diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0055] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are first explained.

[0056] Figure 1The structural block diagram of the communication system is shown. At the transmitting end, the information source provides the data stream to be sent; the transmitting data processor receives the data stream and performs data processing including coding, interleaving, and modulation to obtain a symbol data stream, which is sent to the transmitting signal processor for transmitting signal preprocessing, and is transmitted through the channel to the receiving device. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving signal processor for dispersion compensation, synchronization, phase recovery and other operations, and then sent to the receiving data processor for demodulation, deinterleaving, decoding, and recovery of the original data, which is sent to the destination. Among them, the method provided by the present application is applied to Figure 1 The transmitting data processor shown is a very important part of the communication system.

[0057] It should be noted that the concepts of bit sets and bit subsets in this specification and claims are merely introduced for ease of description. In practical applications, the data stream is a whole and not divided. Each bit set or bit subset can be considered as one or more bits in the data stream. It should be understood that the bit sets and bit subsets can also be presented in the form of matrices, arrays, etc., which are not specifically limited here.

[0058] This application provides a data processing method, such as Figure 2 As shown, the method includes:

[0059] 201. Obtain first data.

[0060] The first data can be obtained from a received data sequence, and the received data sequence can be represented as a data stream or in the form of a matrix, for example: Figure 3 , which represents the received data sequence in matrix form. The data sequence includes multiple rows of bits, and each row includes q bits, where q is a positive integer. Optionally, q is an integer multiple of 257. Typically, Ethernet data frames are encoded at a 257-bit granularity. An integer multiple of 257 can better adapt to Ethernet data frames; for example, q can be 2056, 4112, 8224, or 10280. Each time, r rows are obtained from the received data sequence, each row containing a total of q×r bits. That is, the first data includes r rows and q columns of bits, i.e., r×q bits, where r is a positive integer.

[0061] 202. Obtain a first bit set according to the first data and the added bits.

[0062] Figure 4 FIG. 1 is a functional diagram of the transmitting signal processor in an embodiment of the present application. Figure 4As shown, the functions of the transmitting end signal processor include inserting cyclic redundancy check (CRC) and / or inserting pad (PadInsertion), scrambling, and FEC coding interleaving. In practical applications, at least one of CRC and padding can be performed. Specifically, first data is obtained from the received data sequence, and the first data includes r rows and q columns of bits, and a total of d in =q×r bits, where r is an integer greater than 0 and the value of q is as shown in the previous embodiment. Afterwards, CRC is performed on the first data and / or padding bits are inserted to obtain a first bit set. In the CRC operation, d CRC CRC check bits are inserted during the padding operation. PAD Filling bits. , that is, the number of bits in the first bit set d scr =q×r+d CRC +d PAD , where d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0, the number of bits added can be recorded as d CP =d CRC +d PAD At this time, the redundancy corresponding to the CRC checksum and inserted padding bits is OH CP =d scr / d in -1=(d CRC +d PAD ) / (q×r). Usually, OH CP The smaller the value, the smaller the inserted CRC or padding redundancy is, and the more effective it is. CP ≤0.5%.

[0063] As an example, when d PAD = 0, after inserting CRC check q × r + d CRC As another example, in order to achieve lower latency and lower complexity, CRC check can be omitted and replaced directly with fill bits, that is, d CRC =0, the added bits are only padding bits; that is, the first data including r rows and q columns of bits are directly inserted into the padding bits, and then coded and interleaved to obtain the pre-framing bit set.

[0064] It should be noted that in some specific application scenarios, CRC check can use CRC-32. In this case, d CRC=32×p, where p represents the number of CRC checks performed on the first data, and p is an integer greater than 1; if r is divisible by p, for r rows of data obtained from the received data sequence, a CRC-32 check is performed on each r / p row of bits (a total of q×r / p bits), and a check bit with a length of 32 bits is added. The CRC-32 check is repeated p times, and a total of d CRC =32×p bits of CRC check bits.

[0065] In the case that r is not divisible by p, consider r F0 ×(p-1)+r F1 = r, where the integer r F0 Greater than integer r F1 In some implementations, the integer integer r F1 =rr F0 ×(p-1), and r F0 >r F1 , More specifically, for the r rows of data obtained from the received data sequence, the first r F0 ×(p-1) rows of each r F0 Row bits (q×r F0 bits) perform CRC-32 check, add a check bit with a length of 32 bits, repeat p-1 times, and get a total of 32×(p-1) bits of CRC check bits. F1 Row bits (q×r F1 bits) to perform CRC-32 check, add a check bit with a length of 32 bits, and get a total of d CRC =32×p bits of CRC check bits. For example, when r=20, p=4, and CRC-32 is used, a CRC-32 check is performed for every 5 rows of data, and the CRC-32 check is repeated 4 times to obtain 4×32=128 bits of check bits; when r=20, p=7, and CRC-32 is used, a CRC-32 check is performed for every 3 rows of data in the first 18 rows, and the CRC-32 check is repeated 6 times to obtain 6×32=192 bits of check bits; a CRC-32 check is performed for the last 2 rows to obtain 32 bits of check bits; a total of 224 bits of check bits are obtained. At this time, r F0 =3, r F1 =2.

[0066] It should be noted that in some specific implementations, q×r F0 =41120, which is the first r rows of data F0 ×(p-1) rows of each rF0 Rows total q×r F0 bits for CRC-32; the CRC-32 encoding and detection operations can directly adopt the CRC-32 operations in the existing 800GZR, which has better compatibility and stronger adaptability.

[0067] The above embodiment is described by using CRC-32. Of course, any one of CRC-16, CRC-24 or CRC-48 can also be used, and this application does not limit it.

[0068] Optionally, before performing forward error correction FEC encoding and interleaving on the first bit set, the first bit set needs to be scrambled so that 0 and 1 in the scrambled bit data tend to have equal probability, achieving DC balance and facilitating reception at the receiving end.

[0069] 203. Perform forward error correction (FEC) encoding and interleaving on the first bit set to obtain a pre-framing bit set. Specifically, in the first bit set, perform FEC encoding on every a bits to obtain b coded bits, where a and b are both positive integers, and b / a is any one of 96 / 79, 80 / 63, and 112 / 95. The pre-framing bit set is used to generate a superframe.

[0070] Furthermore, among the a bits, every k bits are FEC-encoded to obtain n FEC bits, where k is a positive integer, n is a positive integer greater than k, and a = c × k, b = c × n, and c is a positive integer. That is, typically, encoding is performed with a granularity of k information bits to obtain n FEC-encoded bits, recorded as a coded bit sequence. Multiple coded bit sequences are then combined and output. For example, c coded bit sequences are combined and output. Overall, c × k bits are encoded to obtain c × n coded bits, where c is a positive integer greater than 0. Specifically, c can be an integer multiple of 16, such as c = 16, 32, 48, or 64, to facilitate hardware implementation and reduce complexity. Optionally, a Hamming code or a Bose–Chaudhuri–Hocquenghem code (BCH) is employed during the FEC encoding.

[0071] The following describes the specific methods of FEC encoding and interleaving. First, each k bits in the first bit set are FEC-encoded to obtain an n-bit FEC bit. Then, L groups of FEC bits, totaling L×n bits, are interleaved. That is, the granularity of the interleaving is L×n bits, where L is a positive integer (the interleaving granularity can be understood as the total number of bits in the interleaved rows and columns, where L is the number of rows and n is the number of columns). In some specific applications, n=96 and k=79, resulting in an FEC coding redundancy of approximately 21.5%. In other specific applications, n=80 and k=63, resulting in an FEC coding redundancy of 27%. In yet other specific applications, n=112 and k=95, resulting in an FEC coding redundancy of 17.9%. It should be understood that the numerical units of n and k are both bits, and the three cases are: n=96 bits and k=79 bits; n=80 bits and k=63 bits; and n=112 bits and k=95 bits.

[0072] For the above three cases, taking c=32 as an example, encoding from c×k bits to obtain c×n encoded bits can be understood as encoding from 32×79=2528 bits to obtain 32×96=3072 encoded bits, or encoding from 32×63=2016 bits to obtain 32×80=2560 encoded bits, or encoding from 32×95=3040 bits to obtain 32×112=3584 encoded bits; taking c=48 as an example, encoding from 48×79=3792 bits to obtain 48×96=4608 encoded bits. bits, or 48×80=3840 coded bits are obtained by encoding 48×63=3024 bits, or 48×112=5376 coded bits are obtained by encoding 48×95=4560 bits. Taking c=64 as an example, 64×96=6144 coded bits are obtained by encoding 64×79=5056 bits, or 64×80=5120 coded bits are obtained by encoding 64×63=4032 bits, or 64×112=7168 coded bits are obtained by encoding 64×95=6080 bits. These values ​​are selected to better compatibility with existing coding schemes, such as those used in existing 400 Gbit / s systems.

[0073] The FEC coding interleaving process is introduced below.

[0074] FEC encoding and interleaving process Figure 5As shown, it can be understood as the following two steps: (1) the first bit set is distributed first to obtain 2Q sub-bit sets, and any sub-bit set is FEC-encoded to obtain 2Q coded bit sets, where Q is a positive integer greater than 1, and typically, Q is 1, 2, or 4; (2) the 2Q coded bit sets are interleaved and merged to obtain the pre-frame bit set; specifically, every two coded bit sets in the 2Q coded bit sets are interleaved, where the granularity of each interleaving process in the Q interleaving processes is L×n bits, and the Q-path interleaved data output by the Q interleaving processes are merged to obtain 1-path merged data, i.e., the pre-frame bit set. The pre-frame bit set is subsequently subjected to symbol mapping, polarization division, and DSP framing operations to generate a superframe, which can be used in future high-speed transmission systems, for example, 800Gbit / s, 1.6Tbit / s, or even higher rates. It should be noted that when Q is 1, the first bit set only distributes two sub-bit sets, which are interleaved after encoding, and the obtained data is directly used as the bit set before framing. That is, at this time, no merging operation is required in FEC encoding and interleaving.

[0075] The following describes the specific operations for FEC encoding of each sub-bit set. Taking n = 96 and k = 79 as an example, the FEC coding redundancy is approximately 21.5%. As shown in Figures 6(a), 6(b), and 6(c), the bits in the encoded bit set are represented by a matrix comprising multiple square matrices. In this application, each square matrix comprises 16 rows and 16 columns, totaling 256 bits. In other specific applications, each square matrix may comprise 32 rows and 32 columns, totaling 1024 bits. Furthermore, the number of rows and columns in each square matrix can be an integer multiple of 16. This is not strictly limited in this application, and the same applies to the square matrices in subsequent embodiments, so this application will not elaborate further. As shown in Figures 6(a), 6(b), and 6(c), the matrix comprises 6 square matrices, totaling 96 columns of bits. The matrix comprises multiple rows of square matrices, each containing 16 rows of bits, i.e., each square matrix comprises 16 × 96 = 1536 bits. In this matrix, the square matrix with the Wth row and the jth column (0≤j≤5) can be recorded as the square matrix (W,j), where W is an integer.

[0076] As shown in Figure 6(a), the matrix is ​​composed of two rows of matrices. When W is an even number, the six matrices in the W-th row, namely, matrix (W,0), matrix (W,1), matrix (W,2), matrix (W,3), matrix (W,4), and matrix (W,5), are combined with the 0th column matrix (W-Δ-11,0) in the W-Δ-11th row, the 1st column matrix (W-Δ-9,1) in the W-Δ-9th row, the 2nd column matrix (W-Δ-7,2) in the W-Δ-7th row, the 3rd column matrix (W-Δ-5,3) in the W-Δ-5th row, the 4th column matrix (W-Δ-3,4) in the W-Δ-3th row, and the 5th column matrix (W-Δ-1,5) in the W-Δ-1st row, for a total of 12 matrices, forming 16 component codes. The component codes are constructed using the BCH (192, 175) codeword, where the codeword length of each component code is 2n = 2 × 96 = 192 bits, and the information length of each component code is n + k = 175 bits. The component codes can be BCH (192, 175), which is obtained by shortening the extended BCH (256, 239) code by 64 bits, also known as eBCH (192, 175). The multiple square matrices with identical stripes in Figure 6(a) represent the 12 square matrices used to construct the 16 component codes, and the same applies to the following embodiments. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), square matrix (W,4), and square matrix (W,5) has a total of 96 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-11,0), square matrix (W-Δ-9,1), square matrix (W-Δ-7,2), square matrix (W-Δ-5,3), square matrix (W-Δ-3,4), and square matrix (W-Δ-1,5) has a total of 96 bits, and a total of 192 bits constitute one component code word.

[0077] When W is an odd number, the six square matrices in the W-th row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), and square (W,5), combined with the square matrix of the 0th column in the W-Δ-13th row (W-Δ-13,0), the square matrix of the 1st column in the W-Δ-11th row (W-Δ-11,1), the square matrix of the 2nd column in the W-Δ-9th row (W-Δ- 9,2), the third column square matrix in the W-Δ-7th row (W-Δ-7,3), the fourth column square matrix in the W-Δ-5th row (W-Δ-5,4), and the fifth column square matrix in the W-Δ-3rd row (W-Δ-3,5), a total of 12 square matrices, constitute 16 component code words, where the length of each component code word is 2n=2×96=192 bits, and the information length is n+k=175 bits. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), square matrix (W,4), and square matrix (W,5) has a total of 96 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-13,0), square matrix (W-Δ-11,1), square matrix (W-Δ-9,2), square matrix (W-Δ-7,3), square matrix (W-Δ-5,4), and square matrix (W-Δ-3,5) has a total of 96 bits, and a total of 192 bits constitute 1 component code word.

[0078] As shown in Figure 6(a), with each two-row square matrix as a group, it can be understood that each 32 × 79 = 2528 bits are encoded to obtain 32 × 96 = 3072 encoded bits. It should be noted that the 2528 bits can be called information bits or bits to be encoded. Furthermore, each k information bits are encoded to obtain an n-bit FEC bit, while the length of the component codewords in the encoding process is 2n. This is mainly because the FEC encoding process uses convolutional algebraic code coding, also known as spatially coupled coding.

[0079] Specifically, it can be understood that the bit sequence in the i-th row in the square matrix in the W-th row includes a first parity bit. When W is an even number, the first parity bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-11th row, the i-th column bit in the 1st square matrix in the W-Δ-9th row, the i-th column bit in the 2nd square matrix in the W-Δ-7th row, the i-th column bit in the 3rd square matrix in the W-Δ-5th row, the i-th column bit in the 4th square matrix in the W-Δ-3th row, and the i-th column bit in the 5th square matrix in the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0080] When W is an odd number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-13th row, the i-th column bit in the 1st square matrix in the W-Δ-11th row, the i-th column bit in the 2nd square matrix in the W-Δ-9th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0081] Furthermore, the following method can be used: the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit, and when W is an odd number, the first check bit is formed by at least the i-th column bit in the 0th square matrix in the W-Δ-11th row, the i-th column bit in the 1st square matrix in the W-Δ-9th row, the i-th column bit in the 2nd square matrix in the W-Δ-7th row, the i-th column bit in the 3rd square matrix in the W-Δ-5th row, the i-th column bit in the 4th square matrix in the W-Δ-3th row, and the i-th column bit in the 5th square matrix in the W-Δ-1th row, where i is not less than is a positive integer greater than 0 and less than 16, and Δ is a positive integer; when W is an even number, the first parity bit is formed by at least the i-th column bit in the 0th square matrix of the W-Δ-13th row, the i-th column bit in the 1st square matrix of the W-Δ-11th row, the i-th column bit in the 2nd square matrix of the W-Δ-9th row, the i-th column bit in the 3rd square matrix of the W-Δ-7th row, the i-th column bit in the 4th square matrix of the W-Δ-5th row, and the i-th column bit in the 5th square matrix of the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0082] It should be understood that Figure 6(a) uses Δ = 4 as an example. Δ can be any other positive integer, such as 1, 2, 3, 5, 6, 7, 8, 9, 10, etc., and this application does not impose any specific limitations. It should be noted that in the above embodiment, the component code includes previously generated data. Assuming W = 1, W - Δ - 13 is a negative number. In this case, we can set all bits in all negative rows of the matrix to 0, which is equivalent to padding the data before entering FEC encoding with 0s to generate the parity bits in the first few rows of the matrix. For example, when Δ = 4 and W is an odd number, the first parity bit included in the bit sequence of the i-th row of the W-th row of the matrix uses the 0th row of the matrix. That is, when W = 1, the -16th row of the matrix is ​​used. Therefore, at least 16 rows of matrices must be added to the front of the data before encoding, and the content can be all 0s. Similar 0-padding is also required in other FEC encoding embodiments, and this application will not elaborate on this further.

[0083] In addition, the matrix can also be grouped into three rows, as shown in Figure 6(b). In this case, when W%3 is 0 or 1 (% represents the remainder), the six square matrices in the Wth row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), and square (W,5), combined with square (W-Δ-17,0), square (W-Δ-14,1), square (W-Δ-11,2), square (W-Δ-8,3), square (W-Δ-5,4), and square (W-Δ-2,5), a total of 12 square matrices, constitute 16 component codewords, where the codeword length of each component code is 2n = 2 × 96 = 192 bits, and the information length of each component code is n + k = 175 bits. The component code may adopt BCH (192, 175), which is obtained by shortening the extended BCH (256, 239) code by 64 bits, also known as eBCH (192, 175). It should be noted that the i-th (0≤i<16) row in the matrix (W, 0), the matrix (W, 1), the matrix (W, 2), the matrix (W, 3), the matrix (W, 4), and the matrix (W, 5) has a total of 96 bits, combined with the i-th (0≤i<16) column in the matrix (W-Δ-17, 0), the matrix (W-Δ-14, 1), the matrix (W-Δ-11, 2), the matrix (W-Δ-8, 3), the matrix (W-Δ-5, 4), and the matrix (W-Δ-2, 5) has a total of 96 bits, for a total of 192 bits constituting a component codeword.

[0084] When W%3 is 2, the 6 square matrices in the Wth row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), and square (W,5), combined with square (W-Δ-20,0), square (W-Δ-17,1), square (W-Δ-14,2), square (W-Δ-11,3), square (W-Δ-8,4), and square (W-Δ-5,5), a total of 12 square matrices, constitute 16 component code words, where the codeword length of each component code is 2n=2×96=192 bits, and the information length of each component code is n+k=175 bits. It should be noted that the 16 bits in the i-th (0≤i<16) row of the square matrix (W,0), the square matrix (W,1), the square matrix (W,2), the square matrix (W,3), the square matrix (W,4), and the square matrix (W,5) totaling 96 bits, combined with the i-th (0≤i<16) column of the square matrix (W-Δ-20,0), the square matrix (W-Δ-17,1), the square matrix (W-Δ-14,2), the square matrix (W-Δ-11,3), the square matrix (W-Δ-8,4), and the square matrix (W-Δ-5,5) totaling 96 bits, a total of 192 bits constitute one component code word.

[0085] As shown in Figure 6(b), with each 3-row square matrix as a group, it can be understood that each 48×79=3792 bits are encoded to obtain 48×96=4608 encoded bits. It should be noted that the 3792 bits can be called information bits or bits to be encoded.

[0086] Convolutional algebraic code encoding is also used here. Specifically, it can be understood that the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit; when W%3 is 0 or 1, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-17th row, the i-th column bit in the 1st square matrix in the W-Δ-14th row, the i-th column bit in the 2nd square matrix in the W-Δ-11th row, the i-th column bit in the 3rd square matrix in the W-Δ-8th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-2th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer;

[0087] When W%3 is 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-20th row, the i-th column bit in the 1st square matrix in the W-Δ-17th row, the i-th column bit in the 2nd square matrix in the W-Δ-14th row, the i-th column bit in the 3rd square matrix in the W-Δ-11th row, the i-th column bit in the 4th square matrix in the W-Δ-8th row, and the i-th column bit in the 5th square matrix in the W-Δ-5th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0088] It should be noted that FIG6(b) takes Δ=6 as an example, where Δ can be other positive integers, such as 1, 2, 3, 4, 5, 7, 8, 9, 10, etc., and this application does not make any specific limitation.

[0089] Figure 6(c) shows another encoding scheme using three rows of matrices as a group. When W%3 = 0, the six matrices in the Wth row—matrix (W,0), (W,1), (W,2), (W,3), (W,4), and (W,5)—combine matrices (W-Δ-16,0), (W-Δ-13,1), (W-Δ-10,2), (W-Δ-7,3), (W-Δ-4,4), and (W-Δ-1,5), for a total of 12 matrices, form 16 component codewords. The codeword length of each component code is 2n = 2 × 96 = 192 bits, and the information length of each component code is n + k = 175 bits. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), square matrix (W,4), and square matrix (W,5) has a total of 96 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-16,0), square matrix (W-Δ-13,1), square matrix (W-Δ-10,2), square matrix (W-Δ-7,3), square matrix (W-Δ-4,4), and square matrix (W-Δ-1,5) has a total of 96 bits, and a total of 192 bits constitute one component code word.

[0090] As shown in Figure 6(c), when W%3=1 or 2, the 6 square matrices in the Wth row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), and square (W,5), combined with square (W-Δ-19,0), square (W-Δ-16,1), square (W-Δ-13,2), square (W-Δ-10,3), square (W-Δ-7,4), and square (W-Δ-4,5), a total of 12 square matrices, constitute 16 component code words, where the codeword length of each component code is 2n=2×96=192 bits, and the information length of each component code is n+k=175 bits. It should be noted that the i-th (0≤i<16) row in the matrix (W,0), matrix (W,1), matrix (W,2), matrix (W,3), matrix (W,4), and matrix (W,5) has a total of 96 bits, combined with the i-th (0≤i<16) column in the matrix (W-Δ-19,0), matrix (W-Δ-16,1), matrix (W-Δ-13,2), matrix (W-Δ-10,3), matrix (W-Δ-7,4), and matrix (W-Δ-4,5) has a total of 96 bits, and a total of 192 bits constitute a component codeword. It should be noted that Figure 6(c) takes Δ=6 as an example, where Δ can be other positive integers, such as 1, 2, 3, 4, 5, 7, 8, 9, 10, etc., and this application does not make specific limitations.

[0091] Similarly, since convolutional algebraic code encoding is used, the bit sequence in the i-th row of the square matrix in the W-th row includes a first parity bit. When W%3 is 0, the first parity bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-16th row, the i-th column bit in the 1st square matrix in the W-Δ-13th row, the i-th column bit in the 2nd square matrix in the W-Δ-10th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-4th row, and the i-th column bit in the 5th square matrix in the W-Δ-1st row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0092] When W%3 is 1 or 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix of the W-Δ-19th row, the i-th column bit in the 1st square matrix of the W-Δ-16th row, the i-th column bit in the 2nd square matrix of the W-Δ-13th row, the i-th column bit in the 3rd square matrix of the W-Δ-10th row, the i-th column bit in the 4th square matrix of the W-Δ-7th row, and the i-th column bit in the 5th square matrix of the W-Δ-4th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0093] Similarly, taking n=80 and k=63 as an example, the FEC coding redundancy is approximately 27%. As shown in Figure 7(a) and Figure 7(b), the bits in the encoded bit set are represented by a matrix containing multiple square matrices. In this application, each square matrix contains 16 rows and 16 columns, totaling 256 bits. As shown in Figure 7(a) and Figure 7(b), the matrix contains 5 columns of square matrices, totaling 80 columns of bits. The matrix contains multiple rows of square matrices, each row of which contains 16 rows of bits, that is, each row of the square matrix includes 16×80=1280 bits. For the infinite length matrix, the square matrix of the Wth row and the jth column (0≤j≤4) can be recorded as the square matrix (W,j), where W is an integer.

[0094] FIG7(a) shows the case where the matrix is ​​grouped into two rows of matrices, which is similar to the case of FIG6(a). When W is an even number, the five matrices in the W-th row, namely, the matrix (W,0), the matrix (W,1), the matrix (W,2), the matrix (W,3), and the matrix (W,4), are combined with the 0th column matrix (W-Δ-9,0) in the W-Δ-9th row, the 1st column matrix (W-Δ-7,1) in the W-Δ-7th row, the 2nd column matrix (W-Δ-5,2) in the W-Δ-5th row, the 3rd column matrix (W-Δ-3,3) in the W-Δ-3th row, and the 4th column matrix (W-Δ-1,4) in the W-Δ-1st row, for a total of 10 matrices, forming 16 component codes. The component codes are each composed of a codeword of 2n=2×80=160 bits, and an information length of n+k=143 bits. The component codes may be BCH(160,143), which is obtained by shortening an extended BCH(256,239) code by 96 bits, also known as eBCH(160,143). It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), and square matrix (W,4) has a total of 80 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-9,0), square matrix (W-Δ-7,1), square matrix (W-Δ-5,2), square matrix (W-Δ-3,3), and square matrix (W-Δ-1,4) has a total of 80 bits, and a total of 160 bits constitute one component code word.

[0095] As shown in FIG7(a), with each 2-row square matrix as a group, it can be understood that each 32×63=2016 bits are encoded to obtain 32×80=2560 encoded bits. It should be noted that the 2016 bits can be called information bits or bits to be encoded.

[0096] Convolutional algebraic code coding is also used here. Specifically, it can be understood that the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit. When W is an even number, the first check bit is formed by at least using the i-th column bit in the 0th square matrix in the W-Δ-9th row, the i-th column bit in the 1st square matrix in the W-Δ-7th row, the i-th column bit in the 2nd square matrix in the W-Δ-5th row, the i-th column bit in the 3rd square matrix in the W-Δ-3th row, and the i-th column bit in the 4th square matrix in the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0097] When W is an odd number, the five square matrices in the W-th row, namely, square (W,0), square (W,1), square (W,2), square (W,3), and square (W,4), combined with the 0th column square (W-Δ-11,0) in the W-Δ-11th row, the 1st column square (W-Δ-9,1) in the W-Δ-9th row, the 2nd column square (W-Δ-7,2) in the W-Δ-7th row, the 3rd column square (W-Δ-5,3) in the W-Δ-5th row, and the 4th column square (W-Δ-3,4) in the W-Δ-3th row, a total of 10 square matrices, constitute 16 component codewords. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), and square matrix (W,4) has a total of 96 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-11,0), square matrix (W-Δ-9,1), square matrix (W-Δ-7,2), square matrix (W-Δ-5,3), and square matrix (W-Δ-3,4) has a total of 96 bits, and a total of 180 bits constitute 1 component code word.

[0098] That is, when W is an odd number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-11th row, the i-th column bit in the 1st square matrix in the W-Δ-9th row, the i-th column bit in the 2nd square matrix in the W-Δ-7th row, the i-th column bit in the 3rd square matrix in the W-Δ-5th row, and the i-th column bit in the 4th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0099] FIG7( b ) shows the situation where the matrix is ​​grouped into four square matrices. Similarly, when W%4 is 0, 1, or 2, the five square matrices in the Wth row, namely, square (W,0), square (W,1), square (W,2), square (W,3), and square (W,4), combined with the 0th column square (W-Δ-19,0) in the W-Δ-19th row, the 1st column square (W-Δ-15,1) in the W-Δ-15th row, the 2nd column square (W-Δ-11,2) in the W-Δ-11th row, the 3rd column square (W-Δ-7,3) in the W-Δ-7th row, and the 4th column square (W-Δ-3,4) in the W-Δ-3rd row, a total of 10 square matrices, constitute 16 component code codewords, where the codeword length of each component code is 2n=2×80=160 bits, and the information length of each component code is n+k=143 bits. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), and square matrix (W,4) has a total of 80 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-19,0), square matrix (W-Δ-15,1), square matrix (W-Δ-11,2), square matrix (W-Δ-7,3), and square matrix (W-Δ-3,4) has a total of 80 bits, and a total of 160 bits constitute 1 component code word.

[0100] As shown in FIG7(b), with each 4-row square matrix as a group, it can be understood that each 64×63=4032 bits are encoded to obtain 64×80=5120 encoded bits. It should be noted that the 4032 bits can be called information bits or bits to be encoded.

[0101] Convolutional algebraic code encoding is also used here. Specifically, it can be understood that the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit. When W%4 is 0, 1, or 2, the first check bit is formed by at least using the i-th column bit in the 0th square matrix in the W-Δ-19th row, the i-th column bit in the 1st square matrix in the W-Δ-15th row, the i-th column bit in the 2nd square matrix in the W-Δ-11th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, and the i-th column bit in the 4th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0102] When W%4 is 3, the five square matrices in the Wth row, namely, square (W,0), square (W,1), square (W,2), square (W,3), and square (W,4), combined with the 0th column square (W-Δ-23,0) in the W-Δ-23th row, the 1st column square (W-Δ-19,1) in the W-Δ-19th row, the 2nd column square (W-Δ-15,2) in the W-Δ-15th row, the 3rd column square (W-Δ-11,3) in the W-Δ-11th row, and the 4th column square (W-Δ-7,4) in the W-Δ-7th row, a total of 10 square matrices, constitute 16 component codewords. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), and square matrix (W,4) has a total of 80 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-23,0), square matrix (W-Δ-19,1), square matrix (W-Δ-15,2), square matrix (W-Δ-11,3), and square matrix (W-Δ-7,4) has a total of 80 bits, and a total of 160 bits constitute 1 component code word.

[0103] That is, the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit. When W%4 is 3, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-23th row, the i-th column bit in the 1st square matrix in the W-Δ-19th row, the i-th column bit in the 2nd square matrix in the W-Δ-15th row, the i-th column bit in the 3rd square matrix in the W-Δ-11th row, and the i-th column bit in the 4th square matrix in the W-Δ-7th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0104] It should be understood that Figure 7(a) and 7(b) Here, Δ=4 is taken as an example. Here, Δ can be other positive integers, such as 1, 2, 3, 5, 6, 7, 8, 9, 10, etc., and this application does not make any specific limitation.

[0105] Similarly, taking n=112 and k=95 as an example, the FEC coding redundancy is about 17.9%. Figure 8 As shown, the bits in the encoded bit set are represented by a matrix containing multiple square matrices. In this application, it is taken as an example that each square matrix contains 16 rows and 16 columns, a total of 256 bits. Figure 8 As shown, the matrix contains 7 square matrices, totaling 112 columns of bits. The matrix also contains multiple rows of square matrices, each of which contains 16 rows of bits, i.e., each row of square matrices contains 16 × 112 = 1792 bits. For the infinite length matrix, the square matrix in the Wth row and jth column (0≤j≤6) can be denoted as square matrix (W, j), where W is an integer.

[0106] Figure 8What is shown is the situation where the matrix is ​​grouped into two rows, which is similar to the situation in Figures 6(a) and 7(a). When W is an even number, the seven square matrices in the W-th row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), square (W,5), and square (W,6), are combined with the square matrices (W-Δ-13,0) in the 0th column of the W-Δ-13th row and the square matrices (W-Δ-13,0) in the 1st column of the W-Δ-11th row. The 14 square matrices (W-Δ-11, 1), the second column of the W-Δ-9th row (W-Δ-9, 2), the third column of the W-Δ-7th row (W-Δ-7, 3), the fourth column of the W-Δ-5th row (W-Δ-5, 4), the fifth column of the W-Δ-3th row (W-Δ-3, 5), and the sixth column of the W-Δ-1st row (W-Δ-1, 6) constitute 16 component code codewords. The codeword length of each component code is 2n = 2 × 112 = 224 bits, and the information length of each component code is n + k = 207 bits. The component code can be BCH (224, 207), which is obtained by shortening the extended BCH (256, 239) code by 32 bits, also known as eBCH (224, 207). It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), square matrix (W,4), square matrix (W,5), and square matrix (W,6) has a total of 112 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-13,0), square matrix (W-Δ-11,1), square matrix (W-Δ-9,2), square matrix (W-Δ-7,3), square matrix (W-Δ-5,4), square matrix (W-Δ-3,5), and square matrix (W-Δ-1,6) has a total of 112 bits, and a total of 224 bits constitute one component code word.

[0107] That is, the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit. When W is an even number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-13th row, the i-th column bit in the 1st square matrix in the W-Δ-11th row, the i-th column bit in the 2nd square matrix in the W-Δ-9th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, the i-th column bit in the 5th square matrix in the W-Δ-3th row, and the i-th column bit in the 6th square matrix in the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0108] When W is an odd number, the seven square matrices in the W-th row, namely, square (W,0), square (W,1), square (W,2), square (W,3), square (W,4), square (W,5), and square (W,6), combined with the square matrix (W-Δ-15,0) in the 0th column of the W-Δ-15th row, the square matrix (W-Δ-13,1) in the 1st column of the W-Δ-13th row, and the square matrix (W-Δ-11) in the W-Δ-11th row, are combined. A total of 14 square matrices, including the 2nd square matrix in the W-Δ-11,2, the 3rd square matrix in the W-Δ-9th row (W-Δ-9,3), the 4th square matrix in the W-Δ-7th row (W-Δ-7,4), the 5th square matrix in the W-Δ-5th row (W-Δ-5,5), and the 6th square matrix in the W-Δ-3rd row (W-Δ-3,6), constitute 16 component code codewords, where the codeword length of each component code is 2n=2×112=224 bits, and the information length of each component code is n+k=207 bits. It should be noted that the i-th (0≤i<16) row in the square matrix (W,0), square matrix (W,1), square matrix (W,2), square matrix (W,3), square matrix (W,4), square matrix (W,5), and square matrix (W,6) has a total of 112 bits, combined with the i-th (0≤i<16) column in the square matrix (W-Δ-15,0), square matrix (W-Δ-13,1), square matrix (W-Δ-11,2), square matrix (W-Δ-9,3), square matrix (W-Δ-7,4), square matrix (W-Δ-5,5), and square matrix (W-Δ-3,6) has a total of 112 bits, and a total of 224 bits constitute one component code word.

[0109] That is, the bit sequence in the i-th row of the square matrix in the W-th row includes a first check bit. When W is an odd number, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-15th row, the i-th column bit in the 1st square matrix in the W-Δ-13th row, the i-th column bit in the 2nd square matrix in the W-Δ-11th row, the i-th column bit in the 3rd square matrix in the W-Δ-9th row, the i-th column bit in the 4th square matrix in the W-Δ-7th row, the i-th column bit in the 5th square matrix in the W-Δ-5th row, and the i-th column bit in the 6th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

[0110] It should be understood that Figure 8 Taking Δ=4 as an example, Δ here can be other positive integers, such as 1, 2, 3, 5, 6, 7, 8, 9, 10, etc., and this application does not make specific limitations.

[0111] The following introduces Figure 5The basic flow of each interleaving operation in the Q interleaving processes described in

[15] is shown in Figure 9(a). Each interleaving process includes two operations: intra-block interleaving and inter-block interleaving. Each of the 2Q coded bit sets undergoes intra-block interleaving, as shown in Figure 9(b). The 16-row, 16-column input matrix is ​​interleaved according to the interleaving rules shown in Figure 9(b), and the order is shuffled to produce a 16-row, 16-column output matrix. In Figure 9(b), the element in row i1, column j1 (0≤i1<16 and 0≤j1<16) is (a, b), indicating that the bit in row i1, column j1 of the output matrix after intra-block interleaving comes from the bit in row a, column b of the input matrix. For example, the element in row 1 and column 0 in Figure 9(b) is (14, 15). Then, after “intra-matrix interleaving”, the bits in row 1 and column 0 of the output matrix come from the bits in row 14 and column 15 of the input matrix.

[0112] After the intra-matrix interleaving process, the bits are interleaved between matrices to improve the overall anti-burst performance. The inter-matrix interleaving operation is described below.

[0113] Figure 9(c) is a schematic diagram of inter-matrix interleaving in an embodiment of the present application. Every two bit sets interleaved within a matrix are stored in the interleaving buffer in the form of an L-row n-column matrix. In this application, taking each matrix containing 16 rows and 16 columns, a total of 256 bits, as an example, the matrix includes L B =L / 16 rows, n B =n / 16 columns in a square matrix, where even-numbered rows come from one of the two interleaved bit sets, and odd-numbered rows come from the other of the two interleaved bit sets. It should be noted that the interleaving buffer contains n bit columns, matching the length n of the FEC coded bits. This facilitates hardware implementation, reduces data format conversion during implementation, and reduces complexity.

[0114] The matrix is ​​divided into four parts, the first part includes the 0th, 2nd, 4th, ..., Lth of the matrix B / 2-2 rows of the square matrix, the second part includes the 1st, 3rd, 5th, ..., L B / 2-1 rows of the square matrix, the third part includes the Lth B / 2,L B / 2+2,L B / 2+4,…,L B -2 rows of the square matrix, the fourth part includes the Lth B / 2+1,L B / 2+3,L B / 2+5,…,L B -1 row of the square matrix; interleaving the four parts between the square matrices to obtain an interleaved bit set.

[0115] The specific interleaving method is as follows: B The bit is the granularity, and polling reads the bits in each column from each set. It reads all the bits in each column before reading the bits in the next column. First, read the first set of d from the first part from top to bottom. B bits, and then read the first d from the second, third, and fourth parts from top to bottom respectively. B bits, a total of 4×d is read in one cycle B Then, the next cycle reads the next set of d from the first part, the second part, the third part, and the fourth part from top to bottom respectively. B bits, a total of 4×d B bits. After a total of L / (4×d B ) cycles to read out the L bits of the current column. Then, read out the bits of the next column according to the above operation, read n columns in total, and read out all L×n bits in the interleaving buffer. B It can be 4 bits, 8 bits or other values, which is not limited in this application.

[0116] Furthermore, the 2Q intra-matrix interleaved bit sets are interleaved between matrices, resulting in a total of Q interleaved bit sets. These are then merged into one path to obtain a pre-framing bit set. The merging may be performed by round-robin reading bits from 0 to Q-1 interleaved bit sets, with t bits read each time, where t is the number of bits required to map to a dual-polarization symbol. It should be understood that other merging schemes may exist, and this application does not limit them herein.

[0117] The pre-framing bit set obtained through the above operations is used to generate a superframe, and Figures 10 (a) and 10 (b) respectively give two flowcharts of generating superframes using the pre-framing bit set in an embodiment of the present application. First, as shown in Figure 10 (a), the pre-framing bit set is subjected to symbol mapping (symbol map) and polarization division (Polarization distribution) to obtain a dual-polarization symbol, and the symbol mapping is also referred to as modulation. Symbol mapping and polarization division map t bits to 1 dual-polarization symbol, where t is an integer greater than 0. The symbol mapping, including but not limited to Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM), is then subjected to polarization symbol division to obtain a dual-polarization (DP) symbol, for example, DP-QPSK, DP-8QAM, DP-16QAM, DP-32QAM, and DP-64QAM. For example, when t=4, the dual polarization symbol is a dual polarization quadrature phase shift keying (DP-QPSK) symbol. When t=6, the dual polarization symbol is an octal dual polarization quadrature amplitude modulation (DP-8QAM) symbol. When t=8, the dual polarization symbol is a hexadecimal dual polarization quadrature amplitude modulation (DP-16QAM) symbol. When t=12, the dual polarization symbol is a 64-decimal dual polarization quadrature amplitude modulation (DP-64QAM) symbol. Furthermore, digital signal processing (DSP) framing is performed on the dual-polarization symbols (including but not limited to inserting pilot symbols, training symbols, frame synchronization symbols, and reserved symbols). DSP framing processes every M dual-polarization symbols to produce a superframe. The M dual-polarization symbols are also called pre-framing symbols or payload symbols.

[0118] The framing operation shown in Figure 10(a) operates on symbols. Alternatively, as shown in Figure 10(b), DSP framing processing can be performed on the pre-framing bit set based on the adopted symbol mapping rules before symbol mapping. For example, bits corresponding to pilot symbols, training symbols, frame synchronization symbols, and reserved symbols can be inserted. Polarization division and symbol mapping can then be performed to obtain a superframe identical to that shown in Figure 10(a). It should be understood that other framing methods are not excluded and will not be further described in this application.

[0119] 9 (c), it can be seen that the number of bit rows L of the interleaved buffer must be an integer multiple of 16, and the number of square rows L of the interleaved buffer B =L / 16 needs to be an integer multiple of 4. Considering that the scheme is compatible with DP-QPSK, 8-ary dual polarization orthogonal amplitude modulation (Dual Polarization 8-Quadrature Amplitude Modulation, DP-8QAM), DP-16QAM, and even the possible future DP-64QAM, L needs to be an integer multiple of 3. Therefore, in order to facilitate hardware implementation, n is selected as an integer multiple of 16, and L is selected as an integer multiple of 16×4×3=192. At this time, the number of interleaving processing granularity bits L×n in the FEC coding interleaving process can be divided by 4, 8, and 12. That is, the L×n bits obtained after the interleaving process can obtain L×n / t complete modulation symbols through symbol mapping.

[0120] It should be noted that, in order to facilitate hardware implementation, the number of symbols before framing is selected as M=L×n. in =q×r bits of first data are inserted with CRC and / or padding, and then subjected to the FEC encoding and interleaving to obtain a total bit length of d scr / k×n pre-framing bit set. scr The bit set before framing of k×n bits undergoes symbol mapping and polarization division to obtain d scr / k×n / t pre-framing symbols. Select d scr / k×n / t=M, so that the first data containing r rows can be encoded and interleaved and processed in a data process including symbol mapping, polarization division, and framing to obtain a superframe, which is convenient for hardware implementation. scr =L×k×t.

[0121] Below, we consider {q = 10280, n = 96, k = 79, t = 4}, {q = 10280, n = 96, k = 79, t = 8}, {q = 10280, n = 80, k = 63, t = 4}, {q = 10280, n = 80, k = 63, t = 8}, {q = 2056, n = 96, k = 79, t = 4}, {q = 2056, n = 96, k = 79, t = 8}, {q = 2056, n = 80, k = 63, t = 4}, {q = 2056, n = 80, k = 63, t = 8}, and give a variety of {L, M, r} parameter combinations, and give the corresponding d under these parameter combinations in d scr d CP OH CP .

[0122] (1) Consider q=10280, n=96, k=79, t=4.

[0123] At this time, the FEC coding redundancy is about 21.5%, and DP-QPSK modulation is used. Table 1(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0124] Table 1(a)

[0125]

[0126]

[0127] It should be noted that in some specific applications, after obtaining the first data of r rows and q columns of bits from the received data sequence, a CRC check is first performed before inserting padding bits. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, CRC-32 can be used for CRC check, and the length of the corresponding information bits for CRC check is not greater than 41120 bits. More specifically, when r is divisible by 4, the integer p = r / 4, and a CRC-32 check is performed on every 4 rows of the first data, a total of 41120 bits, and a check bit with a length of 32 bits is added. The CRC-32 check is repeated p times, and a total of d bits are added. CRC =32×p bits of CRC check bits. When r cannot be divided by 4, Consider 0 <d CRC =32×p≤d CP , Table 1(b) below gives various combinations of {L, M, r} parameters and the corresponding d under these parameter combinations. in dscr OH CP ,p,d CRC d PAD .

[0128] Table 1(b)

[0129]

[0130]

[0131] In some scenarios, we can consider the case where L=1344. In this case, M=129024, r=41, d in =421480,d scr =424704,d CRC =352,d PAD =2872,d CP =3224, p=11, OH CP =0.76%.

[0132] (2) Consider q=10280, n=96, k=79, t=8.

[0133] At this time, the FEC coding redundancy is about 21.5%, and DP-16QAM modulation is used. Table 2(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0134] Table 2(a)

[0135]

[0136]

[0137] It should be noted that, in some specific applications, the first data can be CRC-checked before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, the CRC check can use CRC-32. Other aspects are similar to case (1). Table 2(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under this parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0138] Table 2(b)

[0139]

[0140]

[0141] In some scenarios, we can consider the case where L=1344. In this case, M=129024, r=82, d in =842960,d scr =849408,d CRC =672,d PAD =5776,d CP =6448, p=21, OH CP =0.76%.

[0142] (3) Consider q=10280, n=80, k=63, t=4.

[0143] At this time, the FEC coding redundancy is about 27%, and DP-QPSK modulation is used. Table 3(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0144] Table 3(a)

[0145]

[0146]

[0147] It should be noted that, in some specific applications, the first data may be subjected to CRC check before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, CRC check may adopt CRC-32. Other aspects are similar to case (1). Table 3(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under the parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0148] Table 3(b)

[0149]

[0150]

[0151] (4) Consider q=10280, n=80, k=63, t=8.

[0152] At this time, the FEC coding redundancy is about 27%, and DP-16QAM modulation is used. Table 4(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0153] Table 4(a)

[0154]

[0155]

[0156] It should be noted that, in some specific applications, the first data can be CRC-checked before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, the CRC check can use CRC-32. Other aspects are similar to case (1). Table 4(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under this parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0157] Table 4(b)

[0158]

[0159]

[0160] (5) Consider q=2056, n=96, k=79, t=4.

[0161] At this time, the FEC coding redundancy is about 21.5%, and DP-QPSK modulation is used. Table 5(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0162] Table 5(a)

[0163]

[0164]

[0165] It should be noted that in some specific applications, after obtaining the first data of r rows and q columns of bits from the received data sequence, a CRC check is first performed and then padding is inserted. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, CRC-32 can be used for CRC check, and the corresponding information bit length for CRC check is not greater than 41120 bits. More specifically, when r is divisible by 20, the integer p = r / 20, and a CRC-32 check is performed on every 20 rows of the first data, a total of 41120 bits, and a check bit with a length of 32 bits is added. The CRC-32 check is repeated p times, and a total of d bits are added. CRC =32×p bits of CRC check bits. When r cannot be divided by 20, r F0 =20, Consider 0 <d CRC =32×p≤d CP Table 5(b) below gives various combinations of {L, M, r} parameters and the corresponding d under these parameter combinations. in d scr OH CP ,p,d CRC d PAD .

[0166] Table 5(b)

[0167]

[0168]

[0169] (6) Consider q=2056, n=96, k=79, t=8.

[0170] At this time, the FEC coding redundancy is about 21.5%, and DP-16QAM modulation is used. Table 6(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0171] Table 6(a)

[0172]

[0173]

[0174] It should be noted that, in some specific applications, the first data can be CRC-checked before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, the CRC check can use CRC-32. Other aspects are similar to case (1). Table 6(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under this parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0175] Table 6(b)

[0176]

[0177]

[0178] (7) Consider q=2056, n=80, k=63, t=4.

[0179] At this time, the FEC coding redundancy is about 27%, and DP-QPSK modulation is used. Table 7(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0180] Table 7(a)

[0181]

[0182]

[0183] It should be noted that, in some specific applications, the first data may be subjected to CRC check before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, CRC check may adopt CRC-32. Other aspects are similar to those in case (1). Table 7(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under the parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0184] Table 7(b)

[0185]

[0186]

[0187] (8) Consider q=2056, n=80, k=63, t=8.

[0188] At this time, the FEC coding redundancy is about 27%, and DP-16QAM modulation is used. Table 8(a) below gives various {L, M, r} parameter combinations and the corresponding d under these parameter combinations. in d scr d CP OH CP .

[0189] Table 8(a)

[0190]

[0191]

[0192] It should be noted that, in some specific applications, the first data may be subjected to CRC check before inserting padding. In order to facilitate the reuse of the CRC operation adopted by the existing 800ZR standard, CRC check may adopt CRC-32. Other aspects are similar to those in case (1). Table 8(b) below gives various {L, M, r} parameter combinations in this embodiment, and gives the corresponding d under the parameter combination. in d scr OH CP ,p,d CRC d PAD .

[0193] Table 8(b)

[0194]

[0195]

[0196] The solution of this application is described below with two specific embodiments.

[0197] Example 1:

[0198] This embodiment provides a data processing method for optical communication. In this case, the FEC coding redundancy is about 21.5%, and DP-16QAM modulation is used. The process is as follows: Figure 11 As shown, for the received data sequence, r=766 rows, each row has q=2056 columns of bits (i.e., a total of d in = r × q = 766 × 2056 = 1574896 bits), performs a first data processing to obtain a pre-framing bit set, and then performs a second data processing on the pre-framing bit set to obtain a superframe containing multiple dual-polarization symbols. Which processing steps are included in the first data processing and the second data processing? Figure 11 shown.

[0199] In the first data processing, the first data is first subjected to CRC-32 check, and the CRC-32 check is repeated p=39 times, adding d CRC =39×32=1248 bits of CRC check bits, and then insert d PAD = 1328 padding bits, i.e. a total of d CP =d CRC +d PAD = 2576 bits, then after CRC and inserting padding bits, there are a total of d in +d CP =The first bit set of 1577472 bits. Then, the first bit set is scrambled to facilitate reception at the receiving end. After scrambling, the first bit set is FEC encoded and interleaved to obtain a pre-framing bit set, wherein the first bit set is first distributed to obtain 8 sub-bit sets, and any sub-bit set is FEC encoded (k=79, n=96) to obtain 8 coded bit sets, and then the 8 sub-bit sets are interleaved every 2 sub-bit sets. The interleaving processing granularity of each of the 4 interleaving processes is L×n=2496×96=239616 bits. The processing granularity refers to the total number of interleaving buffer bits in the group interleaving used in each interleaving process, that is, the product of the number of rows and the number of columns. As shown in Figure 9(a), each interleaving process includes intra-matrix interleaving and inter-matrix interleaving. The specific interleaving method is as described in the previous embodiment and will not be repeated in this application. The four paths of interleaved data output by the four interleaving processes are then merged to obtain one path of data, namely, a pre-framing bit set, whose size is 1577472×96 / 79=1916928 bits. That is, the obtained first data of r=766 rows and q=2056 columns of bits per row will become a pre-framing bit set of 1916928 bits after the first data processing, and the pre-framing bit set will be subjected to the second data processing.

[0200] In the second data processing, Figure 11 The illustrated method is used as an example to perform symbol mapping and polarization division on the pre-framing bit set to obtain dual-polarization symbols. In this embodiment, symbol mapping and polarization division map eight bits into one dual-polarization DP-16QAM symbol. Furthermore, digital signal processing is performed on the dual-polarization symbols to form frames. DSP framing is performed on every M = 239,616 dual-polarization symbols (pre-framing symbols) to obtain a superframe.

[0201] The above data processing method has the advantage of simple hardware implementation. Among them, n=96 is an integer multiple of 16, and L=2496 is an integer multiple of 192, which is convenient for hardware implementation; the interleaving buffer for matrix interleaving in this embodiment can also contain 96 bit columns, matching the coding bit length (n=96 bits) in the FEC coding, which is also convenient for hardware implementation, reducing the data format conversion during specific implementation and reducing complexity. Moreover, the number of bit rows of the interleaving buffer L=2496 is an integer multiple of 16, and the number of matrix rows of the interleaving buffer L B =156 is an integer multiple of 4, and L is also an integer multiple of 3, which facilitates compatibility with DP-QPSK, DP-8QAM, DP-16QAM, and even DP-64QAM in the future. The solution with higher FEC coding redundancy OH proposed in this embodiment can have stronger FEC decoding performance to meet the needs of future applications using high baud transmission. In addition, OH in this embodiment CP It can be as low as 0.164%.

[0202] Example 2:

[0203] This embodiment provides a data processing method for optical communication, in which the FEC coding redundancy is about 21.5% and DP-16QAM modulation is used. Figure 12 As shown, for the interpreted data sequence, r=82 rows, each row has q=10280 columns of bits (i.e., a total of d in = r × q = 82 × 10280 = 842960 bits), performs a first data processing to obtain a pre-framing bit set, and then performs a second data processing on the pre-framing bit set to obtain a superframe containing multiple dual-polarization symbols. Which processing steps are included in the first data processing and the second data processing? Figure 12 shown.

[0204] In the first data processing, CRC-32 is first performed on the first data, and the CRC-32 check is repeated p=21 times, adding d CRC = 21 × 32 = 672 bits of CRC check bits, and then insert d PAD = 5776 padding bits, i.e. a total of d CP =d CRC +d PAD = 6448 bits, then after CRC and inserting padding bits, there are a total of d in +d CP=The first bit set of 849408 bits. Then, the first bit set is scrambled to facilitate reception at the receiving end. After scrambling, the first bit set is FEC encoded and interleaved to obtain a pre-framing bit set, wherein the first bit set is first distributed to obtain 8 sub-bit sets, and any sub-bit set is FEC encoded (k=79, n=96) to obtain 8 coded bit sets, and then the 8 sub-bit sets are interleaved every 2 sub-bit sets. The interleaving granularity of each of the 4 interleaving processes is L×n=1344×96=129024 bits, as shown in Figure 9(a). Each interleaving process includes intra-matrix interleaving and inter-matrix interleaving. The specific interleaving method is as described in the previous embodiment and will not be repeated in this application. The four paths of interleaved data output by the four interleaving processes are then merged to obtain one path of data, namely, a pre-framing bit set, whose size is 849408×96 / 79=1032192 bits. That is, the obtained first data of r=82 rows and q=10280 columns of bits per row will become a pre-framing bit set of 1032192 bits after the first data processing, and the pre-framing bit set will be subjected to the second data processing.

[0205] In the second data processing, Figure 12 Taking the illustrated approach as an example, symbol mapping and polarization division are performed on the pre-framing bit set to obtain dual-polarization symbols. In this embodiment, symbol mapping and polarization division map eight bits into one dual-polarization DP-16QAM symbol. Furthermore, digital signal processing is performed on the dual-polarization symbols to form frames. DSP framing is performed on every M = 129,024 dual-polarization symbols (pre-framing symbols) to obtain a superframe.

[0206] The above data processing method also has the advantage of simple hardware implementation, wherein n=96 is an integer multiple of 16, and L=1344 is also an integer multiple of 192, which is convenient for hardware implementation; the interleaving buffer for interleaving between square matrices in this embodiment can also contain 96 bit columns, matching the coded bit length (n=96 bits) output after the FEC sub-coding processing, which is convenient for hardware implementation, reduces the data format conversion during the specific implementation, and can reduce the complexity. Moreover, the number of bit rows of the interleaving buffer L=1344 is an integer multiple of 16, and the number of square matrix rows of the interleaving buffer L B =84 is an integer multiple of 4, and L is also an integer multiple of 3, which facilitates compatibility with DP-QPSK, DP-8QAM, DP-16QAM, and even DP-64QAM in the future. The solution with higher OH proposed in this embodiment can have stronger FEC decoding performance to meet the needs of future applications using high baud transmission. In addition, the OH in this embodiment CP Can be as low as 0.765%.

[0207] The present application provides a receiving method for decoding the superframe provided in the previous embodiments of the present application to recover the original data. The decoding process includes but is not limited to performing dispersion compensation, synchronization, phase recovery, demodulation, deinterleaving, decoding and other processing on the superframe data.

[0208] Figure 13 Schematic diagram of the structure of the data processing device used in the transmitting end in the embodiment of the present application. Figure 13 As shown, the data processing device includes: an acquisition unit 1301 and a processing unit 1302. The acquisition unit 1301 is used to perform the operation of the above-mentioned step 201, and the processing unit 1302 is used to perform the above-mentioned steps 202 and 203 as well as the specific encoding, interleaving and other operations involved. It should be understood that the data processing device provided in the embodiment of the present application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0209] Figure 14 FIG. 1 is a schematic diagram of the structure of a decoding device applied to a receiving end in an embodiment of the present application. Figure 14 As shown, the decoding device includes: a receiving unit 1401 and a processing unit 1402. The receiving unit 1401 is used to receive a superframe transmitted through a channel, and the processing unit 1402 is used to decode the superframe. The decoding steps include but are not limited to performing dispersion compensation, synchronization, phase recovery, demodulation, deinterleaving, decoding and other processing on the superframe data. It should be understood that the decoding device provided in the embodiment of the present application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of the present application can be integrated into a processing unit, or can be independent physical units, or two or more functional units can be integrated into a processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0210] Figure 15 FIG. 1 is another structural diagram of a data processing device in an embodiment of the present application. The data transmission device can be applied to a transmitting end or a receiving end. Figure 15As shown, the data processing device includes a processor 1501 and a memory 1502. The processor 1501 and the memory 1502 are connected to each other via a line. Specifically, the processor 1501 is used to perform data processing operations, such as the data processing operations provided in the previous embodiments of this application. In one possible implementation, the processor 1501 may include the above Figure 13 The obtaining unit 1301 and the processing unit 1302 are shown. The memory 1503 is used to store program instructions and data, and the processor 1501 performs data processing operations according to the instructions and data. The receiving end is similar and will not be described in detail in this application.

[0211] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 401 described above. When the chip integrates memory, it can perform the method steps of any one or more of the aforementioned embodiments. When the chip does not integrate memory, it can be connected to an external memory via an interface. The chip implements the actions performed by the transmitting device or receiving device in the aforementioned embodiments based on program code stored in the external memory.

[0212] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: Acquire first data; Obtaining a first bit set according to the first data and the added bits; The first bit set is forward error correction FEC encoded and interleaved to obtain a pre-framing bit set, wherein, in the first bit set, every a bits are FEC encoded to obtain b encoded bits, a and b are both positive integers, b / a is any one of 96 / 79, 80 / 63, 112 / 95, and the pre-framing bit set is used to generate a superframe.

2. The method according to claim 1, characterized in that The FEC encoding of each a bit to obtain b encoded bits specifically includes: Among the a bits, every k bits are FEC encoded to obtain n FEC bits, wherein k is a positive integer, n is a positive integer greater than k, a=c×k, b=c×n, and c is a positive integer.

3. The method according to claim 2, characterized in that c is an integer multiple of 16.

4. The method according to claim 2 or 3, characterized in that: The first data includes r rows and q columns of bits, where r is a positive integer and q is an integer multiple of 257.

5. The method according to claim 4, characterized in that q is any value of 2056, 4112, 8224 or 10280.

6. The method according to any one of claims 2 to 5, characterized in that: The performing forward error correction FEC encoding and interleaving on the first bit set to obtain a pre-framing bit set specifically includes: Distributing the first bit set to obtain 2Q sub-bit sets, performing FEC encoding on any of the sub-bit sets to obtain 2Q encoded bit sets, where Q is a positive integer greater than 0; The 2Q encoded bit sets are interleaved to obtain the pre-framing bit set.

7. The method according to claim 6, characterized in that The encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row in the W-th row of the square matrix includes the first check bit, and W is a positive integer; When W is an even number, the first check bit is formed by using at least the i-th column bit in the 0th square matrix of the W-Δ-11th row, the i-th column bit in the 1st square matrix of the W-Δ-9th row, the i-th column bit in the 2nd square matrix of the W-Δ-7th row, the i-th column bit in the 3rd square matrix of the W-Δ-5th row, the i-th column bit in the 4th square matrix of the W-Δ-3th row, and the i-th column bit in the 5th square matrix of the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer; When W is an odd number, the first check bit is formed by using at least the i-th column bit in the 0th square matrix in the W-Δ-13th row, the i-th column bit in the 1st square matrix in the W-Δ-11th row, the i-th column bit in the 2nd square matrix in the W-Δ-9th row, the i-th column bit in the 3rd square matrix in the W-Δ-7th row, the i-th column bit in the 4th square matrix in the W-Δ-5th row, and the i-th column bit in the 5th square matrix in the W-Δ-3th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

8. The method according to claim 6, characterized in that The encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row in the W-th row of the square matrix includes the first check bit, and W is a positive integer; When W%3 is 0 or 1, the first check bit is formed by at least the i-th column bit in the 0th square matrix of the W-Δ-17th row, the i-th column bit in the 1st square matrix of the W-Δ-14th row, the i-th column bit in the 2nd square matrix of the W-Δ-11th row, the i-th column bit in the 3rd square matrix of the W-Δ-8th row, the i-th column bit in the 4th square matrix of the W-Δ-5th row, and the i-th column bit in the 5th square matrix of the W-Δ-2th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer; When W%3 is 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-20th row, the i-th column bit in the 1st square matrix in the W-Δ-17th row, the i-th column bit in the 2nd square matrix in the W-Δ-14th row, the i-th column bit in the 3rd square matrix in the W-Δ-11th row, the i-th column bit in the 4th square matrix in the W-Δ-8th row, and the i-th column bit in the 5th square matrix in the W-Δ-5th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

9. The method according to claim 6, characterized in that The encoded bit set is represented as a matrix with 6 square matrices in each row, each square matrix includes 16 rows×16 columns of bits, the bit sequence in the i-th row in the W-th row of the square matrix includes the first check bit, and W is a positive integer; When W%3 is 0, the first check bit is formed by at least using the i-th column bit in the 0th square matrix of the W-Δ-16th row, the i-th column bit in the 1st square matrix of the W-Δ-13th row, the i-th column bit in the 2nd square matrix of the W-Δ-10th row, the i-th column bit in the 3rd square matrix of the W-Δ-7th row, the i-th column bit in the 4th square matrix of the W-Δ-4th row, and the i-th column bit in the 5th square matrix of the W-Δ-1th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer; When W%3 is 1 or 2, the first check bit is formed using at least the i-th column bit in the 0th square matrix in the W-Δ-19th row, the i-th column bit in the 1st square matrix in the W-Δ-16th row, the i-th column bit in the 2nd square matrix in the W-Δ-13th row, the i-th column bit in the 3rd square matrix in the W-Δ-10th row, the i-th column bit in the 4th square matrix in the W-Δ-7th row, and the i-th column bit in the 5th square matrix in the W-Δ-4th row, where i is a positive integer not less than 0 and less than 16, and Δ is a positive integer.

10. The method according to any one of claims 2 to 9, characterized in that: The added bits include padding bits.

11. The method according to claim 10, characterized in that The added bits also include cyclic redundancy check CRC bits, and the CRC is any one of CRC-16, CRC-24, CRC-32 and CRC-48.

12. The method according to any one of claims 2 to 11, characterized in that: q=10280, n=96, k=79, wherein the pre-framing bit set uses dual polarization quadrature phase shift keying DP-QPSK modulation to generate the superframe, then the interleaving granularity is L×n, the pre-framing symbol number M, r and the number of bits included in the first data d in , the number of bits d included in the first bit set scr , the number of bits added d CP The relationship is shown in any of the following table:

13. The method according to any one of claims 1 to 12, characterized in that Before performing forward error correction (FEC) encoding and interleaving on the first bit set, the method further includes: The first set of bits is scrambled.

14. A chip, characterized in that: The method comprises a processor and a communication interface, wherein the processor is connected to the communication interface via a line and is used to execute the method according to any one of claims 1 to 13.

15. A data processing device, characterized in that: The data processing device comprises a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute the instructions, so that the data processing device executes the method according to any one of claims 1 to 13.

16. A computer storage medium, characterized in that: The storage medium stores a software program, and when the software program is read and executed by one or more processors, the software program implements the method according to any one of claims 1 to 13.

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