Formation method of semiconductor structure

Abstract

The invention relates to a method for forming a semiconductor structure. The forming method comprises the following steps: after a hard mask lamination covering a gate structure and a substrate is formed, protecting an NMOS (N-channel Metal Oxide Semiconductor) forming region by using a graphical mask, and performing first anisotropic etching to expose the substrate on two sides of the gate structure in a PMOS (P-channel Metal Oxide Semiconductor) forming region; removing the patterned mask, performing second anisotropic etching, and removing a part of the nitride film in the hard mask laminated layer in the NMOS forming region while forming a source drain groove in the PMOS forming region; protecting the substrate in the NMOS forming region by using an oxide film in the hard mask lamination, forming a sigma-shaped groove in the PMOS forming region, and performing heteroepitaxy; and finally, removing the residual hard mask laminated layer and the gate upper oxide layer and the gate upper nitride layer in the gate structure by using a maskless process. According to the method, a photomask process is only used when the patterned mask is formed, so that the cost of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process can be reduced, the damage to the substrate can be reduced, and the performance of a device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In MOS transistors, the mobility of carriers affects the channel current, which in turn affects the device performance. For example, low carrier mobility will reduce the working saturation current and response speed of the device. Therefore, in the CMOS process, the source / drain regions of PMOS transistors (hereinafter referred to as PMOS) and NMOS transistors (hereinafter referred to as NMOS) are often processed separately, wherein, in the PMOS formation area, grooves with ∑-shaped side walls (hereinafter referred to as ∑-shaped grooves) are formed in the substrate on both sides of the gate and silicon germanium (SiGe) is epitaxially grown in the ∑-shaped grooves as the source / drain regions of the PMOS.

[0003] In an existing CMOS process, corresponding gate structures are formed in the NMOS formation region and the PMOS formation region on the surface of the substrate, respectively, and then a hard mask layer is formed along the surface of the substrate and the gate structure, and then the hard mask layer of the PMOS formation region is etched back non-isotropically and the substrate is further etched to form a groove for epitaxially growing germanium silicon. To avoid damaging the gate during the etching process, each of the gate structures includes a gate nitride layer covering the gate top surface and a sidewall covering the gate side. During the groove etching process, in order to protect the NMOS formation region, a mask layer is used to protect the NMOS formation region. After the germanium silicon epitaxy of the PMOS formation region is completed, another mask layer is used to protect the PMOS formation region and expose the NMOS formation region, and the part of the hard mask layer covering the NMOS formation region is removed to expose the gate nitride layer covering the gate top surface, and then the other mask layer is removed, and the remaining hard mask layer and the gate nitride layer in the PMOS formation region and the NMOS formation region are removed.

[0004] In the above-mentioned CMOS process, at least two photomask processes are required to form a groove in the PMOS formation area, perform a silicon germanium epitaxial process, and remove the hard mask layer in the PMOS formation area and the NMOS formation area as well as the nitride layer on the gate, resulting in high costs. Moreover, when the above-mentioned other mask layer is used to protect the PMOS formation area and the NMOS formation area is exposed and part of the hard mask layer in the NMOS formation area is etched, the substrate in the NMOS formation area is easily etched back (recess) due to over-etching during the etching process, which is not conducive to the performance of the NMOS. Summary of the invention

[0005] In order to reduce the manufacturing cost of CMOS process and improve the device performance, the present invention provides a method for forming a semiconductor structure.

[0006] The method for forming a semiconductor structure provided by the present invention comprises:

[0007] Providing a substrate, wherein the substrate is arranged with a PMOS formation region and an NMOS formation region;

[0008] A first gate structure and a second gate structure are formed in the PMOS formation region and the NMOS formation region, respectively, wherein the first gate structure and the second gate structure at least include a gate dielectric layer, a gate, an oxide layer on the gate, a nitride layer on the gate, and a sidewall formed on the side of the gate stacked on the substrate;

[0009] Conformally forming a hard mask stack along the surfaces of the substrate, the first gate structure and the second gate structure, the hard mask stack comprising an oxide film and a nitride film stacked on the oxide film;

[0010] forming a patterned mask to cover the NMOS formation region and expose the PMOS formation region;

[0011] Performing a first anisotropic etching to expose the nitride layer on the gate in the first gate structure and the substrate surface where the PMOS formation region is located on both sides of the first gate structure;

[0012] removing the patterned mask to expose the hard mask stack in the NMOS formation area;

[0013] Performing a second anisotropic etching to form source-drain grooves in the substrate located at both sides of the first gate structure in the PMOS formation region, and simultaneously etching the nitride film in the hard mask stack in the NMOS formation region to expose the oxide film located on the top surface of the second gate structure and the top surface of the substrate;

[0014] The inner wall of the source / drain groove is etched to transform the source / drain groove into a Σ-shaped groove, and epitaxial growth is performed in the Σ-shaped groove to form a heteroepitaxial layer; and a maskless process is used to remove at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation area and the NMOS formation area.

[0015] Optionally, removing at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region by using a maskless process comprises:

[0016] Removing the oxide film exposed in the NMOS formation region to expose the nitride layer on the gate in the second gate structure and the substrate in the NMOS formation region;

[0017] removing the nitride film in the hard mask layer stack covering the sides of the first gate structure and the second gate structure, and removing the nitride layer on the gate in the first gate structure and the second gate structure; and

[0018] The oxide film in the hard mask layer covering the sides of the first gate structure and the second gate structure and the oxide layer on the gate are removed.

[0019] Optionally, the first anisotropic etching and the second anisotropic etching are performed by dry etching.

[0020] Optionally, wet etching is used to remove the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region.

[0021] Optionally, the nitride layer on the gate and the nitride film in the hard mask stack are both made of silicon nitride, and the nitride film and the nitride layer on the gate are removed by the same wet etching process.

[0022] Optionally, in the first gate structure and the second gate structure, the sidewall spacer includes a side oxide layer formed on a side of the gate and a side nitride layer formed on a side of the side oxide layer away from the gate.

[0023] Optionally, the patterned mask at least includes a bottom anti-reflection layer and a photoresist layer formed on the bottom anti-reflection layer.

[0024] Optionally, when performing the second anisotropic etching, an etching selectivity ratio between the substrate and the nitride film ranges from 2 to 8.

[0025] Optionally, in the hard mask stack, the thickness of the oxide film is The thickness of the nitride film is

[0026] Optionally, at least two second gate structures are formed in the PMOS formation region, wherein one Σ-shaped groove is formed between two adjacent second gate structures.

[0027] In the method for forming a semiconductor structure provided by the present invention, after forming a hard mask stack, a patterned mask is used to protect the NMOS formation area, and a first anisotropic etching is performed to expose the substrate on both sides of the first gate structure, and then the patterned mask is removed, and a second anisotropic etching is performed, so that while forming source and drain grooves in the PMOS formation area, the oxide film covering the top surface of the second gate structure and the top surface of the substrate in the hard mask stack of the NMOS formation area is exposed, and then the oxide film is used to protect the substrate of the NMOS formation area, a ∑-shaped groove is formed in the PMOS formation area and a heteroepitaxial layer is epitaxially grown, and finally a maskless process is used to remove the remaining hard mask stack, the oxide layer on the gate, and the nitride layer on the gate in the PMOS formation area and the NMOS formation area. The above method only uses one mask process when forming the patterned mask, which helps to reduce the cost of the CMOS process.

[0028] In addition, in the method for forming a semiconductor structure provided by the present invention, in the hard mask stack covering the surface of the substrate in the NMOS formation area, the nitride film is first removed and the oxide film is retained. After a ∑-shaped groove is formed in the PMOS formation area and a heteroepitaxial layer is epitaxially grown, the remaining oxide film in the NMOS formation area can be removed by wet etching. Over-etching is easy to control and causes little damage to the substrate, which helps to improve device performance compared to the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1A to 1J It is a cross-sectional schematic diagram of a CMOS process at multiple steps.

[0030] Figure 2 It is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] FIG. 3A to FIG. 3K is a schematic cross-sectional view of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following is a further detailed description of the method for forming a semiconductor structure of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0033] In order to more clearly understand the embodiments of the present invention, Figures 1A to 1J A CMOS process that needs to be improved is introduced, and the CMOS process includes the following processes:

[0034] First, refer to Figure 1A , providing a substrate 100 (such as a silicon substrate), wherein the substrate 100 includes a PMOS formation region A1 and an NMOS formation region A2 separated by shallow trench isolation STI, and gate structures for manufacturing PMOS and NMOS are respectively formed on the substrate 100 in the PMOS formation region A1 and the NMOS formation region A2 (as shown in the dotted box area), wherein the gate structures each include a gate dielectric layer 101, a gate 102, an oxide layer 103 on the gate, and a nitride layer 104 on the gate stacked on the substrate 100, and a sidewall SP formed on the side of the gate 102;

[0035] Next, refer to Figure 1B , forming a hard mask stack HM along the substrate 100 and the surface of each of the gate structures, wherein the hard mask stack HM includes an oxide film 105 and a nitride film 106 stacked on the oxide film 105;

[0036] Afterwards, refer to Figure 1C , forming a patterned first mask layer M1, wherein the first mask layer M1 covers the NMOS formation region A2 and exposes the PMOS formation region A1;

[0037] Next, refer to Figure 1D, performing a first anisotropic etching to remove the hard mask layer HM covering the top surface of the gate structure and the hard mask layer HM covering the surface of the substrate 100 in the PMOS formation region A1, and further etching the substrate 100 to form a source-drain groove T1 in the PMOS formation region A1, and the gate nitride layer 104 in the gate structure is exposed. During the etching process, the gate nitride layer 104 can protect the gate 102, and the first mask layer M1 can protect the hard mask stack HM in the NMOS formation region A2 and the substrate 100 from being etched;

[0038] Afterwards, refer to Figure 1E , removing the first mask layer M1, at this time, the hard mask stack HM conformally covering the NMOS formation region A2 is exposed;

[0039] Next, refer to Figure 1F , using the hard mask stack HM to protect the NMOS forming area A2, etching the inner wall of the source / drain groove T1 to transform the source / drain groove T1 into a Σ-shaped groove T2, and performing epitaxial growth in the Σ-shaped groove T2 to form a germanium silicon layer 107;

[0040] Afterwards, refer to Figure 1G , forming a patterned second mask layer M2, wherein the second mask layer M2 covers the PMOS forming region A1 and exposes the NMOS forming region A2;

[0041] Next, refer to Figure 1H , performing a second anisotropic etching to remove the hard mask stack HM covering the top surface of the gate structure and the hard mask stack HM covering the surface of the substrate 100 in the NMOS formation region A2, so that the gate nitride layer 104 located on the top surface of the gate 102 is exposed;

[0042] Afterwards, refer to Fig. 1I , removing the second mask layer M2;

[0043] Next, referring to 1J, since the gate nitride layer 104 and the hard mask stack HM located on the side of each gate structure are exposed, the gate nitride layer 104 and the hard mask stack HM located on the side of each gate structure can be removed uniformly and step by step. The obtained semiconductor structure includes a substrate 100, the gate structure formed on the substrate 100, and a source region and a drain region of a PMOS formed in the substrate 100 in the PMOS formation area A1, the gate structure includes a gate dielectric layer 101, a gate 102, and a sidewall SP covering the side of the gate 102, and the source region and the drain region of the PMOS include a Σ-shaped groove T2 formed on both sides of the gate structure in the PMOS formation area A1 and a silicon germanium layer 107 filled in the Σ-shaped groove T2.

[0044] In the CMOS process, at least two mask processes are required to form the Σ-shaped groove T2 in the PMOS forming region A1, perform the SiGe epitaxial process, and remove the hard mask stack HM in the PMOS forming region A1 and the NMOS forming region A2 and the nitride layer 104 on the gate, resulting in high cost. In addition, when the second mask layer M2 is used to protect the PMOS forming region A1 and expose the NMOS forming region A2 and a portion of the hard mask stack HM in the NMOS forming region A2 is etched (see Figure 1H ), the substrate 100 in the NMOS forming area A2 is easily etched back (recess) due to over-etching during the etching process, which is not good for the performance of the NMOS.

[0045] The following combination Figure 2 and FIG. 3A to FIG. 3K A method for forming a semiconductor structure according to an embodiment of the present invention is introduced.

[0046] Reference Figure 2 and Figure 3A , perform step S1, provide a substrate 100, the substrate 100 is arranged with a PMOS formation region A1 and an NMOS formation region A2. The PMOS formation region A1 and the NMOS formation region A2 respectively represent different ranges in a plane parallel to the surface of the substrate 100. The substrate 100 can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (for example, a gallium nitride substrate or a gallium arsenide substrate), etc., and a doped region and / or an isolation structure can be formed in the substrate 100. The PMOS formation region A1 and the NMOS formation region A2 are isolated, for example, by shallow trench isolation (STI).

[0047] In the PMOS formation region A1, the substrate 100 can be used as the source region and drain region of the PMOS by forming Σ-shaped grooves on both sides of the gate structure and epitaxially growing a heterogeneous material capable of improving the hole mobility in the channel region in the Σ-shaped grooves. In this embodiment, the substrate 100 is, for example, a silicon substrate, and in the PMOS formation region A1, Σ-shaped grooves are subsequently formed on both sides of the gate structure and a germanium silicon layer is epitaxially grown as the source region and drain region of the PMOS.

[0048] Continue to refer to Figure 3A , performing step S2 to form a first gate structure 10 and a second gate structure 20 in the PMOS forming region A1 and the NMOS forming region A2 respectively.

[0049] like Figure 3AAs shown, the PMOS forming region A1 is formed with at least one first gate structure 10. As an example, the PMOS forming region A1 is formed with more than two first gate structures 10. The NMOS forming region A2 is formed with at least one second gate structure 10. As an example, the NMOS forming region A2 is formed with more than two second gate structures 20. The first gate structure 10 and the second gate structure 20 can be formed simultaneously on the substrate 100, and thus can have the same or similar materials and structures. In this embodiment, the first gate structure 10 and the second gate structure 20 both include at least a gate dielectric layer 101, a gate 102, an oxide layer 103 on the gate, a nitride layer 104 on the gate, and a sidewall SP formed on the side of the gate 102. The gate dielectric layer 101 is, for example, silicon oxide. The gate 102 is, for example, a doped polysilicon gate, a metal gate, a multi-layer composite structure gate, etc. The oxide layer 103 on the gate is, for example, silicon oxide. The nitride layer 104 on the gate is, for example, silicon nitride. The nitride layer 104 on the gate can protect the gate 102 in the subsequent process of engraving a groove in the substrate 100. The sidewall SP is, for example, a composite sidewall, which includes a side oxide layer SP1 formed on the side of the gate 102 and a side nitride layer SP2 formed on the side of the side oxide layer SP1 away from the gate 102, and the sidewall SP covers the gate dielectric layer 101, the gate 102, the gate oxide layer 103 and the side of the nitride layer 104 on the gate.

[0050] Reference Figure 2 and Figure 3B , perform step S3 to conformally form a hard mask stack HM along the surface of the substrate 100, the first gate structure 10 and the second gate structure 20, wherein the hard mask stack HM includes an oxide film 105 (for example, silicon oxide) and a nitride film 106 (for example, silicon nitride) stacked on the oxide film 105. In the subsequent etching process for forming source and drain grooves in the PMOS formation area A1, the hard mask stack HM is first etched and the substrate 100 is further etched to facilitate the control of etching accuracy. The hard mask stack HM can also protect the NMOS formation area A2 when the semiconductor process is performed in the PMOS formation area A1. As an example, in the hard mask stack HM, the thickness of the oxide film 105 is The thickness of the nitride film 106 is

[0051] Reference Figure 2 and Figure 3C, perform step S4 to form a patterned mask 110, wherein the patterned mask 110 covers the NMOS formation region A2 and exposes the PMOS formation region A1. The patterned mask 110 is used to protect the hard mask stack HM of the NMOS formation region A2 when the hard mask stack HM of the PMOS formation region A1 is subsequently etched. The patterned mask 110 may include a photoresist layer (PR). In the present embodiment, the patterned mask 110 at least includes a bottom anti-reflection layer (BARC) (not shown) and a photoresist layer formed on the bottom anti-reflection layer.

[0052] Reference Figure 2 and Figure 3D , step S5 is performed to perform a first anisotropic etching to expose the gate nitride layer 104 in the first gate structure 10 and the surface of the substrate 100 where the PMOS formation region A1 is located on both sides of the first gate structure 10. The first anisotropic etching is performed, for example, by dry etching, and its etching direction is, for example, along the normal direction of the substrate 100 (i.e., the direction perpendicular to the top surface of the substrate 100). After etching, the lateral extension portion of the hard mask stack HM located above the top surface of the first gate structure 10 and the lateral extension portion located on the surface of the substrate 100 are removed. During the etching process, the nitride film 106 in the hard mask stack HM can be first etched by a silicon nitride etching process to expose the oxide film 105, and then the oxide film 105 can be etched by a silicon oxide etching process, thereby exposing the gate nitride layer 104 in the first gate structure 10 and the surface of the substrate 100 on both sides of the first gate structure 10. During the etching process, the gate nitride layer 104 can protect the gate 102, and the patterned mask 110 can protect the hard mask stack HM in the NMOS formation region A2 and the substrate 100 from being etched.

[0053] Reference Figure 2 and Figure 3E , executing step S6, removing the patterned mask 110, so that the hard mask stack HM of the NMOS formation area A2 is exposed.

[0054] Reference Figure 2 and Figure 3F , step S7 is performed to perform a second anisotropic etching to form source-drain grooves T1 in the substrate 100 at both sides of the PMOS formation region A1 located in the first gate structure 10. Due to the protection of the hard mask stack HM, the substrate 100 at the NMOS formation region A2 will not be etched.

[0055] The longitudinal cross-section of the source-drain groove T1 is, for example, U-shaped. In this embodiment, by adjusting the etching process, the nitride film 106 in the hard mask stack HM of the NMOS formation region A2 can be etched simultaneously when the second anisotropic etching is performed. More specifically, the lateral extension portion of the nitride film 106 in the hard mask stack HM located above the top surface of the second gate structure 20 and the lateral extension portion of the nitride film 106 located on the surface of the substrate 100 are removed, thereby exposing the oxide film 105 located on the top surface of the second gate structure 20 and the top surface of the substrate 100 in the NMOS formation region A2. The second anisotropic etching is, for example, dry etching. Optionally, when the second anisotropic etching is performed, the etching selectivity of the substrate 100 and the nitride film 106 in the hard mask stack HM ranges from 2 to 8, more specifically, for example, 5. The specific etching process parameters and etching selectivity can be adjusted according to the thickness of the nitride film 106.

[0056] Reference Figure 2 , Figure 3G and Figure 3H , performing step S8, etching the inner wall of the source-drain groove T1 to transform the source-drain groove T1 into a Σ-shaped groove T2, and performing epitaxial growth in the Σ-shaped groove T2 to form a heteroepitaxial layer. In this embodiment, the heteroepitaxial layer is a germanium silicon layer 107.

[0057] like Figure 3G As shown, the inner wall of the source-drain groove T1 is first etched to transform the source-drain groove T1 into a ∑-shaped groove T2. In this process, since the substrate 100 of the NMOS forming region A2 is covered by the oxide film 105 in the hard mask stack HM, by retaining the oxide film 105 of appropriate thickness and selecting an etching process with high etching selectivity to the substrate 100 and silicon oxide, the substrate 100 of the NMOS forming region A2 can be formed in the PMOS forming region A1 while the substrate 100 is not etched. In this embodiment, for example, tetramethylammonium-hydroxide (TMAH) etchant is selected to etch the inner wall of the source-drain groove T1 to transform the source-drain groove T1 into a ∑-shaped groove T2. The sidewall of the ∑-shaped groove T2 has a concave angle extending below the first gate structure 10. The concave angle is conducive to the subsequently formed source region or drain region to generate stress on the substrate 100 in the channel region to improve the carrier mobility. As an example, at least two first gate structures 10 are formed in the PMOS forming region A1 , wherein a Σ-shaped groove T2 is formed between two adjacent first gate structures 10 , and the Σ-shaped groove T2 is shared by the two adjacent first gate structures 10 .

[0058] like Figure 3HAs shown, epitaxial growth is performed in the ∑-shaped groove T2 to form a germanium silicon layer 107 by using an epitaxial growth process. Specifically, a germanium silicon seed layer can be first formed on the inner wall of the ∑-shaped groove T2, and then a selective epitaxial process can be performed to form the germanium silicon layer 107. During the epitaxial process, P-type doping ions (such as boron) can be added to the germanium silicon layer 107 to improve conductivity. After the germanium silicon layer 107 is formed, a silicon layer can be formed on the surface of the germanium silicon layer 107 by an epitaxial process. During the epitaxial process, since the substrate 100 of the NMOS formation area A2 is covered by the oxide film 105 in the hard mask stack HM, epitaxial growth can be avoided on the surface of the substrate 100 of the NMOS formation area A2.

[0059] Reference Figure 2 , perform step S9, and use a maskless process to remove at least the remaining hard mask stack HM, the gate oxide layer 103, and the gate nitride layer 104 in the PMOS formation area A1 and the NMOS formation area A2.

[0060] Specifically, refer to Fig. 3I First, the oxide film 105 exposed in the NMOS formation region A2 is removed to expose the gate nitride layer 104 in the second gate structure 20 and the substrate 100 of the NMOS formation region A2. As an example, the etching selectivity of the oxide film 105 and other materials exposed on the substrate 100 can be used to select a corresponding etching process to remove the oxide film 105 without a mask, and specifically wet etching can be used, more specifically, for example, a dilute hydrofluoric acid (DHF) solution is used. Since the thickness of the oxide film 105 is set to be relatively thin, the etching time can be controlled so that the oxide film 105 is removed without damaging the substrate 100. For example, a DHF solution with a ratio of 1:100 is used, and the etching time is about 30s to 90s.

[0061] Reference Figure 3J Then, the nitride film 106 in the hard mask stack M2 covering the sides of the first gate structure 10 and the second gate structure 20 is removed, and the nitride layer 104 on the gate in the first gate structure 10 and the second gate structure 20 is removed.

[0062] By removing the oxide film 105 exposed in the NMOS formation region A2, the gate nitride layer 104 in the second gate structure 20 is exposed, and the gate nitride layer 104 in the first gate structure 10 has been exposed in step S5, so that the gate nitride layer 104 in the first gate structure 10 and the second gate structure 20 can be removed by the same etching process. In this embodiment, the gate nitride layer 104 and the nitride film 106 in the hard mask stack HM are both made of silicon nitride, so the gate nitride layer 104 and the nitride film 106 in the hard mask stack HM covering the sides of the first gate structure 10 and the second gate structure 20 can be removed by the same etching process, and the etching selectivity of silicon nitride and other materials exposed on the substrate 100 is used to select the corresponding etching process to remove the nitride film 106 and the gate nitride layer 104 without the need for a mask. As an example, wet etching is used to remove the nitride film 106 and the nitride layer 104 on the gate, for example, a phosphoric acid solution with a ratio of 85% is used, and the etching time is about 200s to 600s.

[0063] Afterwards, if Figure 3K As shown, the oxide film 105 in the hard mask stack HM covering the side of the first gate structure 10 and the second gate structure 20 is removed. In this process, the gate oxide layer 103 exposed on the top of the first gate structure 10 and the second gate structure 20 is also removed. In this embodiment, the oxide film 105 and the gate oxide layer 103 are both silicon oxide. Therefore, by utilizing the etching selectivity of silicon oxide and other materials exposed on the substrate 100, a corresponding etching process can be selected to remove the oxide film 105 and the gate oxide layer 103 without a mask, for example, wet etching can be used, specifically, a DHF solution with a ratio of 1:100 can be used, and the etching time is about 30s to 90s.

[0064] In the method for forming a semiconductor structure described in the above embodiment, after forming a hard mask stack HM covering the first gate structure 10, the second gate structure 20 and the substrate 100, a patterned mask 110 is used to protect the NMOS formation region A2, and the hard mask stack HM of the PMOS formation region A1 is etched by a first anisotropic etching to expose the substrate 100 on both sides of the first gate structure 10 of the PMOS formation region A1; then the patterned mask 110 is removed, and a second anisotropic etching is performed to form a source-drain groove T1 in the substrate 100 on both sides of the first gate structure 10 of the PMOS formation region A1, and at the same time expose the The oxide film 105 covering the top surface of the second gate structure 20 and the top surface of the substrate 100 in the hard mask stack HM of the NMOS formation region 20 is removed; the substrate 100 of the NMOS formation region A2 is then protected by the oxide film 105 of the NMOS formation region A2, a ∑-shaped groove T2 is formed in the PMOS formation region A1, and a germanium silicon layer 107 is epitaxially grown in the ∑-shaped groove T2; finally, a maskless process is used to remove the remaining hard mask stack HM in the PMOS formation region A1 and the NMOS formation region A2, as well as the gate oxide layer 103 and the gate nitride layer 104 in the first gate structure 10 and the second gate structure 20. The above method uses only one photomask process when forming the patterned mask 110, which helps to reduce the cost of the CMOS process.

[0065] In addition, in the method for forming the semiconductor structure described in the above embodiment, in the hard mask stack HM covering the surface of the substrate 100 in the NMOS formation region A2, the nitride film 106 is first removed and the oxide film 105 is retained. After a ∑-shaped groove T2 is formed in the PMOS formation region A1 and a germanium silicon layer 107 is epitaxially grown, the remaining oxide film 105 in the NMOS formation region A2 can be removed by wet etching. Over-etching is easy to control, with little damage to the substrate 100, thereby reducing the risk of the substrate 100 being etched back, thereby helping to improve device performance.

[0066] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate is arranged with a PMOS formation region and an NMOS formation region; A first gate structure and a second gate structure are formed in the PMOS formation region and the NMOS formation region, respectively, wherein the first gate structure and the second gate structure at least include a gate dielectric layer, a gate, an oxide layer on the gate, a nitride layer on the gate, and a sidewall formed on the side of the gate stacked on the substrate; Conformally forming a hard mask stack along the surfaces of the substrate, the first gate structure and the second gate structure, the hard mask stack comprising an oxide film and a nitride film stacked on the oxide film; forming a patterned mask to cover the NMOS formation region and expose the PMOS formation region; Performing a first anisotropic etching to expose the nitride layer on the gate in the first gate structure and the substrate surface where the PMOS formation region is located on both sides of the first gate structure; removing the patterned mask to expose the hard mask stack in the NMOS formation area; Performing a second anisotropic etching to form source-drain grooves in the substrate located at both sides of the first gate structure in the PMOS formation region, and simultaneously etching the nitride film in the hard mask stack in the NMOS formation region to expose the oxide film located on the top surface of the second gate structure and the top surface of the substrate; The inner wall of the source / drain groove is etched to transform the source / drain groove into a Σ-shaped groove, and epitaxial growth is performed in the Σ-shaped groove to form a heteroepitaxial layer; and a maskless process is used to remove at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation area and the NMOS formation area.

2. The forming method according to claim 1, characterized in that: Removing at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region by using a maskless process comprises: Removing the oxide film exposed in the NMOS formation region to expose the nitride layer on the gate in the second gate structure and the substrate in the NMOS formation region; removing the nitride film in the hard mask layer stack covering the sides of the first gate structure and the second gate structure, and removing the nitride layer on the gate in the first gate structure and the second gate structure; and The oxide film in the hard mask layer covering the sides of the first gate structure and the second gate structure and the oxide layer on the gate are removed.

3. The forming method according to claim 1, characterized in that: The first anisotropic etching and the second anisotropic etching are performed by dry etching.

4. The forming method according to claim 1, characterized in that: The remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region are removed by wet etching.

5. The forming method according to claim 4, characterized in that: The nitride layer on the gate and the nitride film in the hard mask stack are both made of silicon nitride, and the nitride film and the nitride layer on the gate are removed by the same wet etching process.

6. The forming method according to claim 1, characterized in that: In the first gate structure and the second gate structure, the sidewall spacer includes a side oxide layer formed on a side of the gate and a side nitride layer formed on a side of the side oxide layer away from the gate.

7. The forming method according to claim 1, characterized in that: The patterned mask at least includes a bottom anti-reflection layer and a photoresist layer formed on the bottom anti-reflection layer.

8. The forming method according to any one of claims 1 to 7, characterized in that: When performing the second anisotropic etching, the etching selectivity ratio between the substrate and the nitride film is in the range of 2-8.

9. The forming method according to any one of claims 1 to 7, characterized in that: In the hard mask stack, the thickness of the oxide film is The thickness of the nitride film is 10. The forming method according to any one of claims 1 to 7, characterized in that: At least two second gate structures are formed in the PMOS forming region, wherein one Σ-shaped groove is formed between two adjacent second gate structures.

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