Dual-channel single-pole double-throw analog switch circuit

Abstract

The invention belongs to the technical field of analog switches, and particularly relates to a double-channel single-pole double-throw analog switch circuit which comprises two turn-off leakage compensation modules, two ISO isolation circuits, two turn-on leakage compensation modules, eight MOS tubes M5-M12 and a current source. All the devices are correspondingly connected according to a circuit diagram to form an analog switch circuit; the invention designs a dual-channel single-pole double-throw analog switch, a 0.25 [mu] m BCD process is adopted, two groups of completely consistent single-pole double-branch CMOS switches are arranged in a chip, the normal temperature interval is-40 DEG C to 125 DEG C, the analog switch can normally work under three power supply conditions of + / -15V, 12V, 0V and + / -5V, and the analog switch has the advantages of low on-resistance, high switching speed, high reliability and the like. And conduction electric leakage and turn-off electric leakage are small.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog switches, and particularly relates to a dual-channel single-pole double-throw analog switch circuit. Background Art

[0002] A dual-channel single-pole double-throw (DPST) analog switch is an electrical component used for signal switching. It has a wide range of applications in analog signal processing, communication, audio and video equipment, and other electronic systems. Its main function is to switch the signal path, select the input or output channels of two signals, and is suitable for routing, adjusting, and controlling multi-channel signals. This switch can handle the switching operations of two signal channels simultaneously, so it is particularly important in audio, video, and wireless communication systems.

[0003] Most of the existing technologies involve traditional analog switch designs, mainly implemented through mechanical relays, field-effect transistors (FETs), or CMOS technology. Among these technologies, mechanical relays are not suitable for some high-frequency and high-speed applications due to their slow response speed, short lifespan, and high power consumption. Solid-state analog switches can provide faster response, longer service life, and lower power consumption, especially having advantages in occasions that require frequent switching, but there are still technical bottlenecks in terms of low distortion, high isolation, and miniaturization. Patent publication number CN102830000A discloses a dual-channel single-pole double-throw relay, which describes the design of a dual-channel single-pole double-throw relay for audio signal routing and focuses on the application of the relay in audio signals. However, its disadvantages are slow response time and high power consumption. Patent publication number CN103410926A discloses an analog signal switch based on MOSFET, which uses MOSFET to implement the technology of analog signal switching. The advantages are low power consumption and high switching speed, but the requirements for low distortion and high isolation are not fully met.

[0004] In summary, the following problems mainly exist in current traditional mechanical relays and some solid-state analog switches: Slow response speed: The switching speed of mechanical relays is relatively slow, which limits their application in high-speed signal processing. Especially in scenarios requiring high-frequency switching, their performance cannot meet the requirements. High power consumption: Especially for mechanical relays, because they require a large current to drive mechanical movement, resulting in high power consumption; while although the power consumption of solid-state switches is relatively low, there may be high conduction losses. Signal distortion: Existing solid-state analog switches are not optimized for low-distortion signal transmission in design, and there may be problems such as insertion loss and intermodulation distortion, affecting the purity of the signal. Low-frequency and high-frequency performance issues: In high-frequency applications, the frequency response of some existing switches is not ideal, with large parasitic capacitance and inductance, resulting in signal distortion or interference. For dual-channel applications, there is often a lack of sufficient isolation in the existing technology, which may lead to signal interference between channels. Low integration level: Most existing technologies still have problems of low integration level, large volume, and more occupied space, and cannot meet the requirements of modern miniaturized devices. Summary of the Invention

[0005] To solve the above problems existing in the prior art, the present invention proposes a dual-channel single-pole double-throw analog switch circuit, and the circuit structure includes: two turn-off leakage compensation modules, two ISO isolation circuits, two turn-on leakage compensation modules, 8 MOS transistors M5 to M12, and a current source;

[0006] The connection relationships of each circuit include: the gate of M5 is connected to the gate of M6, the drain of M5 is respectively connected to the first turn-off leakage compensation module, the first ISO isolation circuit, the first turn-on leakage compensation module, and the drain of M7, the substrate of M5 is respectively connected to the substrate of M6, the source of M10, and the positive pole of the current source, the source of M5 is connected to the source of M6; the drain of M6 is respectively connected to the second turn-off leakage compensation module, the second ISO isolation circuit, the second turn-on leakage compensation module, and the drain of M8; the gate of M10 accesses the CPB signal, the drain of M10 is connected to the drain of M9; the gate of M9 accesses the GNN_B signal, the source of M9 accesses the VSS signal; the negative pole of the current source is connected to the source of M11; the gate of M11 accesses the GNP signal, the drain of M11 accesses the VCC signal; the gate of M7 is connected to the gate of M8, the source of M7 is respectively connected to the source of M8 and the drain of M12, the gate of M12 accesses the GNN signal, and the source of M12 accesses the VSS signal.

[0007] Advantages of the present invention:

[0008] The present invention designs a dual-channel single-pole double-throw analog switch, which adopts a 0.25um BCD process. The chip internally contains two sets of completely identical single-pole double-branch CMOS switches. Its normal temperature range is from -40°C to 125°C, and it can work normally under three power supply conditions of ±15V, 12V and 0V, and ±5V. This analog switch has the advantages of low on-resistance, fast switching speed, small on-leakage and off-leakage, small total harmonic distortion, and the switch action that can ensure turn-off first and then turn-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is the circuit structure diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0011] In this embodiment, a dual-channel single-pole double-throw analog switch adopts a 0.25um BCD process. The chip internally contains two sets of completely identical single-pole double-branch CMOS switches. Its normal temperature range is from -40°C to 125°C, and it can work normally under three power supply conditions of ±15V, 12V and 0V, and ±5V. This analog switch has the advantages of low on-resistance, fast switching speed, small on-leakage and off-leakage, small total harmonic distortion, and the switch action that can ensure turn-off first and then turn-on. It can be well applied to the transmission of audio signals.

[0012] A dual-channel single-pole double-throw analog switch circuit, as Figure 1As shown in the figure, the circuit structure includes: two turn-off leakage compensation modules, two ISO isolation circuits, two turn-on leakage compensation modules, eight MOS transistors M5 to M12, and a current source; the connection relationships of each circuit include: the gate of M5 is connected to the gate of M6, the drain of M5 is respectively connected to the first turn-off leakage compensation module, the first ISO isolation circuit, the first turn-on leakage compensation module, and the drain of M7, the substrate of M5 is respectively connected to the substrate of M6, the source of M10, and the positive pole of the current source, the source of M5 is connected to the source of M6; the drain of M6 is respectively connected to the second turn-off leakage compensation module, the second ISO isolation circuit, the second turn-on leakage compensation module, and the drain of M8; the gate of M10 is connected to the CPB signal, the drain of M10 is connected to the drain of M9; the gate of M9 is connected to the GNN_B signal, the source of M9 is connected to the VSS signal; the negative pole of the current source is connected to the source of M11; the gate of M11 is connected to the GNP signal, the drain of M11 is connected to the VCC signal; the gate of M7 is connected to the gate of M8, the source of M7 is respectively connected to the source of M8 and the drain of M12, the gate of M12 is connected to the GNN signal, the source of M12 is connected to the VSS signal.

[0013] In this embodiment, the circuit structure of the turn-off leakage compensation module is the same as that of the turn-on leakage compensation module.

[0014] The turn-off leakage compensation module is composed of two MOS transistors M1 and M13, where the drain of M13 is connected to the VSS signal, the gate of M13 is respectively connected to the source of M13 and the source of M1, and the drain of M1 is connected to the drain of M5.

[0015] In this embodiment, the first ISO isolation circuit is composed of a MOS transistor M17 and a resistor R1. One end of the resistor R1 is connected to the VCC signal, the other end of R1 is respectively connected to the ISO signal and the source of M17. The drain of M17 is connected to the VSS signal, and the gate of M17 is connected to the drain of M7. The structure of the first ISO isolation circuit is the same as that of the second ISO isolation circuit.

[0016] In this embodiment, a complementary CMOS analog switch is adopted. The complementary type uses two complementary MOS transistors, and the complementary structure itself can be used to reduce the change in its on-resistance and make it more stable.

[0017] For the design of the main switch circuit: isolation is performed on the ISO terminal and the D terminal at the NMOS switch transistor, effectively handling the leakage of the ISO terminal.

[0018] The switch main tube adopts a back-to-back structure: The back-to-back MOS tubes can withstand bidirectional current by connecting the sources of the two MOS tubes. This structure can achieve current conduction in both forward and reverse directions, and at the same time has a lower on-resistance, which can greatly improve the symmetry and flatness of the on-resistance curve and better reduce signal distortion.

[0019] Design of the drive circuit: To ensure the reliability of the devices inside the chip, a level shift circuit is designed in the drive module, and the gate control voltage of the switch main tube is designed to ensure that under the power supply of ±15V, the gate control voltage can follow the input signal voltage, dynamically adjust the gate voltage of the MOS tube, further reduce the on-resistance, and at the same time ensure high-speed signal switching to guarantee the device reliability.

[0020] Design of the logic control circuit: The design of the logic control circuit ensures that it judges as a low level when the maximum logic level input is 0.4V, and judges as a high level when the minimum logic level input is 2.1V.

[0021] To ensure that the chip is suitable for multiplexer applications, a logic control circuit is designed to ensure that both types of switches of the chip adopt the switch action of opening first and then closing.

[0022] Design of the internal power supply module and current mirror module: Since the gate-source breakdown voltage of the LDMOS in this process is only 24V, an 8V internal power supply is designed under the ±15V power supply. Since the drive module control adopts the voltage control method of R*I, a current mirror module is designed.

[0023] In this embodiment, GPP and GPN are dynamically changed by the external module through the input signal obtained from the S port, so that Vgs remains relatively unchanged to reduce harmonic distortion. GPB is the S-terminal voltage of M5 and M6. GNN_B and GNP are at a high level when the switch is on, making M9 conduct. Through M10, GPX = GPB + Vth. GPB is the input voltage signal. When the switch is off, GNN_B is at a low level, making M9 turn off. At this time, GNP is at a low level and M11 conducts. At this time, GPX = VCC.

[0024] SS is the S-terminal voltage of M7 and M8. When the switch is on, GNN is at a low level and M12 turns off. At this time, SS is the input voltage signal. When the switch is off, GNN is at a high level and M12 conducts. SS = VSS.

[0025] Embodiment 1:

[0026] Existing double-channel single-pole double-throw switches mostly use mechanical relays or traditional solid-state switches, which have problems such as slow response speed, high power consumption, and distortion. This embodiment proposes a CMOS-based double-channel single-pole double-throw analog switch design, aiming to provide higher switching speed, lower power consumption, and ensure low distortion and high signal isolation.

[0027] The double-channel single-pole double-throw analog switch of this embodiment includes two independent switch channels, and each channel is used. By controlling the gate voltage of the MOSFET, the switch state is switched to select different signal paths.

[0028] MOSFET design: Each channel uses two complementary MOS transistors. The complementary type uses two complementary MOS transistors, and the complementary structure itself can be used to reduce the change in its on-resistance and make it more stable. The control signal of the switch comes from the control circuit, and this control circuit can adjust the gate voltage as needed, thereby switching the switch state of the MOSFET.

[0029] Low-power design: The gate drive current of the MOSFET is very small, so the overall power consumption is low. During operation, the on-resistance of the MOSFET is low, reducing the loss in signal transmission.

[0030] Low distortion and high isolation: By optimizing the design of the MOSFET and selecting appropriate operating points, low distortion of the signal path and high isolation between channels are ensured, avoiding interference between signals.

[0031] Switching speed optimization: By using a suitable drive circuit, the response speed of the switch is optimized, enabling the switch to meet the requirements of high-frequency signal switching.

[0032] In this embodiment, a special control circuit is used to generate the gate voltage signal, and the switch state of the MOSFET is controlled by adjusting the gate voltage. The circuit parameters are adjusted to ensure signal integrity, reduce insertion loss, and improve signal isolation. The performance of the switch is tested under high-frequency signal input to verify its effects of low distortion, low power consumption, and high switching speed.

[0033] Through the above implementation method, higher signal transmission accuracy and lower distortion can be provided, which are suitable for high-demand audio, video, and wireless communication devices. It has low power consumption and is especially suitable for portable or embedded devices. It has a fast response speed and can meet the requirements of high-frequency signal switching. By optimizing the MOSFET operating point, signal interference between channels is reduced, and the stability and reliability of the system are improved.

[0034] Embodiment 2:

[0035] The main switch tube structure adopts a complementary CMOS analog switch. The main switch tube uses a back-to-back structure. By connecting the sources of two MOS transistors, it can withstand bidirectional current. This structure can achieve current conduction in both forward and reverse directions, and at the same time has a lower on-resistance, which greatly improves the symmetry and flatness of the on-resistance and can better reduce signal distortion. At the NMOS switch tube, the ISO terminal and the D terminal are isolated by a source follower, effectively solving the leakage problem of the ISO terminal of the NMOS transistor. The gate and source of the MOS transistor are connected, and the MOS transistor is used as a diode. Since the reverse current is very small when the diode is applied with a reverse voltage, it can just be used as a leakage compensation module. When the switch is turned on, CNP is at a low level. At this time, M3 and M4 are turned on, and the on-leakage compensation module works. When the switch is turned off, CPN is at a high level. At this time, M1 and M2 are turned on, and the off-leakage compensation module works.

[0036] The gate control voltages of the main switch tubes M5, M6, M7, and M8 can follow the input signal voltage, dynamically adjusting the gate voltage of the MOS transistor, further reducing the on-resistance, and at the same time ensuring the device reliability during high-speed signal switching. When the switch is turned on, the S terminal receives the voltage of the input signal and transmits it to GPX. The gate control voltages of the main switch tubes M5 and M6 are transmitted from the source follower and the current mirror module to the drive circuit module, and finally output a stable GPX - 15V signal to GPP through the zener diodes D1 and D2, so that the gate control signal of the switch tube can change dynamically following the input signal.

[0037] The above-mentioned embodiments further elaborate on the purpose, technical solutions, and advantages of the present invention. It should be understood that the above-mentioned embodiments are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made to the present invention within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A dual-channel single-pole double-throw analog switch circuit, characterized in that: include: Two turn-off leakage compensation modules, two ISO isolation circuits, two turn-on leakage compensation modules, eight MOS tubes M5 to M12 and a current source; The connection relationship of each circuit includes: the gate of M5 is connected to the gate of M6, the drain of M5 is respectively connected to the first off leakage compensation module, the first ISO isolation circuit, the first on leakage compensation module and the drain of M7, the substrate of M5 is respectively connected to the substrate of M6, the source of M10 and the positive electrode of the current source, the source of M5 is connected to the source of M6; the drain of M6 is respectively connected to the second off leakage compensation module, the second ISO isolation circuit, the second on leakage compensation module and the drain of M8. The gate of M10 is connected to the CPB signal, and the drain of M10 is connected to the drain of M9; the gate of M9 is connected to the GNN_B signal, and the source of M9 is connected to the VSS signal; the negative electrode of the current source is connected to the source of M11; the gate of M11 is connected to the GNP signal, and the drain of M11 is connected to the VCC signal; the gate of M7 is connected to the gate of M8, and the source of M7 is connected to the source of M8 and the drain of M12 respectively, the gate of M12 is connected to the GNN signal, and the source of M12 is connected to the VSS signal.

2. A dual-channel single-pole double-throw analog switch circuit according to claim 1, characterized in that: The circuit structure of the turn-off leakage compensation module is the same as the circuit structure of the turn-on leakage compensation module.

3. A dual-channel single-pole double-throw analog switch circuit according to claim 2, characterized in that: The shutdown leakage compensation module is composed of two MOS tubes M1 and M13, wherein the drain of M13 is connected to the VSS signal, the gate of M13 is respectively connected to the source of M13 and the source of M1, and the drain of M1 is connected to the drain of M5.

4. The dual-channel single-pole double-throw analog switch circuit according to claim 1, characterized in that: The first ISO isolation circuit is composed of a MOS tube M17 and a resistor R1, wherein one end of the resistor R1 is connected to the VCC signal, the other end of R1 is respectively connected to the ISO signal and the source of M17, the drain of M17 is connected to the VSS signal, and the gate of M17 is connected to the drain of M7.

5. A dual-channel single-pole double-throw analog switch circuit according to claim 4, characterized in that: The structure of the first ISO isolation circuit is the same as that of the second ISO isolation circuit.

6. The dual-channel single-pole double-throw analog switch circuit according to claim 1, characterized in that: The operating voltage of the analog switch circuit is ±15V.

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