Ultrathin multi-layer memory chip stacking and packaging method and system

Through optical scanning and thickness optimization, configuration of intermediate layer materials and stacking path planning, the problems of uneven chip thickness and insufficient positioning accuracy in the prior art are solved, and high-precision chip stacking and packaging are realized, and packaging quality and stability are improved.

CN119742237AActive Publication Date: 2025-04-01DONGGUAN HUAHUI ELECTRONICS SCI & TECH
9 Cites 4 Cited by

Patent Information

Application Number
CN202411822095.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-11
Publication Date
2025-04-01
Estimated Expiration
2044-12-11

AI Technical Summary

Technical Problem

The existing ultra-thin multi-layer memory chip stacking packaging technology has problems such as uneven chip thickness, insufficient positioning accuracy, complex through-hole digging and metal layer deposition processes, and easy defects in welding, resulting in low packaging quality.

Method used

Through optical scanning, chip surface defects and circuit integrity are analyzed, chip quality division and thickness optimization are carried out, intermediate layer materials are configured for coating and curing, identification of identification attributes and intermediate layer positions are identified and stacking path planning is carried out, and high-precision chip stacking and packaging are achieved.

Benefits of technology

The accuracy and quality of chip stacking and packaging are improved, the connection problems caused by thickness differences and positioning deviations are reduced, and the bonding force between chips and the stability of the packaging structure is enhanced.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.
Need to check novelty before this filing date? Find Prior Art