Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving short-circuit tolerance and reducing gate capacity while maintaining a high channel density in a trench MOSFET having a vertical channel fin structure. The present invention is provided with: a plurality of trenches (2) arranged in a second direction and having a long side direction in a first direction and a short side direction in the second direction in plan view; a first source region (3) of the first conductivity type; a second source region (4) of the first conductivity type including a region at least partially having a fin structure demarcated by the plurality of trenches (2); a second conductivity-type channel region (5) having a fin structure, the channel region (5) being partitioned by the plurality of trenches (2); a gate insulating film and a gate electrode disposed inside the trench (2); a JFET region (8) of the first conductivity type; and a body region (9) of a second conductivity type in which a channel current flows in the vertical direction, and in the semiconductor device (1), the depth of the second source region (4) from the surface is shallower than that of the first source region (3).

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] As one type of trench MOSFET, a trench MOSFET having a vertical channel fin structure has been proposed.

[0003] Fig. 9 2 is a perspective view schematically illustrating the structure of a conventional trench MOSFET having a vertical channel fin structure. Fig. 9 In the figure, the gate electrode, the gate insulating film, the interlayer insulating film, the source electrode, and the drain electrode are omitted.

[0004] Fig. 9 The conventional semiconductor device 1 shown has a plurality of trenches 2, which have a long side direction in a first direction and a short side direction in a second direction when viewed from above, and are arranged in plurality in the second direction. Fig. 9 The groove 2 indicated by the dotted line in the cross section just before is a groove shown virtually at a position corresponding to the groove 2 in order to explain the positional relationship between other components and the groove 2 .

[0005] The source region of the first conductivity type is a fin structure which is partially divided by a plurality of trenches 2. Fig. 9 In the description, the undivided portion is referred to as the first source region 3 and the divided portion is referred to as the second source region 4.

[0006] A second conductive type channel region 5 of a fin structure connected to the second source region 4 and divided by a plurality of trenches 2 is formed on the lower surface of the second source region 4. A first conductive type JFET region 8 is formed below the channel region 5, and a second conductive type body region 9 is formed on the side of the JFET region 8. A first conductive type drift region 10 is formed below the JFET region 8, and a first conductive type drain region 11 is formed below the drift region 10.

[0007] and, Fig. 9 The conventional semiconductor device 1 shown has a channel structure in which a gate electrode is buried in the inside of the trench 2 via a gate insulating film formed on the side of the trench 2, and current flows in the depth direction through the side of the trench 2. In addition, the gate electrodes buried in the inside of the trench 2 are connected to each other outside the trench 2.

[0008] According to this structure, the channel density is increased by reducing the trench pitch, thereby reducing the on-resistance.

[0009] In addition, as a patent document related to this technology, there is Patent Document 1, for example. Although the names of the components and the structures of the details are different, in paragraphs 0048 to 0052 of Patent Document 1, Figure 3 14 to 18, which show the same Fig. 9 Similar structure.

[0010] Prior art literature

[0011] Patent Literature

[0012] Patent Document 1: Japanese Patent Application Publication No. 2004-207289 Summary of the invention

[0013] Problems to be solved by the invention

[0014] However, Fig. 9 The conventional semiconductor device 1 shown has the following problems: the channel density is high, and the on-resistance is correspondingly low, so the short-circuit withstand capability is low. In addition, the channel density is high, and the gate capacitance is correspondingly large, resulting in a slow switching speed.

[0015] The problem to be solved by the present invention is to provide a semiconductor device capable of improving short-circuit withstand capability and reducing gate capacitance while maintaining a high channel density in a trench MOSFET having a vertical channel fin structure.

[0016] Solutions to Solve Problems

[0017] In order to solve the above-mentioned problems, the semiconductor device of the present invention, for example, comprises: a plurality of grooves, which have a long side direction in the first direction and a short side direction in the second direction when viewed from above, and a plurality of grooves are arranged in the above-mentioned second direction; a first source region of the first conductivity type, which is arranged on the outside of the above-mentioned groove in the above-mentioned first direction; a second source region of the first conductivity type, which includes at least a portion of a region that becomes a fin structure divided by the above-mentioned plurality of grooves; a channel region of the second conductivity type of the fin structure, which is connected to the lower surface of the above-mentioned second source region and is divided by the above-mentioned plurality of grooves; a gate insulating film, which is arranged inside the above-mentioned groove; a gate electrode, which includes at least a portion of a region arranged inside the above-mentioned groove; a JFET region of the first conductivity type, which is arranged below the above-mentioned channel region; and a main region of the second conductivity type, which is arranged on the side of the above-mentioned JFET region, and the channel current flows in the vertical direction. The above-mentioned semiconductor device is characterized in that the depth of the above-mentioned second source region from the surface is shallower than that of the above-mentioned first source region.

[0018] Effects of the Invention

[0019] According to the semiconductor device of the present invention, even when a short circuit occurs and a high voltage is applied between the source and the drain to flow a saturation current, the second source region is shallower than the first source region and therefore has a higher resistance. The resistance increases at high temperatures and therefore the potential is higher than the first source region. Accordingly, the voltage in the JFET region increases, thereby increasing the reverse bias of the PN junction between the JFET region and the main region and enabling the JFET region to be further depleted. Therefore, compared with the case where the depth of the second source region is the same as that of the first source region, the saturation current can be reduced and the short-circuit tolerance is improved.

[0020] In addition, since the second source region is shallow, the overlap capacity between the gate electrode extending in the depth direction of the trench and the second source region is reduced, and the gate capacity can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a perspective view of the semiconductor device of Example 1.

[0022] Figure 2 The semiconductor device of Example 1 Figure 1 X1-X1' section view.

[0023] Figure 3 The semiconductor device of Example 1 Figure 1 X2-X2' section view.

[0024] Figure 4 The semiconductor device of Example 1 Figure 1 Y1-Y1' section view.

[0025] Figure 5 The semiconductor device of Example 2 is Figure 2 Corresponding X1-X1' section view.

[0026] Figure 6 The semiconductor device of Example 3 is Figure 2 Corresponding X1-X1' section view.

[0027] Figure 7 The semiconductor device of Example 3 is relative to Figure 6 Impurity concentration distribution diagram of the depth in the Z1-Z1' direction.

[0028] Figure 8 The semiconductor device of the fourth embodiment is Figure 2 Corresponding X1-X1' section view.

[0029] Fig. 9 This is a perspective view schematically illustrating the structure of a conventional trench MOSFET having a vertical channel fin structure. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0031] Example 1

[0032] Figure 1 is a perspective view of the semiconductor device of Example 1, Figure 2 The semiconductor device of Example 1 Figure 1 The X1-X1' section view, Figure 3 The semiconductor device of Example 1 Figure 1 The X2-X2' section view, Figure 4 The semiconductor device of Example 1 Figure 1 In addition, Figure 1 In the figure, the gate electrode 7, the gate insulating film 6, the interlayer insulating film 14, the source electrode 12, and the drain electrode 13 are omitted.

[0033] like Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a plurality of trenches 2 , which have a long side direction in a first direction and a short side direction in a second direction in a plan view, and are arranged in plurality in the second direction.

[0034] Furthermore, the semiconductor device 1 has: a first conductivity type (in Figure 2 a first source region 3 of the first conductivity type (of n type in the first direction), which is arranged outside the trench 2; a second source region 4 of the first conductivity type, which includes at least a portion of a region of a fin structure divided by a plurality of trenches 2; and a second conductivity type (of n type in the first direction) of the fin structure. Figure 2 A channel region 5 (of p-type in the embodiment) is connected to the lower surface of the second source region 4 and is divided by a plurality of trenches 2.

[0035] In addition, in the first embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited thereto. The first conductivity type may be p-type and the second conductivity type may be n-type. Figure 1 and Figure 2 The groove 2 indicated by the dotted line in the cross section of FIG. 1 is a groove that is virtually shown at a position corresponding to the groove 2 in order to explain the positional relationship between other components and the groove 2 .

[0036] The semiconductor device 1 of the first embodiment and Fig. 9 The existing structures are different in the following aspects: Figure 2As shown, the impurity concentration of the second source region 4 is lower than that of the first source region 3, and the depth from the surface is shallower than that of the first source region 3. In Example 1, as an example, the first source region 3 is illustrated as a high-concentration n+ type, the second source region 4 is illustrated as an n-type with a lower concentration than the first source region 3, and the channel region 5 is illustrated as a p-type, but it is not limited to this as long as the desired action in Example 1 can be achieved.

[0037] In the first embodiment, a part of the second source region 4 has a fin structure, and the other part is shown as an example of a structure connected to the first source region 3 , but the present invention is not limited thereto, and the entire second source region 4 may have a fin structure.

[0038] In addition, if Figure 3 as well as Figure 4 As shown, the semiconductor device 1 includes: a gate insulating film 6 disposed inside the trench 2; and a gate electrode 7 including a region at least partially disposed inside the trench 2. Figure 4 As shown, the gate electrodes 7 arranged inside the trench 2 are connected to each other outside the trench 2. An interlayer insulating film 14 is formed between the interconnected portions of the gate electrodes 7 and the second source region 4. The interlayer insulating film 14 is also formed in a manner covering the upper portion and the side portion of the interconnected portions of the gate electrodes 7. The gate electrode 7 can be formed of, for example, polycrystalline silicon.

[0039] And, if Figure 2 As shown, the semiconductor device 1 has: a first conductive type JFET region 8, which is arranged below the channel region 5; a second conductive type body region 9, which is arranged on the side of the JFET region 8; a first conductive type drift region 10, which is arranged below the JFET region 8; a first conductive type drain region 11, which is arranged below the drift region 10; a source electrode 12, which is connected to the upper surface side of the first source region 3; and a drain electrode 13, which is connected to the lower surface side of the drain region 11. The channel region 5 is electrically connected to the body region 9. The JFET region 8 is electrically connected to the drift region 10. As shown Figure 2 As shown, the trench 2 is formed so that the length in the longitudinal direction overlaps the body region 9 on both sides of the JFET region 8. The depth of the trench 2 is shallower than the body region 9 and deeper than the channel region 5.

[0040] In the first embodiment, as an example, the JFET region 8 is shown as an n-type, the body region 9 is a p-type, the drift region 10 is a low-concentration n-type, and the drain region 11 is a high-concentration n+ type, but it is not limited to this as long as the desired operation in the first embodiment can be achieved. For example, the JFET region 8 can also be a low-concentration n-type.

[0041] The semiconductor device 1 of the first embodiment controls the gate electrode 7 in the trench 2 by inputting a gate drive signal, so that the channel current flows in the vertical direction to the channel region 5 of the fin structure. That is, a trench MOSFET of a vertical channel fin structure is formed. Therefore, by reducing the trench pitch to increase the density of the trench 2, the channel density can be increased, the channel resistance can be reduced, and the on-resistance can be reduced.

[0042] According to the semiconductor device 1 of the first embodiment, even when a short circuit occurs and a high voltage is applied between the source and the drain and a saturation current flows, the JFET region 8 is depleted due to the deep body region 9 during a short circuit, and the saturation current can be reduced by pinching off the current path by which the depletion layer extends from the right and left to connect and disappear. In addition, the second source region 4 is shallower than the first source region 3, and therefore has a high resistance. When a high temperature is increased as in the case of a short circuit, the potential is higher than the first source region 3, and accordingly, the voltage of the JFET region 8 increases, thereby strengthening the reverse bias of the PN junction between the JFET region 8 and the body region 9, and can further deplete the JFET region 8, so that Fig. 9 Such a second source region 4 having the same depth as the first source region 3 can reduce the saturation current and improve the short-circuit withstand capability.

[0043] In addition, as in Example 1, it is preferred that the impurity concentration of the second source region 4 is lower than the impurity concentration of the first source region 3. This can further increase the resistance, thereby achieving a greater effect. However, this is not limited to this, and the impurity concentration of the second source region 4 can also be the same as the impurity concentration of the first source region 3.

[0044] In addition, since the second source region 4 is shallow, the overlap capacitance between the gate electrode 7 extending in the depth direction of the trench 2 and the second source region 4 is reduced, and the gate capacitance can be reduced. As a result, the switching speed can also be increased.

[0045] Therefore, generally, in a trench MOSFET with a longitudinal channel fin structure, there is a trade-off relationship in which if the channel density is high, the on-resistance is low, the short-circuit tolerance is low, the gate capacity is large, and the switching speed is slow. However, according to the semiconductor device 1 of Example 1, the short-circuit tolerance can be improved and the gate capacity can be reduced while maintaining a high channel density, and the switching speed can also be increased.

[0046] Therefore, in order to fully obtain the effect of improving the short-circuit withstand capability, the sheet resistance of the second source region 4 is preferably 10 times or more of the sheet resistance of the first source region 3 .

[0047] The semiconductor device 1 of the first embodiment can be formed, for example, from an n+ type SiC substrate, but is not limited thereto. In addition, it can be manufactured by a general semiconductor device manufacturing method such as forming an n+ type drain region 11 from an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth, so detailed description is omitted.

[0048] Example 2

[0049] Figure 5 The semiconductor device of Example 2 is Figure 2 Corresponding X1-X1' section view.

[0050] Embodiment 2 is a variation of Embodiment 1, and Embodiment 2 differs from Embodiment 1 in that the connection structure between the second source region 4 and the first source region 3 is different. The rest is basically the same as Embodiment 1, so the description will be centered on the differences and repeated description will be omitted.

[0051] like Figure 5 As shown, in the semiconductor device 1 of the second embodiment, only one end of the second source region 4 is connected to the first source region 3. Figure 5 , an example is shown in which the left end of the second source region 4 is connected to the first source region 3, but the opposite may be true. In addition, the end to be connected may be changed according to the location, and there are two structures, one connecting the left end of the second source region 4 and the other connecting the right end of the second source region 4.

[0052] Thus, by extracting the connection, a larger resistance can be applied, so the short-circuit tolerance is further improved.

[0053] In addition, the extraction frequency can be adjusted within the chip surface. For example, the extraction frequency can be increased in a location that is prone to high temperature during a short circuit, thereby reducing the amount of heat generated.

[0054] In this case, the second source region 4 may be of the following two types: Figure 2 The first connection structure in which both ends of the second source region 4 are connected to the first source region 3; and Figure 5 In this way, a second connection structure is formed in which only one end portion of the second source region 4 is connected to the first source region 3 .

[0055] Example 3

[0056] Figure 6 The semiconductor device of Example 3 is Figure 2 Corresponding X1-X1' section view.

[0057] Embodiment 3 is a modified example of Embodiment 1. Embodiment 3 is different from Embodiment 1 in that it has a push-back area 15. Other than that, it is basically the same as Embodiment 1, so the description will be centered on the different aspects and repeated descriptions will be omitted. In addition, Embodiment 3 can also be applied to Embodiment 2.

[0058] The semiconductor device 1 of the third embodiment includes a push-back region 15 of the first conductivity type having an impurity concentration higher than that of the JFET region 8 between the channel region 5 and the JFET region 8. Figure 6 In the figure, the push-back region 15 is illustrated as an n-type, but it is not limited to this as long as the desired action in Example 3 can be achieved.

[0059] Figure 7 The semiconductor device of Example 3 is relative to Figure 6 The vertical axis represents the impurity concentration IC and the horizontal axis represents the depth DP.

[0060] When the channel region 5 is formed by ion implantation, for example, the distribution pattern of aluminum as a p-type dopant tends to be pulled downward, and the channel region 5 becomes deeper than necessary. Accordingly, the trench 2 also needs to be deepened, the gate capacitance increases, and the length of the effective JFET region 8 becomes shorter, so the short-circuit resistance decreases.

[0061] Therefore, by using nitrogen as the ion species of the push-back region 15, for example, and arranging the push-back region 15 of the first conductivity type having a higher impurity concentration than the JFET region 8 between the channel region 5 and the JFET region 8, the channel region depth d1 in the case without the push-back region can be reduced to the channel region depth d2 in the case with the push-back region, and the low-concentration region (the region of the lower hem) of the channel region 5 can be reduced, so that the depth of the channel region 5 can be shallowed while maintaining the necessary charge amount. As a result, the gate capacitance can be reduced, and the dimension of the JFET region 8 in the depth direction can also be increased, so the short-circuit tolerance is also improved.

[0062] Example 4

[0063] Figure 8 The semiconductor device of the fourth embodiment is Figure 2 Corresponding X1-X1' section view.

[0064] Embodiment 4 is a modified example of Embodiment 1, and the difference between Embodiment 4 and Embodiment 1 is that it has a 3C-SiC region 16. Other than that, it is basically the same as Embodiment 1, so the description will be centered on the different aspects, and repeated descriptions will be omitted. In addition, Embodiment 4 can also be applied to Embodiment 2 or Embodiment 3.

[0065] In the semiconductor device 1 of the fourth embodiment, the first source region 3 includes the 3C—SiC region 16 provided on the outermost surface of the 4H—SiC region.

[0066] Typically, the SiC used in power devices is a polycrystalline type called 4H-SiC, which has a wide band gap and is suitable for high withstand voltage, but it is difficult to obtain ohmic contact, and generally requires heat treatment above 900°C. In contrast, 3C-SiC can obtain ohmic contact at low temperatures because of its small band gap. In order to make the surface of 4H-SiC 3C-SiC, it can be achieved by injecting high-mass ions such as phosphorus at a high dose to cause it to recrystallize. Here, if the high-dose injection layer of phosphorus is near the channel region 5, the channel characteristics will be deteriorated. On the other hand, in this embodiment, there is a second source region 4 near the channel region 5, and the first source region 3 is not in contact with the channel region 5, so a low-temperature ohmic contact using 3C-SiC can be applied. If a low-temperature ohmic contact is applied, the degradation of the oxide film in the high-temperature process can be avoided, so the reliability of the oxide film is also improved, and the short-circuit tolerance is also improved.

[0067] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, some or all of the structures described in the embodiments can also be combined for application.

[0068] Explanation of symbols

[0069] 1—semiconductor device, 2—trench, 3—first source region, 4—second source region, 5—channel region, 6—gate insulating film, 7—gate electrode, 8—JFET region, 9—body region, 10—drift region, 11—drain region, 12—source electrode, 13—drain electrode, 14—interlayer insulating film, 15—push-back region, 16—3C-SiC region, IC—impurity concentration, DP—depth, d1—channel region depth without push-back region, d2—channel region depth with push-back region.

Claims

1. A semiconductor device comprising: A plurality of grooves, which have a long side direction in a first direction and a short side direction in a second direction when viewed from above, and are arranged in plurality in the second direction; A first source region of a first conductivity type, which is arranged outside the trench in the first direction; A second source region of the first conductivity type, including a region at least part of which is a fin structure divided by the plurality of trenches; A second conductive type channel region of the fin structure, which is connected to the lower surface of the second source region and is divided by the plurality of grooves; A gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed inside the trench; A JFET region of the first conductivity type, which is arranged below the channel region; as well as a second conductive type body region disposed on the side of the JFET region, The channel current flows in the longitudinal direction. The semiconductor device is characterized in that The second source region is shallower than the first source region in depth from the surface.

2. The semiconductor device according to claim 1, wherein: The second source region has an impurity concentration lower than that of the first source region.

3. The semiconductor device according to claim 1, wherein: have: A drift region of the first conductivity type, which is disposed below the JFET region; and The drain region of the first conductivity type is arranged below the drift region.

4. The semiconductor device according to claim 1, wherein: The gate electrodes disposed inside the trench are connected to each other outside the trench.

5. The semiconductor device according to claim 1, wherein: The sheet resistance of the second source region is at least 10 times the sheet resistance of the first source region.

6. The semiconductor device according to claim 1, wherein: In the second source region, only one end portion of the second source region is connected to the first source region.

7. The semiconductor device according to claim 1, wherein: The second source region has two types: a first connection structure in which both ends of the second source region are connected to the first source region; and a second connection structure in which only one end of the second source region is connected to the first source region.

8. The semiconductor device according to claim 1, wherein: A push-back region of the first conductivity type having an impurity concentration higher than that of the JFET region is provided between the channel region and the JFET region.

9. The semiconductor device according to claim 1, wherein: The first source region includes a 3C-SiC region provided on the outermost surface of the 4H-SiC region.

10. The semiconductor device according to claim 1, wherein: The first conductivity type is n-type, and the second conductivity type is p-type.

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