A silicon carbide trench gate MOSFET device and its preparation method

Abstract

The present invention discloses a silicon carbide trench gate MOSFET device and a method for preparing the same. The device is composed of two alternating cell structures, wherein structure one is a conventional silicon carbide trench gate MOSFET structure with a P-type shielding layer below the gate, while structure two utilizes selective tilted ion implantation to form a P-type connection region below the gate trench side that connects the P-type base region on the side of the gate and the P-type shielding layer below the gate, thereby achieving effective grounding of the P-type shielding layer and improving the shielding effect of the P-type shielding layer. Furthermore, an additional N-type connection region for connecting the channel is added inside the P-type connection region, so that electrons in the source region can flow to the JFET region through the N-type connection region along the alternating arrangement direction of the two structures after passing through the base region channel, thereby increasing the effective channel density and reducing the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of power devices, and in particular to a trench gate silicon carbide power MOSFET device with a P-type shielding layer. Background Art

[0002] Power MOSFET devices are commonly used to control the on / off switching of loads and can also be used as controlled rectifiers to achieve AC / DC conversion. They are one of the most commonly used devices in power circuits. Compared to silicon, silicon carbide has advantages such as high critical breakdown electric field, high thermal conductivity, and high saturation electron drift velocity, making it more suitable for high voltage and high current semiconductor devices. In the field of power electronics, silicon carbide power MOSFETs have been widely used and have high power switching performance. However, a major challenge of silicon carbide MOSFETs is the low electron mobility in the channel, which leads to a large channel resistance, which becomes an important component of the overall specific on-resistance. Silicon carbide power MOSFETs mainly have two structures: planar gate and trench gate. Compared with traditional planar gate MOSFETs, the channel of trench gate MOSFETs is in the vertical direction, which can utilize higher mobility, eliminate the width of the JFET region, make the cell more compact, and increase the channel density, thereby reducing the on-resistance of the device [1].

[0003] However, the main problem with silicon carbide trench gate MOSFETs is the high gate oxide electric field during device withstand voltage, which seriously damages the device's reliability. In addition, the device's reverse transfer capacitance is large, resulting in slow device switching speed and high switching loss. To solve these two problems, J. Tan et al. from Purdue University in the United States proposed in 1998 to form a P-type shielding layer by injecting it under the trench gate to shield the gate oxide electric field [2]. Subsequent studies have shown that the charge storage effect of the floating P-type shielding layer will damage the dynamic performance of the device, so the P-type shielding layer needs to be grounded [3]. In traditional methods, the grounding of the P-type shielding layer is achieved by forming contact holes around the device cells. However, this method sacrifices the number of effective cells, and the distance from the contact hole to the P-type shielding layer is long, resulting in a large contact resistance and limited improvement in device performance [4].

[0004] References:

[0005] Agarwal AK, Casady JB, Rowland LB, et al.1.1kv 4h-sic power umosfets[J]. IEEE Electron Device Letters, 1997, 18(12): 586-588.

[0006] Tan J, Cooper JA, Melloch M R. High-voltage accumulation-layer UMOSFET's in4H-SiC[J]. IEEE Electron Device Letters, 1998, 19(12): 487-489.

[0007] Wei J, Zhang M, Jiang H, et al.Dynamic Degradation in SiC Trench MOSFETWith a Floating p-Shield Revealed With Numerical Simulations[J].IEEETransactions on Electron Devices,2017:1-7.

[0008] Tanaka R,Kagawa Y,Fujiwara N,et al.Impact of grounding the bottomoxide protection layer on the short-circuit ruggedness of 4H-SiC trenchMOSFETs[C] / / IEEE International Symposium on Power Semiconductor Devices&Ics.IEEE, 2014. Summary of the Invention

[0009] The purpose of the present invention is to provide a trench gate silicon carbide power MOSFET device with a P-type shielding layer to solve the problem of grounding design of the P-type shielding layer.

[0010] The silicon carbide MOSFET device proposed in the present invention is composed of two cell structures arranged alternately. Structure 1 is similar to the traditional silicon carbide trench gate MOSFET structure with a P-type shielding layer under the gate. Structure 2 utilizes selective tilted ion implantation to form a P-type connection area below the gate trench side that connects the P-type base region on the gate side and the P-type shielding layer under the gate to achieve grounding of the P-type shielding layer.

[0011] The silicon carbide trench gate MOSFET device proposed in the present invention may be specifically implemented in one of the following ways:

[0012] First, referring to Example 1 of the present invention, the silicon carbide trench gate MOSFET device is composed of two cellular structures arranged alternately, both structures include an N-type heavily doped silicon carbide substrate, and an N-type lightly doped drift region and an N-type doped JFET region epitaxially grown in sequence on the substrate, the gate is located in a gate trench formed after etching in the middle of the JFET region, the gate is surrounded by a gate dielectric layer, and the gate is under a P-type shielding layer; above the JFET region, on both sides of the gate are P-type base regions; the drain is located on the back side of the substrate; it is characterized in that structure one of the two structures has an N-type heavily doped source region above the P-type base region, and the source is located above the gate dielectric layer and the N-type heavily doped source region; while structure two has a P-type connection region connecting the P-type base region and the P-type shielding layer below the gate trench side, and the source is located above the gate dielectric layer and the P-type base region.

[0013] Secondly, referring to the second embodiment of the present invention, the silicon carbide trench gate MOSFET device is composed of two cell structures arranged alternately, both structures include an N-type heavily doped silicon carbide substrate, and an N-type lightly doped drift region and an N-type doped JFET region epitaxially grown on the substrate in sequence, the gate is located in the gate trench formed after etching in the middle of the JFET region, the gate is surrounded by a gate dielectric layer, and the gate is under the P-type shielding layer; above the JFET region and on both sides of the gate are P-type base regions; an N-type heavily doped source region is provided above the inner side of the P-type base region and adjacent to the gate dielectric layer; the source is located above the gate dielectric layer, the N-type heavily doped source region and the P-type base region; the drain is located on the back side of the substrate; it is characterized in that, compared with structure one, structure two further includes: an N-type connection region connected to the P-type base channel is provided on the side wall of the lower part of the gate trench, and a P-type connection region connected to the P-type base region and the P-type shielding layer is provided on the lower side of the N-type connection region.

[0014] As can be seen from the above, compared with the first solution, the source of Structure 1 of the second solution is located above the gate dielectric layer, the N-type heavily doped source region and the P-type base region, and Structure 2 also has an N-type heavily doped source region above the inner side of the P-type base region and adjacent to the gate dielectric layer, and on the inner side of the P-type connection region, the side wall of the lower part of the gate trench has an N-type connection region connected to the P-type base region channel.

[0015] In the silicon carbide power MOSFET device of the present invention, the N-type heavily doped silicon carbide substrate generally adopts an off-axis angle of 4 degrees, a thickness of 20 to 2000 μm, and a doping concentration of 1×10 17 ~2×10 20 cm -3 .

[0016] Preferably, the thickness of the N-type lightly doped drift region epitaxially grown on the substrate is 5 to 100 μm, and the doping concentration is 1×10 15 ~2×10 17 cm -3The thickness of the N-type doped JFET region is 2 to 6 μm, and the doping concentration is 5×10 15 ~5×10 17 cm -3 .

[0017] Preferably, the depth of the trench gate in the structure is 0.4-4.0 μm; the thickness of the P-type shielding layer is 0.2-0.8 μm, and the doping concentration is 5×10 16 ~5×10 19 cm -3 The thickness of the P-type base region is 0.3 to 0.8 μm, and the doping concentration is 5×10 16 ~5×10 18 cm -3 The thickness of the N-type heavily doped source region is 0.1 to 0.4 μm, and the doping concentration is 1×10 19 ~1×10 20 cm -3 The doping concentration of the P-type connection region and the N-type connection region is 1×10 16 ~5×10 18 cm -3 The width along the alternating arrangement direction is 0.6 to 2 μm, and the distance between adjacent connection areas is 2 to 6 μm.

[0018] The present invention proposes a method for preparing the above-mentioned silicon carbide trench gate MOSFET device. Taking the first implementation scheme as an example, the method specifically includes the following steps:

[0019] Step 1: On an N-type heavily doped silicon carbide substrate, epitaxially grow an N-type lightly doped drift region, an N-type JFET region, and a P-type base region in sequence, and form an N-type heavily doped source region by epitaxy or ion implantation;

[0020] Step 2: Arranging an etching mask on the N-type heavily doped source region, etching to form a silicon carbide trench, and forming a P-type shielding layer under the trench by self-aligned ion implantation;

[0021] Step 3: growing silicon dioxide on the inner surface of the trench by thermal oxidation to obtain a gate dielectric layer, and depositing heavily doped polysilicon to form a gate;

[0022] Step 4: Arrange an ion implantation mask and form a P-type connection region connecting the P-type base region and the P-type shielding layer on both sides of the gate by selective tilted ion implantation;

[0023] Step 5: Deposit a silicon dioxide layer on the upper surface of the device, and form a gate top dielectric layer by photolithography and etching; finally, prepare source and drain contact electrodes on the upper and lower surfaces of the device, respectively.

[0024] The preparation process of the second implementation is similar to that of the first implementation, and only an ion implantation process of the N-type connection region needs to be added in step 4.

[0025] Furthermore, variations in parameters such as the length, thickness, and doping concentration of each region are within the scope of the present invention and depend on different design requirements and fabrication processes. The present invention focuses on the P-type connection region formed by selective tilted ion implantation, through which the P-type shielding layer is connected to the P-type base region for grounding. It is understood that other process sequences and combinations may be used to ultimately achieve the same device structure without departing from the scope of the present invention.

[0026] Beneficial effects of the present invention:

[0027] The existing technology realizes the grounding of the P-type shielding layer in the silicon carbide trench gate MOSFET by forming contact holes of the P-type shielding layer around the device cells. However, this method sacrifices the number of effective cells, and the contact resistance of the P-type shielding layer is large, and the improvement of device performance is limited. To this end, the present invention proposes a device structure with a P-type connection region and a preparation method thereof. One solution is to form a P-type connection region connecting the P-type base region and the P-type shielding layer on both sides of the gate trench by selective tilted ion implantation, which effectively realizes the grounding of the P-type shielding layer and makes the P-type shielding layer have better shielding effect. Another solution is to add an N-type connection region for connecting the channel to the inner side of the P-type connection region, so that the electrons in the source region can flow to the JFET region through the N-type connection region along the alternating arrangement direction of the two structures after passing through the base channel. Compared with the first solution, the effective channel density is increased and the on-resistance of the device can be reduced.

[0028] The following table can intuitively see the beneficial effects of the present invention (refer to the literature in the background technology):

[0029] Technical Solution Shielding effect of P-type shielding layer P-type shielding layer facilitates good grounding Channel density Reference 1 (T-MOS) none no high Reference 2 (P-MOS) generally no generally Embodiment 1 of the present invention good yes Higher Embodiment 2 of the present invention good yes high BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 1 is a top view of the silicon carbide MOSFET device involved in the first embodiment of the present invention.

[0031] Figure 2 yes Figure 1 Top view of the silicon carbide MOSFET device and cross-sectional view of the device cell along the AA' direction.

[0032] Figure 3 yes Figure 1 Top view of the silicon carbide MOSFET device and cross-sectional view of the device cell along the BB' direction.

[0033] Figure 4 It is a top view of the silicon carbide MOSFET device involved in the second embodiment of the present invention.

[0034] Figure 5 yes Figure 4 Top view of the silicon carbide MOSFET device and cross-sectional view of the device cell along the AA' direction.

[0035] Figure 6 yes Figure 4 Top view of the silicon carbide MOSFET device and cross-sectional view of the device cell along the BB' direction.

[0036] Figure 7 This is a top view of the structure completed in step 1 of Example 1.

[0037] Figure 8 It is a top view of the structure completed in step 2 of embodiment 1.

[0038] Figure 9 It is a top view of the structure completed in step 4 of embodiment 1.

[0039] Figure 10 This is a top view of the structure completed in step 1 of Example 2.

[0040] Figure 11 It is a top view of the structure completed in step 2 of embodiment 2.

[0041] Figure 12 It is a top view of the structure completed in step 4 of embodiment 2.

[0042] In the figure: 1-source, 2-gate dielectric layer, 3-gate, 4-P-type shielding layer, 41-P-type connection region, 42-N-type connection region, 5-source region, 6-P-type base region, 7-JEFT region, 8-drift region, 9-substrate, 10-drain. DETAILED DESCRIPTION

[0043] The device structure and preparation process of the present invention are described below by way of examples in conjunction with the accompanying drawings.

[0044] Example 1

[0045] Figure 1 is a top view of the silicon carbide MOSFET device involved in this embodiment, Figure 2 and Figure 3 They are cross-sectional views of the device cell along the AA' and BB' directions respectively. Figure 1The silicon carbide MOSFET device shown is composed of two cell structures arranged alternately. Both structures include an N-type heavily doped silicon carbide substrate 9, an N-type lightly doped drift region 8 and an N-type doped JFET region 7 epitaxially grown on the substrate 9. The gate 3 is located in the gate trench formed by etching in the middle of the JFET region 7. The gate 3 is surrounded by a gate dielectric layer 2, and below the gate 3 is a P-type shielding layer 4. Above the JFET region 7, on both sides of the gate 3 are P-type base regions 6. The source 1 is located on the top layer, and the drain 10 is located on the back of the substrate 9. The difference is that Figure 2 The structure shown has an N-type heavily doped source region 5 above the P-type base region 6, and the source 1 is located above the gate dielectric layer 2 and the N-type heavily doped source region 5; Figure 3 The structure shown has a P-type connection region 41 connecting the P-type base region 6 and the P-type shielding layer 4 below the gate trench side, and the source 1 is located above the gate dielectric layer 2 and the P-type base region 6 .

[0046] The steps for preparing the device of Example 1 are as follows:

[0047] Step 1: At a phosphorus ion doping concentration of 6×10 19 cm -3 On a silicon carbide substrate 9 with a thickness of 300 μm and a 4-degree off-angle, after a standard cleaning process, a phosphorus ion doping concentration of 8×10 15 cm -3 , a silicon carbide drift region 8 with a thickness of 10 μm; a phosphorus ion doping concentration of 3.5×10 16 cm -3 , a silicon carbide N-type doped region with a thickness of 2.5 to 4 μm is used as the JFET region 7. A doping concentration of 2×10 17 cm -3 , a P-type doped region with a depth of 0.6 μm from the surface of the JFET region is used as the P-type base region 6. Subsequently, selective nitrogen ion implantation is performed to form a doping concentration of 2×10 19 cm -3 , ion implantation depth of 0.2μm source region 5, obtained Figure 7 The structure shown in FIG. 1 shows a structure in which the width of the source region 5 along the CC' direction is 5 μm, and the distance between adjacent source regions 5 is 1 μm.

[0048] Step 2: Deposit silicon dioxide on the surface as an etching mask, first selectively etch away the silicon dioxide layer on the upper part of the trench area to form an etching window for silicon carbide, and then etch a trench in the source area 5 using the ICP process. The trench is 1.2 μm deep and 0.8 μm wide. Subsequently, aluminum ion implantation is performed using a self-aligned process to form a doping concentration of 5×10 18 cm -3, a P-type shielding layer 4 with a thickness of 0.5 μm, such as Figure 8 shown.

[0049] Step 3: Perform sacrificial oxidation on the etched trench, then remove the sacrificial oxide layer, grow a 50nm thick silicon dioxide layer on the inner surface of the trench by thermal oxidation, and then anneal in a nitrogen monoxide atmosphere to obtain a gate dielectric layer 2; use chemical vapor deposition to deposit P-type heavily doped polysilicon, and then obtain the gate 3 through steps such as photolithography and etching.

[0050] Step 4: Deposit silicon dioxide on the surface as an etching mask, first selectively etch away the silicon dioxide on the source region 5 and part of the base region 6, and then form a P-type connection region 41 connecting the base region 6 and the P-type shielding layer 4 in the region with a depth of 0.6μm to 1.7μm on both sides of the gate 3 by aluminum ion implantation at a certain angle, as shown in FIG. Figure 9 As shown. The doping concentration of the P-type connection region 41 is 5×10 17 cm -3

[0051] Step 5: Deposit a silicon dioxide layer on the device surface, and then through steps such as photolithography and etching, retain only the gate dielectric layer 2 on the top of the gate 3; then deposit metal aluminum on the device surface, perform a rapid thermal annealing process, form an ohmic contact, and obtain a source electrode 1; deposit metal titanium on the lower surface of the substrate 9 and form an ohmic contact to obtain a drain electrode 10, and obtain the following: Figure 1 The silicon carbide power MOSFET device shown.

[0052] Example 2

[0053] Figure 4 is a top view of the silicon carbide MOSFET device involved in this embodiment, Figure 5 and Figure 6 Compared with the first embodiment, the selective doping region of the source region 5 of the second embodiment is slightly different, and an N-type connection region 42 connected to the channel is additionally added.

[0054] The preparation process of Example 2 is similar to that of Example 1, except that an ion implantation process of the N-type connection region is added in step 4. By means of inclined phosphorus ion implantation, a doping concentration of 2×10 17 cm -3 , used to connect the N-type connection area 42 of the channel. Example 2 The top views after the above steps 1, 2 and 4 are respectively as shown in FIG. Figure 10 、 Figure 11 and Figure 12 shown.

[0055] The specific embodiments described above provide a detailed description of the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A silicon carbide trench gate MOSFET device, comprising two alternating cell structures, wherein structure one is a conventional silicon carbide trench gate MOSFET structure with a P-type shield layer below the gate, and structure two has a P-type connection region formed below the gate trench side by selective tilted ion implantation. The P-type connection region connects the P-type shield layer below the gate to the P-type base region located on the side of the gate to achieve grounding of the P-type shield layer; characterized in that: The two alternating cell structures both include an N-type heavily doped silicon carbide substrate, an N-type lightly doped drift region, and an N-type doped JFET region, which are epitaxially grown on the substrate. The gate is located in a gate trench formed by etching in the middle of the JFET region. The gate is surrounded by a gate dielectric layer, and below the gate is a P-type shielding layer. Above the JFET region, on both sides of the gate, is a P-type base region. An N-type heavily doped source region is provided above the inner side of the P-type base region and adjacent to the gate dielectric layer; The source is located on the gate dielectric layer, the N-type heavily doped source region and the P-type base region; the drain is located on the back side of the substrate; Compared with structure 1, structure 2 further includes: an N-type connection region connected to the P-type base channel on the sidewall at the bottom of the gate trench, and a P-type connection region connected to the P-type base and the P-type shielding layer below the N-type connection region.

2. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The N-type heavily doped silicon carbide substrate has an off-axis angle of 4 degrees, a thickness of 20 to 2000 μm, and a doping concentration of 1×10 17 ~2×10 20 cm -3 .

3. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The thickness of the N-type lightly doped drift region is 5 to 100 μm, and the doping concentration is 1×10 15 ~2×10 17 cm -3 The thickness of the N-type doped JEFT region is 2 to 6 μm, and the doping concentration is 5×10 15 ~5×10 17 cm -3 .

4. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The depth of the trench gate is 0.4 to 4.0 μm; the thickness of the P-type shielding layer below the gate is 0.2 to 0.8 μm, and the doping concentration is 5×10 16 ~5×10 19 cm -3 The thickness of the P-type base region on the side of the gate is 0.3 to 0.8 μm, and the doping concentration is 5×10 16 ~5×10 18 cm -3 ; The doping concentration of the P-type connection region connecting the P-type base region and the P-type shielding layer is 1×10 16 ~5×10 18 cm -3 .

5. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The thickness of the N-type heavily doped source region is 0.1 to 0.4 μm, and the doping concentration is 1×10 19 ~1×10 20 cm -3 .

6. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The doping concentration of the N-type connection region is 1×10 16 ~5×10 18 cm -3 .

7. The silicon carbide trench gate MOSFET device according to claim 1, wherein: The width of the P-type connection region and the N-type connection region along the alternating arrangement direction is 0.6-2 μm, and the distance between adjacent connection regions is 2-6 μm.

8. The method for preparing the silicon carbide trench gate MOSFET device according to claim 1, comprising the following steps: b1) epitaxially growing an N-type lightly doped drift region, an N-type JFET region, and a P-type base region on an N-type heavily doped silicon carbide substrate, and forming an N-type heavily doped source region by epitaxy or ion implantation; b2) disposing an etching mask on the N-type heavily doped source region, etching to form a silicon carbide trench, and forming a P-type shielding layer below the trench by self-aligned ion implantation; b3) growing silicon dioxide on the inner surface of the trench by thermal oxidation to obtain a gate dielectric layer, and depositing heavily doped polysilicon to form a gate; b4) Arranging ion implantation masks and forming N-type connection regions connected to the P-type base channel and P-type connection regions connected to the P-type base and the P-type shielding layer on both sides of the gate through selective tilted ion implantation; b5) Deposit a silicon dioxide layer on the top surface of the device and form a gate top dielectric layer through photolithography and etching; finally, prepare source and drain contact electrodes on the upper and lower surfaces of the device, respectively.

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