A simulation method and system of power electronic converter based on binary resistance model

Abstract

The application belongs to the technical field of simulation modeling, and discloses a power electronic converter simulation method and system based on a binary resistance model. c (k), then in stage 2, the predicted half-bridge natural switching state combination and the flag signal flag(k) and the real half-bridge natural switching state combination sigma hd (k) are sequentially updated. Finally, in stage 3, the combination of vectors flag(k), sigma hd (k) and the state vector x(k) is completed. The above method can accurately identify the state combination switching time of the natural switching half-bridge, and only needs to update the half-bridge natural switching state combination through simple logical operation, and only needs to calculate the state equation once in the whole calculation process, so that the modeling calculation amount is extremely low.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of simulation modeling, and more particularly to a power electronic converter simulation method based on a binary resistance model and a system thereof. BACKGROUND

[0002] With the wide application of wide-bandgap semiconductors, power electronic converters gradually develop towards high switching frequency, and therefore, research on real-time simulation technology applicable to high switching frequency is a research hotspot in the field of real-time simulation.

[0003] A power electronic converter has a series of half-bridge structures, each of which includes an upper switch tube and a lower switch tube, and is the most commonly used switching network unit of a high-frequency power electronic converter. The binary resistance switching model is one of the most commonly used switching models in the field of real-time simulation modeling. When the switch is turned on, the switch is equivalent to a small on-resistance R on to simulate a short-circuit state; and when the switch is turned off, the switch is equivalent to a large off-resistance R off to simulate an open-circuit state. Therefore, the binary resistance switching model is also called the R on / R off switching model. Existing documents indicate that the power electronic converter model established by using the R on / R off switching model has higher precision than the power electronic converter model established by using other switching models.

[0004] Under normal circumstances, a half-bridge has three working modes, namely a forward conduction mode, a reverse conduction mode, and a blocking mode (i.e., a mode in which both diodes of the half-bridge are turned off). However, when the R on / R off switching model is used for modeling, there is a problem of difficulty in judging the blocking mode, because a real-time simulation adopts a fixed-step solver, and the input current of the half-bridge cannot be accurately calculated to zero, and the blocking mode cannot be identified. The failure to identify the blocking mode will lead to an over-zero oscillation problem and an oscillation problem of a resonant converter during a resonant process. For example, when a series load resonant (SLR) converter works in a resonant process, because the blocking mode cannot be identified, the real-time simulation will produce obvious oscillation phenomena, but the oscillation phenomena will not occur in an actual hardware circuit. The failure to judge the blocking mode will reduce the reliability and precision of the real-time simulation.

[0005] The existing document ("Modeling Method for the Real-Time Simulation of Bridge-Based High-Switching-Frequency Power Electronic Converters," in IEEE Transactions on Power Electronics, vol. 39, no. 9, pp. 11723-11731, Sept. 2024, doi: 10.1109 / TPEL.2024.3402428) proposes a prediction correction method to realize the judgment of the blocking mode, by predicting the state vector, so as to judge whether the state of the diode on the half-bridge changes, and updating the switch state combination of the half-bridge at the current time according to the direction of the current at the last time. However, the prediction correction method needs to calculate the state equation twice, which significantly increases the modeling calculation amount.

[0006] Therefore, it is of great significance to study a simulation method with low calculation amount and ensuring simulation accuracy for reliable simulation of high-frequency power electronic converters. SUMMARY

[0007] In view of the above defects or improvement needs of the prior art, the present application provides a power electronic converter simulation method and system based on a binary resistance model, which aims to reduce the calculation amount and ensure the simulation accuracy.

[0008] To achieve the above-mentioned purpose, the present application provides a power electronic converter simulation method based on a binary resistance model, which comprises:

[0009] obtaining the predicted switch state combination of each half-bridge j at the current k time and calculating the predicted switch state combination σ*(k) of the converter system; the natural switch half-bridge is the actual switch state combination of its k-1 time, and the forced switch half-bridge is determined according to the gate signal of its forced switch;

[0010] determining the state matrix and the input matrix, if the flags flag(k-1) of all natural switch half-bridges at the k-1 time are all no change flags, obtaining the state matrix and the input matrix simulated based on σ*(k) with a step Δt, otherwise, obtaining the state matrix and the input matrix simulated based on σ*(k) with a step 2Δt; constructing the state equation at the k time based on the state matrix, the input matrix, the actual state vector x(k-1) at the k-1 time and the input vector u(k) at the k time, to obtain the predicted state vector x c (k) at the k time;

[0011] according to xc (k) is updated to

[0012] the actual switching state combination σ hd (k) of each natural switching half-bridge at the kth moment is determined or σ hd (k-1) = σ h0 , then σ hd (k) = σ h c d (k), otherwise, σ hd (k) = σ h0 , and σ h0 is the switching state combination in the half-bridge blocking mode;

[0013] flag(k) of each natural switching half-bridge at the kth moment is recorded, if flag(k-1) is the change mark or flag(k) is marked as the no-change mark, otherwise, flag(k) is marked as the change mark;

[0014] the actual state vector x(k) at the current kth moment is corrected, if flag(k-1) of all natural switching half-bridges is the no-change mark and there exists a natural switching half-bridge satisfying then x(k) = x(k-1), otherwise, x(k) = x c (k).

[0015] Optionally, the signal flag takes the first value as the change mark and takes the second value as the no-change mark.

[0016] Optionally, a mark vector flag(k-1) at the (k-1)th moment is constructed, and the mark vector flag(k-1) contains marks of all natural switching half-bridges at the (k-1)th moment.

[0017] it is judged whether the marks of all natural switching half-bridges at the (k-1)th moment are the no-change marks, comprising:

[0018] it is judged whether the mark vector flag(k-1) at the (k-1)th moment is the second value vector, if yes, it is determined that the marks of all natural switching half-bridges at the (k-1)th moment are the no-change marks.

[0019] Optionally, the mark vector flag(k-1) further contains marks of all forced switching half-bridges at the (k-1)th moment, and the marks of the forced switching half-bridges are directly given the second value.

[0020] Optionally, the first value is 1 and the second value is 0.

[0021] Optionally, the switch adopted by the natural switch half-bridge is a diode or a gate switch with a gate signal being 0, and the switch adopted by the forced switch half-bridge is a gate switch and at least one gate signal is not 0.

[0022] Optionally, the power electronic converter is any one of an LLC resonant converter, a series load resonant converter, a dual active bridge converter, and a three-phase inverter.

[0023] The application further provides a power electronic converter simulation system based on a binary resistance model, which comprises:

[0024] a switch state prediction module, configured to obtain a predicted switch state combination of each half-bridge j at a current k moment and calculate a predicted switch state combination σ*(k) of the converter system; the predicted switch state combination σ*(k) of the natural switch half-bridge is an actual switch state combination at a k-1 moment, and the predicted switch state combination σ*(k) of the forced switch half-bridge is determined according to a gate signal of a forced switch thereof;

[0025] a state vector prediction module, configured to determine a state matrix and an input matrix, if all flags flag(k-1) of the natural switch half-bridges at the k-1 moment are no-change flags, obtain the state matrix and the input matrix simulated based on σ*(k) with a step Δt, otherwise, obtain the state matrix and the input matrix simulated based on σ*(k) with a step 2Δt; construct a state equation at the k moment based on the state matrix, the input matrix, an actual state vector x(k-1) at the k-1 moment and an input vector u(k) at the k moment, and obtain a predicted state vector x c (k) at the k moment;

[0026] a switch state prediction update module, configured to update the predicted switch state combination of the natural switch half-bridge to according to x c (k);

[0027] a switch state determination module, configured to correct to obtain an actual switch state combination σ hd (k) of each natural switch half-bridge at the k moment, if or σ hd (k-1)=σ h0 , otherwise, σ hd (k)=σ h0 , and σ h0 is a switch state combination in a half-bridge blocking mode;

[0028] a flag module, configured to record a flag(k) of each natural switch half-bridge at the k moment, if the flag(k-1) is a no-change flag or If flag(k) is unchanged, flag(k) is marked as unchanged, otherwise, flag(k) is marked as changed.

[0029] The state vector correction module is used for correcting the actual state vector x(k) at the current k moment, if all flag(k-1) of the natural switching half-bridge are unchanged and there is a natural switching half-bridge satisfying x(k)=x(k-1), otherwise, x(k)=x c (k).

[0030] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the method according to any one of the above.

[0031] The application further provides a computer program product, which comprises a computer program or instructions, and the computer program or instructions are executed by a processor to realize the steps of the method according to any one of the above.

[0032] Overall, compared with the prior art, the above technical scheme conceived by the application mainly has the following beneficial effects:

[0033] The simulation method of the power electronic converter based on the binary resistance model provided by the application adopts the prediction correction mode to realize the decoupling of the update of the state variable and the update of the switching state combination, analyzes the switching principle of the natural switching half-bridge, realizes the prediction correction of the switching state of the natural switching half-bridge, and when updating the state vector, if the state combination of a natural switching half-bridge changes from the k-2 moment to the k-1 moment, the application forces the state variable at the k-1 moment to maintain the same as that at the k-2 moment, and then updates the state vector at the k moment from the k-2 moment with a double simulation step 2Δt. Therefore, the application can accurately identify the state combination switching moment of the natural switching half-bridge, and only needs to update the natural switching state combination of the half-bridge by using simple logical operation, and only needs to calculate the state equation once in the whole calculation process, so that the modeling calculation amount is extremely low. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a step flow chart of the simulation method of the power electronic converter based on the binary resistance model in an embodiment of the application;

[0035] Figure 2 is a state interval division diagram of a diode half-bridge;

[0036] Figure 3 is a flow chart of the simulation method in an embodiment of the application;

[0037] Figure 4is a SLR converter circuit topology schematic diagram in an embodiment of the present application;

[0038] Figure 5 is an offline simulation waveform comparison of the built SLR converter model and the MATLAB / Simulink reference model in an embodiment;

[0039] Figure 6 is a real-time simulation waveform of the SLR converter model in an embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] In order to facilitate understanding of the present application, the traditional method of simulating power electronic converters based on the binary resistance model is first introduced. The power electronic converter can be an LLC resonant converter, a series load resonant converter, a dual active bridge converter, a three-phase inverter, etc.

[0042] Based on R on / R off The system network equation of the switch model is described by the time-domain state equation shown in formula (1):

[0043]

[0044] In the formula, x is a state vector, u is an input vector, A σ is a time-domain system state matrix, B σ is a time-domain system input matrix, the state vector is composed of the inductor current and the capacitor voltage of the converter, the input vector is composed of the excitation signal source of the converter, and the state matrix and the input matrix can be obtained by deriving the KVL equation of the inductor voltage in the circuit and the KCL equation of the capacitor current in the circuit.

[0045] In order to ensure the numerical stability of the model, formula (1) is discretized by the backward Euler discretization method. The discretized system state equation is shown in formula (2):

[0046]

[0047] In the formula, k is the sampling time of the discrete system, I is the unit matrix, Δt is the simulation step, F σ is a discrete system state matrix, H σ is a discrete system input matrix, and σ is a system switch state combination.

[0048] To solve the system state equation as shown in equation (2), the system switch state combination σ needs to be determined, and the state matrix F is determined based on the system switch state combination σ σ and the input matrix H σ .

[0049] The system switch state combination σ is composed of each half-bridge switch state combination σ h , which reflects the on or off state of the upper switch tube and the lower switch tube of the half-bridge. Assuming that the system contains m half-bridges, the system switch state combination σ is updated using equation (3):

[0050] σ = 4 0 σ h1 + 4 1 σ h2 +....4 m-1 σ hm (3)

[0051] For a half-bridge composed of an upper tube S a and a lower tube S b , there are only four switch state combinations σ h0-3 as shown in equation (4), which correspond to the blocking mode, the reverse conduction mode, the forward conduction mode and the error mode respectively:

[0052]

[0053] To solve the system switch state combination σ as shown in equation (3), the switch state combination of each half-bridge needs to be determined.

[0054] Half-bridges are divided into natural switch half-bridges and forced switch half-bridges according to their control modes. The natural switch half-bridge is a switch controlled by the current direction, such as a diode switch or a gate signal that is 0. The forced switch half-bridge is a switch controlled by a gate signal, such as an IGBT half-bridge with a gate signal that is not 0. Different types of half-bridges have different update methods for their switch state combinations. The switch state combination of the forced switch half-bridge is denoted as forced switch state combination σ hc , and the switch state combination of the natural switch half-bridge is denoted as σ hd , as shown in equation (5):

[0055]

[0056] The forced switch state combination σ hc and the natural switch state combination σ hd of the half-bridge are updated using equations (6) and (7) respectively:

[0057]

[0058]

[0059] update the forced switch state combination σ(k) hc (k) only needs to sample the gate signal g a and g b to complete the update.

[0060] However, according to formula (7), the update of the natural switch state combination σ hd (k) of the half-bridge at time k needs to know the half-bridge input current i h (k) and the half-bridge input voltage v h (k) in advance. But according to formula (2), the update of i h (k) and v h (k) also needs to know σ h (k) in advance, so the update of the state variable and the update of the switch state are coupled.

[0061] The existing research decouples the two calculation processes by using the prediction correction method. First, the switch state combination of the half-bridge is determined by the prediction correction method, and then the state vector is updated. However, the prediction correction stage also needs to calculate the state equation once, so the state equation needs to be calculated twice in the whole modeling process. This significantly increases the modeling calculation amount and the calculation delay. The large calculation delay makes it impossible to meet the requirement of oversampling of the gate signal at high switching frequency, thereby reducing the reliability of real-time simulation.

[0062] The present application provides a power electronic converter simulation method based on a binary resistance model, which only needs to calculate the state equation once by correcting the predicted state variable, thereby reducing the modeling calculation amount.

[0063] As shown in Figure 1 the step flowchart of the power electronic converter simulation method based on the binary resistance model in an embodiment of the present application. It should be noted that the order of the steps is only an example, but is not limited thereto. The steps are described in detail as follows.

[0064] Step S1: obtaining the predicted switch state combination σ of each half-bridge j at the current time k and calculating the predicted switch state combination σ*(k) of the converter system. The natural switch half-bridge is its actual switch state combination at time k-1, and the forced switch half-bridge is determined according to the gate signal of its forced switch.

[0065] In the conventional way, the forced switching state combination and the natural switching state combination of the half-bridge are updated respectively by the above formula (6) and formula (7), wherein the forced switching state combination at time k only needs to sample the gating signal g a and g b , and the half-bridge natural switching state combination at time k is difficult to be directly determined due to the coupling with the state vector.

[0066] In the present application, the forced switching half-bridge is also determined according to the gating signal of its forced switching, and specifically, σ hc,j (k) is determined according to formula (7).

[0067] In the present application, the actual switching state combination σ hd,j (k-1) at the previous time is directly taken as the predicted state combination σ

[0068] Therefore, can be expressed as:

[0069]

[0070] Wherein, the natural switching half-bridge is a switching controlled by the current direction, such as a diode switching or a gate switching with a gating signal of 0, and the forced switching half-bridge is a switching controlled by the gating signal, such as an IGBT half-bridge with a gating signal not being 0.

[0071] The converter system contains m half-bridges, and the predicted switching state combination σ*(k) of the system is updated according to the same way as formula (3), as shown below:

[0072]

[0073] Step S2: determining the state matrix and the input matrix, if the flags flag(k-1) of all the natural switching half-bridges at time k-1 are all the unchanged flags, then the state matrix and the input matrix simulated based on σ*(k) with a step Δt are obtained, otherwise, the state matrix and the input matrix simulated based on σ*(k) with a step 2Δt are obtained, and the state equation at time k is constructed based on the state matrix, the input matrix, the actual state vector x(k-1) at time k-1 and the input vector u(k) at time k, to obtain the predicted state vector x c (k) at time k.

[0074] In step S1, the predicted switching state combination σ*(k) of the system has been preliminarily predicted, and based on the σ*(k), the state matrix and the input matrix under different simulation steps can be calculated, and the state matrix and the input matrix are the coefficient matrices for constructing the system state equation as shown in formula (2).

[0075] In the present application, a flag is set to mark whether the natural switch state combination changes compared to the previous moment. The simulation step length at the current moment is determined based on the flag at the previous moment. Specifically, if the flags of all natural switch half-bridges at k-1 moment are all unchanged flags, the state matrix and input matrix simulated based on σ*(k) with step length Δt are obtained, otherwise, the state matrix and input matrix simulated based on σ*(k) with step length 2Δt are obtained. The flag at the previous moment is determined and recorded at the previous simulation moment.

[0076] In an embodiment, for the convenience of recording, the first value is taken as the changed flag and the second value is taken as the unchanged flag. For example, the first value is 1 and the second value is 0. If flag = 1, it indicates that the on-off state combination of the half-bridge changes, and if flag = 0, it indicates that the on-off state combination of the half-bridge does not change.

[0077] Further, for the convenience of comparison, the flags of all natural switch half-bridges at k-1 moment are combined together to form a flag. For example, the flag vector flag(k-1) contains the flags of all natural switch half-bridges at k-1 moment. Whether the flags of all natural switch half-bridges at k-1 moment are all unchanged flags is determined by judging whether the flag vector flag(k-1) is a second value vector.

[0078] It is considered that the type of the natural switch half-bridge and the forced switch half-bridge may change. For example, when a gate switch is used, if the gate signals of the upper and lower bridge arms are both 0, it is a natural switch half-bridge, otherwise, it is a forced switch half-bridge. For the half-bridge using such a switch, the gate signal may change the type of the half-bridge. Therefore, for the overall planning and the convenience of comparison, all forced switch half-bridges are also marked, and the flags of the forced switch half-bridges are directly assigned to the second value. In this way, the flag vector flag represents the flags of all half-bridges in the system, and whether the type of the half-bridge changes or not, the vector flag can be directly called for judgment.

[0079] For example, the state matrix and the input matrix simulated based on σ*(k) with step length Δt are denoted as and The state matrix and the input matrix simulated based on σ*(k) with step length 2Δt are denoted as and The finally selected state matrix and input matrix are denoted as and

[0080] The matrix and the matrix The following formula (10) and formula (11) are updated:

[0081]

[0082] After determining the state matrix and the input matrix , the system state equation can be constructed according to the above formula (2) as follows:

[0083]

[0084] By solving the system state equation, the state vector at time k is predicted, that is, the predicted state vector x c (k) at time k is obtained.

[0085] Step S3: According to x c (k), the predicted switching state combination of the natural switching half-bridge is updated to

[0086] Through step S2, the state vector x c (k) is predicted, and based on the predicted state vector x c (k), the switching state combination of the natural switching half-bridge is re-predicted according to the above formula (7), and is updated to

[0087] Step S4: Determine the actual switching state combination σ hd (k) of each natural switching half-bridge at time k, if or σ hd (k-1) = σ h0 , then Otherwise, σ hd (k) = σ h0 , and σ h0 is the switching state combination in the half-bridge blocking mode.

[0088] Specifically, the actual switching state combination of the half-bridge is determined according to the updated predicted result , which can be specifically expressed as:

[0089]

[0090] Step S5: Record the flag(k) of each natural switching half-bridge at time k, if the flag(k-1) is a change mark or , then the flag(k) is recorded as a no-change mark, otherwise, the flag(k) is recorded as a change mark.

[0091] Specifically, the update formula of the flag(k) can be expressed in the following form:

[0092]

[0093] Step S6: Correct the actual state vector x(k) at the current time k. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

[0094] Specifically, the update formula of the actual state vector x(k) can be expressed as follows:

[0095]

[0096] Where, is a vector consisting of the natural switching state combinations of all natural switching half-bridges at time k.

[0097] The principle of the above scheme is explained below.

[0098] First, the prediction and correction methods of the natural half-bridge switching state are explained.

[0099] In the present invention, there is a coupling problem between the update of the state variables and the update of the switch state combination. The present invention also adopts a prediction correction method to achieve the decoupling of the two calculation processes. When making a prediction in step S1, it is assumed that the switching state of the natural switch half bridge at time k has not changed compared with time k-1, that is, Based on this assumption, the state equation is constructed to obtain the predicted state vector x based on this assumption. c (k), and then analyze the state vector x c (k) The switching state of the natural switching half-bridge under the above assumptions is consistent with the switching state assumed. This shows that the prediction is accurate and the actual switching state combination of the natural switching half bridge at time k

[0100] At the same time, by analyzing the switching principle of the natural switching half-bridge, if the above prediction results are not met, the prediction results can also be corrected.

[0101] Take the diode half bridge as an example, Figure 2 The diagram shows the state interval division of the diode half bridge. The state switching principle of the diode half bridge is: due to the half bridge input current i h and the half-bridge input voltage v h are all continuously changing, for example, i h is the inductor current of the half bridge, v hCapacitor voltage or input DC voltage of half-bridge is not abrupt, so when state changes from forward conducting mode (σ h2 ) or reverse conducting mode (σ h1 ), it must enter blocking mode (σ h0 ); when state changes from blocking mode, it will enter either conducting mode as long as v h is greater than zero. Therefore, the prediction correction method is used to predict whether the state of diode half-bridge changes and correct the switch state combination according to the above state change principle.

[0102] If the half-bridge is in blocking mode (σ h0 ) at k-1 time, it may enter any mode at k time, so the prediction result is usually accurate, and the prediction result is directly used as the actual result without correction, i.e. if σ hd (k-1) == σ h0 , it is considered that

[0103] The prediction of the above two cases is considered to be a problem, i.e. the half-bridge is not in blocking mode (σ h0 ) at k-1 time, and the prediction result reflects that the switch state of the half-bridge at k time is different from that at k-1 time, which indicates that the switch state of the half-bridge at k time changes. Based on the above analysis of the state interval of the half-bridge, the half-bridge can only enter blocking mode from non-blocking mode at k-1 time, so it needs to be corrected to blocking mode (σ h0 ), i.e. σ hd (k) = σ h0 .

[0104] Thus, the switch state prediction correction formula of formula (13) in the above step S4 is obtained.

[0105] Secondly, the determination of the state vector is described.

[0106] In the present application, if a natural switch half-bridge changes its state combination from k-2 time to k-1 time, the present application forces the state variable at k-1 time to maintain the same as that at k-2 time, i.e. x(k-1) = x(k-2), and then updates the state vector x(k) at k time from k-2 time with a double simulation step 2Δt. This method can reduce the amount of calculation.

[0107] For convenience of representation, the state vector updated with a simulation step Δt is denoted as x p (k), and the state vector updated with a double simulation step 2Δt is denoted as x 2ΔtThe predicted system switch status combination at time k is denoted as

[0108] If the predicted switch status at time k-1 has changed, i.e. if then the state vector x(k) at time k is updated from time k-2 with double simulation step size 2Δt, i.e. x(k) = x(k-2) + 2Δt 2Δt (k).

[0109] If the predicted switch status at time k-1 has not changed, but the predicted switch status at time k has changed, i.e. if and then the state variable at time k is forced to maintain the same as that at time k-1, i.e. x(k) = x(k-1).

[0110] If the predicted switch status at time k-1 has not changed, and the predicted switch status at time k has not changed, i.e. if and then the predicted x p (k) is simulated normally at time k with single simulation step size, and x(k) = x p (k).

[0111] In summary, the state vector at time k is updated as shown in equation (16) below:

[0112]

[0113] The system state equation for predicting x p (k) with single simulation step size Δt is shown below:

[0114]

[0115] where matrix and matrix are the coefficient matrices corresponding to switch status combination σ* with single simulation step size Δt.

[0116] The system state equation for updating x 2Δt (k) with double step size is shown below:

[0117]

[0118] where matrix and matrix are the coefficient matrices corresponding to switch status combination σ* with double simulation step size 2Δt.

[0119] It can be seen that the updating of x p (k) in equation (16) is equivalent to the updating of x2Δt (k) corresponds to a different system state equation, so the state equation needs to be calculated twice. Compared with the traditional method, its computational complexity has no obvious advantage.

[0120] However, since the present invention proposes that when the state combination switches from time k-1 to time k, the algorithm of formula (15) forces x(k) to be equal to x(k-1), therefore, when condition 3 in formula (16) When it is satisfied, x(k-1)=x(k-2). Therefore, formula (18) can be rewritten as shown in formula (19):

[0121]

[0122] Since x in the update formula (17) p (k) and x in formula (19) 2Δt (k) needs to use x(k-1) and u(k), that is, update x p (k) and x 2Δt (k) The corresponding system state equation has the same form, that is, the function is the same. The only difference is that the coefficient matrix substituted into the function is different. Therefore, the corresponding coefficient matrix can be selected at different times according to whether the state change occurs at the current time and the previous time, and the same function can be substituted, thereby calculating the system state equation only once.

[0123] Therefore, x can be p (k) and x 2Δt (k) is uniformly represented as the state vector x c , the coefficient matrix under different step lengths is uniformly expressed as a matrix and the matrix x p (k) and x 2Δt (k) The corresponding system state equation is uniformly expressed as the following form of the above formula (20):

[0124]

[0125] At the same time, the flag signal is used to indicate whether the switching state combination of the natural switching half-bridge has changed. Therefore, the final equation (16) can be rewritten as the following form of the above equation (21):

[0126]

[0127] Therefore, at each moment, only the corresponding coefficient matrix is selected in step S2 according to whether the state changes at the current moment and the last moment, so that the system state equation is calculated only once each time, and the operation amount is greatly reduced. Moreover, when the state matrix and the input matrix are determined, the system switch state combination σ*(k) based on the system considers the influence of the gate signal at the k moment, compared with the traditional prediction correction mode which does not consider the influence of the gate signal at the k moment on the state variable, the prediction mode has higher precision.

[0128] As Figure 3 shown is a flowchart of the simulation method in an embodiment of the application, the whole step is divided into three stages: at the k moment, in stage 1, the predicted state vector x c (k) is updated, then in stage 2, the predicted half-bridge switch state combination and the flag signal flag(k) and the half-bridge switch state combination σ hd (k) are sequentially updated, wherein the flag signal flag(k) and the half-bridge switch state combination σ hd (k) can be calculated in parallel. Finally, in stage 3, the combination of the vectors flag(k), σ hd (k) and the update of the state vector x(k) are completed.

[0129] The significant advantages of the application are: 1) the state combination switching moment of the natural switch half-bridge can be accurately identified, and the half-bridge natural switch state combination can be updated only by simple logical operation; 2) the state equation needs to be calculated only once in the whole calculation process, so the modeling calculation amount is extremely low; 3) the modeling calculation path is short, which greatly improves the modeling calculation efficiency, so that the gate signal oversampling can be guaranteed at high switching frequency.

[0130] Correspondingly, the application also relates to a power electronic converter simulation system based on a binary resistance model, which comprises:

[0131] a switch state prediction module, used for acquiring the predicted switch state combination σ of each half-bridge j at the current k moment and calculating the predicted switch state combination σ*(k) of the converter system; the actual switch state combination of the natural switch half-bridge is its actual switch state combination at the k-1 moment, and the actual switch state combination of the forced switch half-bridge is determined according to the gate signal of the forced switch;

[0132] ​a state vector prediction module, configured to determine a state matrix and an input matrix, if flags of all natural switch half-bridges at k-1 time are all no-change flags, obtain the state matrix and the input matrix simulated based on σ*(k) with a step Δt, otherwise, obtain the state matrix and the input matrix simulated based on σ*(k) with a step 2Δt; construct a state equation at k time based on the state matrix, the input matrix, an actual state vector x(k-1) at k-1 time and an input vector u(k) at k time, and obtain a predicted state vector x(k) at k time; c (k).

[0133] a switch state prediction updating module, configured to update a predicted switch state combination of the natural switch half-bridge to c (k) according to x

[0134] a switch state determination module, configured to correct an actual switch state combination σ hd (k) of each natural switch half-bridge at k time, if σ hd (k-1)=σ h0 , otherwise, σ hd (k)=σ h0 , and σ h0 is a switch state combination in a half-bridge blocking mode.

[0135] a flag module, configured to record a flag(k) of each natural switch half-bridge at k time, if the flag(k-1) is a no-change flag or , the flag(k) is recorded as a no-change flag, otherwise, the flag(k) is recorded as a change flag.

[0136] a state vector correction module, configured to correct an actual state vector x(k) at current k time, if the flag(k-1) of all natural switch half-bridges are all no-change flags and there is a natural switch half-bridge satisfying , x(k)=x(k-1), otherwise, x(k)=x c (k).

[0137] It can be understood that the above system can be used to implement the simulation method in the foregoing, and each module in the system can be used to implement the corresponding step in the simulation method. Details can be referred to the foregoing description, and will not be repeated here.

[0138] The application also relates to a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the method.

[0139] Specifically, the storage medium can be an FPGA chip.

[0140] The present application also provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the steps of the above-mentioned embodiment method of the present application.

[0141] To verify the practicability of the method of the present application, an SLR converter is simulated as shown in the following figure. Figure 4 Figure 4 The SLR converter shown in the figure comprises a resonant inductor L r , a resonant capacitor C r , an output capacitor C o , and a load R o . The primary side full-bridge of the SLR converter model comprises a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, and the secondary side full-bridge of the SLR converter model comprises a first diode d1, a second diode d2, a third diode d3 and a fourth diode d4. Lr is the current flowing through the resonant inductor L r , u Cr is the voltage on the resonant capacitor C r , u o is the voltage on the output capacitor C o , v in is the input DC voltage, and g 1-4 is the gate signal of the switch S 1-4 , and the switching frequency is f s . The control strategy of the model uses switching control, the switching frequency is f s is 100 kHz, the gate signals g1 and g2 are complementary and have a 300 ns dead time, and the gate signals g3 and g4 are complementary and have a 300 ns dead time.

[0142] The circuit parameters of the SLR converter model are set as shown in the following table:

[0143]

[0144]

[0145] Figure 5 The waveform comparison between the SLR model established by writing m language code in the System generator software and the MATLAB / Simulink reference model is shown in the following figure. The simulation model established by the present application is denoted as “Model”, and the MATLAB / Simulink reference model is denoted as “Reference”. The simulation step of the model is 20 ns. Figure 5 ​(a), (b), (c), (d) in the figure respectively show the resonance current i Lr of the built model and the MATLAB / Simulink reference model Cr of the built model and the MATLAB / Simulink reference model Lr of the built model and the MATLAB / Simulink reference model Cr of the built model and the MATLAB / Simulink reference model

[0146] It can be seen from Figure 5 that the built model of the application not only does not have the zero-crossing oscillation problem caused by ignoring the blocking mode compared with the MATLAB / Simulink reference model, but also achieves extremely high precision, the absolute error of the resonance current i Lr and the resonance capacitor voltage v Cr is less than 0.18A and 0.11V.

[0147] In order to further verify the reliability of the method proposed in the application, real-time simulation verification is carried out. The built model of real-time simulation is realized by writing Verilog code in Vivado software. The real-time simulation platform of this experiment is composed of an Alinx AX7325B FPGA development board, the FPGA model is XC7K325TFFG900-2, which has 203800 lookuptables (LUTs), 840 DSP48slices (DSP48s), 445 Block RAMs (BRAMs) and 407600 Flipflops. The digital signal generated by the FPGA generates analog variables on the oscilloscope through the AD9767 digital-to-analog chip.

[0148] Figure 6 The real-time simulation test waveform is given, including the resonance current i Lr and the resonance capacitor voltage v Cr . The simulation step can be as low as 20ns, and the switching frequency is 100kHz.

[0149] It can be seen from Figure 6 that the built model can normally run at a simulation step of 20ns and the real-time simulation is consistent with the offline simulation. The reliability of the built model of the application is verified. The simulation step of 20ns also far guarantees the oversampling requirement of 100kHz switching frequency.

[0150] The resource test results of the SLR converter real-time simulation model are shown in the following table:

[0151] Parameter Value Total amount of resources LUTs 2107(1.03％) 203800 DSP48s 36(4.29％) 840 BRAMs 0 445 Flipflops 683(0.17％) 407600

[0152] As can be seen from the above table, the built SLR converter model has extremely low resource consumption.

[0153] In summary, the blocking mode recognition method provided by the application can not only accurately determine the half-bridge blocking mode switching time, but also greatly reduces the modeling calculation amount and the FPGA calculation resource consumption by calculating the state equation only once. Meanwhile, the model can also run normally under a 20ns simulation step, which indicates that the method provided by the application can guarantee the oversampling of the gate signal under a high switching frequency, and improves the FPGA calculation efficiency.

[0154] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application. It should be noted that the "in an embodiment of the present application", "for example", "for instance" and the like are intended to illustrate the present application, but not to limit the present application.

[0155] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A power electronic converter simulation method based on a binary resistance model, characterized in that: include: Get the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch; Determine the state matrix and input matrix. If the flags flag(k-1) of all natural switch half-bridges at time k-1 are unchanged, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of △t. Otherwise, obtain the state matrix and input matrix simulated based on σ*(k) with a step size of 2△t. Construct the state equation at time k based on the state matrix, input matrix, actual state vector x(k-1) at time k-1, and input vector u(k) at time k, and obtain the predicted state vector x at time k. c (k); According to x c (k) Update the predicted switching state combination of the natural switching half bridge to Determine the actual switching state combination σ of each natural switching half bridge at time k hd (k) If or σ hd (k-1)=σ h0 ,but Otherwise, σ hd (k)=σ h0 ,σ h0 is the switch state combination in half-bridge blocking mode; Record the flag(k) of each natural switch half bridge at time k. If flag(k-1) is a change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark; Correct the actual state vector x(k) at the current k moment. If the flag(k-1) of all natural switch half-bridges is unchanged and there is a natural switch half-bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

2. The simulation method according to claim 1, wherein: The signal flag takes the first value as a change mark and the second value as a no-change mark.

3. The simulation method according to claim 2, wherein: Construct a flag vector flag(k-1) at time k-1, where the flag vector flag(k-1) contains the flags of all natural switch half-bridges at time k-1; Determine whether the marks of all natural switching half-bridges at time k-1 are all unchanged marks, including: It is determined whether the flag vector flag(k-1) at time k-1 is the second value vector. If so, it is determined that the flags of all natural switch half bridges at time k-1 are unchanged flags.

4. The simulation method according to claim 3, wherein: The flag vector flag(k-1) also includes flags of all forced switching half bridges at time k-1, and the flags of the forced switching half bridges are directly assigned to the second value.

5. The simulation method according to any one of claims 2 to 4, wherein: The first value is 1 and the second value is 0.

6. The simulation method according to claim 1, wherein: The switches used by the natural switching half-bridge are diodes or gate-controlled switches whose gate control signals are all 0, and the switches used by the forced switching half-bridge are gate-controlled switches and at least one gate control signal is not 0.

7. The simulation method according to claim 1, wherein: The power electronic converter is any one of an LLC resonant converter, a series load resonant converter, a dual active bridge converter, and a three-phase inverter.

8. A power electronic converter simulation system based on a binary resistance model, characterized in that: include: The switch state prediction module is used to obtain the predicted switch state combination of each half bridge j at the current time k And calculate the predicted switching state combination σ*(k) of the converter system; the natural switching half bridge The actual switch state combination at time k-1 forces the switching half bridge to Determined by the gate signal of its forced switch; The state vector prediction module is used to determine the state matrix and input matrix. If the flags flag(k-1) of all natural switch half-bridges at time k-1 are unchanged, the state matrix and input matrix simulated based on σ*(k) with a step size of △t are obtained. Otherwise, the state matrix and input matrix simulated based on σ*(k) with a step size of 2△t are obtained. The state equation at time k is constructed based on the state matrix, input matrix, actual state vector x(k-1) at time k-1 and input vector u(k) at time k to obtain the predicted state vector x at time k. c (k); The switch state prediction update module is used to update the switch state according to x c (k) Update the predicted switching state combination of the natural switching half bridge to The switch state determination module is used to correct the actual switch state combination σ of each natural switch half bridge at time k hd (k) If or σ hd (k-1)=σ h0 ,but Otherwise, σ hd (k)=σ h0 , σ h0 is the switch state combination in half-bridge blocking mode; The marking module is used to record the flag (k) of each natural switch half bridge at time k. If flag (k-1) is a no-change mark or Then flag(k) is recorded as no change mark, otherwise, flag(k) is recorded as a change mark; The state vector correction module is used to correct the actual state vector x(k) at the current k moment. If the flag(k-1) of all natural switch half bridges is unchanged and there is a natural switch half bridge that satisfies Then x(k)=x(k-1), otherwise, x(k)=x c (k).

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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