Photoelectric device array structure and preparation method thereof

Abstract

The invention discloses a photoelectric device array structure and a preparation method thereof, and relates to the technical field of semiconductors. The method comprises the steps that a driving wafer and compound pixels are bonded and integrated through bonding structures on the surfaces of the driving wafer and the compound pixels, a bonded device is formed, and a reflector layer and a first semiconductor layer are stacked on the surface of the side, away from the driving wafer, of the bonding structures corresponding to the compound pixels; pixelization is carried out on compound pixels in the bonded device, etching is carried out to a part of the first semiconductor layer in the compound pixels, so that the other part of the first semiconductor layer is reserved, a plurality of continuous pixel units on the first semiconductor layer are obtained, and each pixel unit is electrically connected with a first electrode contact in the driving wafer. Pixel isolation is carried out on a plurality of continuous pixel units, and a reflection cavity structure surrounding the pixel units is prepared; and preparing a second conductive electrode at the top of the pixel unit after pixel isolation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a photoelectric device array structure and a preparation method thereof. Background Art

[0002] Optoelectronic device array structures (such as Micro LED) are the core chips of devices such as AR (augmented reality) / VR (virtual reality). Compared with technologies such as LCOS (liquid crystal on silicon) and OLED (organic light-emitting diode), optoelectronic device array structures are regarded as the best solution due to their advantages such as high resolution, low power consumption, high brightness and long life.

[0003] The optoelectronic device array structure is generally made of compound pixels and driving wafers, wherein the compound pixels include: a first semiconductor layer, an active layer and a second semiconductor layer. In order to form contact between the semiconductor layers, a transparent conductive film is generally prepared on the surface of the first semiconductor layer as the first semiconductor contact layer, and then a bonding structure is prepared on the transparent conductive film and the driving wafer respectively, and the bonding integration of the compound pixels and the driving wafer is completed through the bonding structure.

[0004] Although the transmittance of transparent conductive film is very high, it still cannot achieve full transparency, which will cause optical loss and fail to achieve the best reflection effect. At the same time, the thickness of this film is limited. When the film is too thin, the resistance is large. When the transparent conductive oxide film is thicker, the resistance and etching anomalies will be improved, but the reflectivity will be reduced. Therefore, the contradiction between the thickness of the transparent conductive film and the brightness and voltage makes it impossible for the optoelectronic device array structure to obtain the best device performance. Summary of the invention

[0005] The object of the present invention is to provide an optoelectronic device array structure and a preparation method thereof, which can greatly reduce the loss of light between the pixel unit and the metal of the reflector layer when there is no transparent conductive film or the transparent conductive film is extremely thin, thereby achieving optimal brightness improvement.

[0006] In order to achieve the above-mentioned object of the invention, the present invention proposes the following technical solutions:

[0007] In one aspect, a method for preparing an optoelectronic device array structure is provided, the method comprising:

[0008] The driving wafer and the compound pixel are bonded and integrated through the bonding structures on their respective surfaces to form a bonded device, wherein a reflector layer and a first semiconductor layer are stacked on a surface of the bonding structure corresponding to the compound pixel on a side away from the driving wafer;

[0009] Pixelating the compound pixel in the bonded device, etching a portion of the first semiconductor layer in the compound pixel so that another portion of the first semiconductor layer remains, and obtaining a plurality of continuous pixel units on the first semiconductor layer, each of the pixel units being electrically connected to a first electrode contact in the driving wafer;

[0010] Performing pixel isolation on a plurality of continuous pixel units, and preparing a reflective cavity structure surrounding the pixel units, wherein the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel units;

[0011] A second conductive electrode is prepared on the top of the pixel unit after pixel isolation, and the second conductive electrode is electrically connected to the second electrode contact in the driving wafer.

[0012] In a possible implementation manner, before performing pixel isolation on a plurality of consecutive pixel units, the method further includes:

[0013] Depositing an insulating medium on the outer surfaces of a plurality of consecutive pixel units to prepare a passivation layer;

[0014] An insulating dielectric is deposited again on the surface of the passivation layer to prepare a sidewall structure.

[0015] In a possible implementation, the pixel isolation of a plurality of continuous pixel units and the preparation of a reflective cavity structure surrounding the pixel units include:

[0016] The sidewall structure is etched in the first step to retain the sidewall structure of each pixel unit sidewall portion; the passivation layer, the first semiconductor layer, the reflector layer and the bonding structure continuous between adjacent pixel units are etched in the second step to complete pixel isolation and the preparation of the reflective cavity structure.

[0017] In a possible implementation, the second etching step adopts any one of the following methods:

[0018] Ion beam etching (IBE) or neutral beam etching (NBE).

[0019] In a possible implementation, after the second etching step is completed, the method further includes:

[0020] Filling the entire surface of the isolated pixel unit with an insulating medium to prepare a first insulating layer;

[0021] or,

[0022] The isolated pixel units are covered with a film layer of an insulating medium to prepare a second insulating layer.

[0023] In a possible implementation, after the first insulating layer is prepared and before the second conductive electrode is prepared, the method further includes:

[0024] A first metal grid structure is prepared in the first insulating layer between adjacent pixel units, the top of the first metal grid structure is in contact with the second conductive electrode, and the bottom of the first metal grid structure is higher than the surface of the driving wafer.

[0025] In a possible implementation, the step of preparing a second conductive electrode on the top of the pixel unit after pixel isolation includes:

[0026] An opening is made at the top of the pixel unit to expose the second semiconductor layer of the pixel unit;

[0027] A conductive film is deposited on the top of each pixel unit to form the second conductive electrode, and the second conductive electrode connects the second semiconductor layer exposed by each pixel unit.

[0028] In a possible implementation manner, before forming the second conductive electrode, the method further includes:

[0029] A connected metal filling structure is prepared between the second conductive electrode and the second electrode contact.

[0030] In a possible implementation manner, during the preparation of the pixel unit, the method further includes:

[0031] A redundant structure is simultaneously prepared around the outer periphery of the pixel unit.

[0032] In a possible implementation, the method further includes:

[0033] A second metal grid structure is formed on top of the second conductive electrode.

[0034] In a possible implementation, the preparation process of the compound pixel includes:

[0035] The reflector layer is directly formed on the first semiconductor layer of the compound pixel.

[0036] On the other hand, an optoelectronic device array structure is provided, wherein the optoelectronic device array structure is prepared by the optoelectronic device array intermediate structure as described in the above aspect, and the optoelectronic device array structure comprises: a driving wafer and a compound pixel;

[0037] The compound pixel and the driving wafer are respectively provided with bonding structures, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the reflector layer in the compound pixel;

[0038] The compound pixel includes a plurality of mutually isolated pixel units, each of which is electrically connected to a first electrode contact in the driving wafer;

[0039] The outer periphery of the pixel unit is surrounded by a reflective cavity structure, the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel unit, and the first semiconductor layer at least includes a stacked first partial layer and a second partial layer, the first partial layer is in contact with the reflector layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer;

[0040] A second conductive electrode is disposed on the top of the pixel unit, and the second conductive electrode is electrically connected to a second electrode contact in the driving wafer.

[0041] In a possible implementation, a passivation layer is attached to the outer surface of the pixel unit;

[0042] The reflective cavity structure is also connected to the outer edge of the passivation layer.

[0043] In a possible implementation manner, a sidewall structure is provided between the reflective cavity structure and the passivation layer on the sidewall surface of the pixel unit.

[0044] In a possible implementation, the entire outer periphery of the pixel unit is filled with a first insulating layer;

[0045] or,

[0046] The outer periphery of the pixel unit is covered with a second insulating layer in a thin film style.

[0047] In a possible implementation manner, the first insulating layer is filled with a first metal grid structure, the top of the first metal grid structure is in contact with the second conductive electrode, and the bottom of the first metal grid structure is higher than the surface of the driving wafer.

[0048] In a possible implementation manner, a interconnected metal filling structure is provided between the second conductive electrode and the second electrode contact.

[0049] In a possible implementation manner, a second metal grid structure is further disposed on top of the second conductive electrode.

[0050] In a possible implementation manner, at least one second electrode contact is disposed inside the pixel area of ​​the driving wafer.

[0051] In a possible implementation manner, a first semiconductor contact layer is disposed between the reflector layer and the first semiconductor layer.

[0052] In a possible implementation manner, the thickness of the first semiconductor contact layer is no more than 70 nm.

[0053] In a possible implementation manner, a redundant structure is arranged around the outer periphery of the pixel unit.

[0054] In a possible implementation manner, the distribution width of the redundant structure is not less than the minimum value of the pixel unit size in the pixel area.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] The driving wafer and the compound pixel are bonded and integrated through the bonding structures on their respective surfaces to form a bonded device, wherein a reflector layer and a first semiconductor layer are stacked on the surface of the bonding structure corresponding to the compound pixel which is away from the driving wafer; the compound pixel in the bonded device is pixelated, and a part of the first semiconductor layer in the compound pixel is etched so that another part of the first semiconductor layer is retained, thereby obtaining a plurality of continuous pixel units on the first semiconductor layer, and each pixel unit is electrically connected to the first electrode contact in the driving wafer; the plurality of continuous pixel units are pixel isolated, and a reflective cavity surrounding the pixel unit is prepared. The structure is characterized in that the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel unit; a second conductive electrode is prepared on the top of the pixel unit after the pixel is isolated, and the second conductive electrode is electrically connected to the second electrode contact in the driving wafer; thus, when a bottom reflector layer is provided in the device, the electrical connection of the retained part of the first semiconductor layer and the reflective cavity structure is enhanced, and while solving the electrical connection problem when there is no transparent conductive film or the transparent conductive film is extremely thin and the leakage problem when the pixel is etched to the metal, the loss of light between the compound and the reflector metal is greatly reduced, thereby achieving the best brightness improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a method flow chart of a method for preparing a photoelectric device array structure provided in an embodiment of the present application;

[0058] Figure 2 is a schematic diagram of the structure of a compound pixel provided in an embodiment of the present application;

[0059] Figure 3is a schematic structural diagram of a driver wafer provided in an embodiment of the present application;

[0060] Figure 4 is a schematic structural diagram of a bonded device provided in an embodiment of the present application;

[0061] Figure 5 is a schematic structural diagram of a pixelated device provided in an embodiment of the present application;

[0062] Figure 6 is a schematic structural diagram of a pixel-isolated device provided in an embodiment of the present application;

[0063] Figure 7 is a schematic structural diagram of another pixelated device provided in an embodiment of the present application;

[0064] Figure 8 It is a schematic structural diagram of a device after an insulating layer is prepared provided in an embodiment of the present application;

[0065] Fig. 9 is a schematic structural diagram of another device after the insulating layer is prepared provided in an embodiment of the present application;

[0066] Fig.10 is a schematic structural diagram of a device after opening preparation provided in an embodiment of the present application;

[0067] Fig.11 It is a schematic structural diagram of a device after the second conductive electrode is prepared provided in an embodiment of the present application;

[0068] Fig.12 is a structural schematic diagram of an optoelectronic device array structure having a first metal grid structure and a metal filling structure provided in an embodiment of the present application;

[0069] Fig.13 is a structural schematic diagram of an optoelectronic device array structure with a metal filling structure provided in an embodiment of the present application;

[0070] Fig.14 is a schematic structural diagram of an optoelectronic device array structure with a second electrode contact in a pixel provided in an embodiment of the present application;

[0071] Fig.15 is a schematic structural diagram of another optoelectronic device array structure with a second electrode contact in a pixel provided in an embodiment of the present application;

[0072] Fig.16 is a schematic structural diagram of an optoelectronic device array structure with an optical enhancement structure provided in an embodiment of the present application;

[0073] Fig.17is a structural schematic diagram of another optoelectronic device array structure with an optical enhancement structure provided in an embodiment of the present application;

[0074] Fig.18 It is a structural schematic diagram of a non-continuous bonding structure provided in an embodiment of the present application.

[0075] Reference numerals:

[0076] 100-driving wafer, 110-first electrode contact, 120-second electrode contact, 200-compound pixel, 210-pixel unit, 211-bonding structure, 212-reflector layer, 213-first semiconductor layer, 214-active layer, 215-second semiconductor layer, 216-substrate, 220-reflection cavity structure, 230-passivation layer, 240-side wall structure, 251-first insulating layer, 252-second insulating layer, 261-first metal grid structure, 262-metal filling structure, 270-redundant structure, 280-second conductive electrode, 290-microlens. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0078] In the description of the present invention, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0079] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0080] In the embodiment of the present application, by pixelating the compound, the electrical connection of the partially retained first semiconductor layer and the reflective cavity structure of the side wall is enhanced, thereby solving the electrical connection problem when there is no transparent conductive film or the transparent conductive film is extremely thin and the leakage problem when the pixel is etched to the metal. When there is no transparent conductive film or the transparent conductive film is extremely thin, the light loss between the pixel unit and the metal of the reflector layer is greatly reduced, thereby achieving the best brightness improvement.

[0081] Next, the method for preparing the device structure proposed in this application is described.

[0082] like Figure 1 As shown, the method for preparing the optoelectronic device array structure may include the following steps:

[0083] Step S1: bonding and integrating the driving wafer and the compound pixel through the bonding structures on their respective surfaces to form a bonded device, wherein a reflector layer and a first semiconductor layer are stacked on the surface of the bonding structure corresponding to the compound pixel away from the driving wafer.

[0084] Specifically, Figure 2 , Figure 3 As shown, a bonding structure 211 is prepared on the compound pixel 200 and the driving wafer 100 , and the bonding structure 211 includes Au, Cu, AuSn, CuSn, etc.

[0085] Among them, the bonding structure 211 can be a patterned discontinuous metal layer. The bonding structure 211 can be continuous only in the pixel area, which is the area for preparing the pixel unit, but is a discontinuous film layer in the non-pixel area. The non-pixel area is filled with an insulating medium for support. The insulating medium can be one or more of SiO2, Si3N4, PI and other media. The patterned discontinuous metal layer can achieve better bonding warpage and metal cost control. Exemplary, combined with reference Fig.18 The bonding structure 211 on the surface of the driving wafer 100 and the bonding structure 211 on the surface of the compound pixel 200 are discontinuous metal layers.

[0086] Among them, Figure 2As shown, a reflector layer 212 may be stacked on the bonding structure 211 at the end of the compound pixel 200, and the reflector layer 212 is used to reflect the light entering the bottom of the compound pixel 200. The reflector layer 212 includes metal layers such as Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, AuBe / Ag, Cr / Pt, Cr / Rh, etc. Further, an adhesion barrier layer may be provided between the reflector layer 212 and the bonding structure 211, and the adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.

[0087] If necessary, a transparent oxide such as ITO, ZnO, etc. can be inserted between the reflector layer and the first semiconductor layer as the first semiconductor contact layer to reduce the difficulty of ohmic contact of the first semiconductor layer. The thickness of the transparent oxide is in the range of 0 to 70 nm.

[0088] Among them, an adhesion barrier layer may be provided between the bonding structure at the driving wafer end and the driving wafer. The bonding structure includes Au, Cu, AuSn, CuSn, etc. The adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.

[0089] Exemplarily, a partial cross-section of a single chip of a compound pixel and a driver wafer having a bonding structure is shown below:

[0090] In one embodiment, the reflector layer at the compound pixel end is a double-layer structure of 10nm ITO and 100nm Al, the adhesion barrier layer is 50nm Ni, 50nm Cr and 50nm Pt, and the bonding structure is a stack of 100nm Au and 100nm Sn;

[0091] In one embodiment, the adhesion barrier layer at the driver wafer end is 50 nm Cr and 50 nm Pt, and the bonding structure is a stack of 100 nm Au and 100 nm Sn.

[0092] Further, such as Figure 4 As shown, after the bonding integration of the two wafer surfaces is completed through the bonding structures 211 on the surfaces of the two wafers, the substrate 216 on the surface of the compound pixel 200 can be removed.

[0093] In a possible implementation, the preparation process of the compound pixel includes: directly preparing a reflector layer on the first semiconductor layer of the compound pixel. That is, instead of preparing a transparent conductive film as the first semiconductor contact layer on the surface of the first semiconductor layer, a reflector layer can be directly prepared thereon, thereby avoiding the optical loss caused by the first semiconductor contact layer. It is understandable that in addition to not preparing the first semiconductor contact layer, a first semiconductor contact layer with a thickness of no more than 70nm can also be prepared. In the case of thinning the first semiconductor contact layer, the influence of the excessive thickness of the first semiconductor contact layer on the optical performance of the device can be avoided as much as possible.

[0094] Step S2: pixelating the compound pixels in the bonded device, etching part of the first semiconductor layer in the compound pixels so that another part of the first semiconductor layer is retained, and obtaining a plurality of continuous pixel units on the first semiconductor layer, each pixel unit being electrically connected to the first electrode contact in the driving wafer.

[0095] Specifically, Figure 5 As shown, the compound pixel is patterned and etched in pixel array, for example, the number of pixel units 210 obtained by etching is not less than 3, and each pixel unit 210 is electrically connected to the first electrode contact 110 in the driving wafer 100. In the patterned etching, the structure of the compound pixel is not completely isolated, and a portion of the first semiconductor layer 213 is retained, and the retained thickness is 30nm to 400nm, which can ensure that the active layer 214 is completely disconnected. It can be understood that the figure only uses the one-to-one correspondence between the pixel unit 210 and the first electrode contact 110 for exemplary description, and each pixel unit 210 can also correspond to multiple first electrode contacts 110.

[0096] It is understandable that, during the pixelization process, the retention of part of the first semiconductor layer can avoid over-etching of the metal during pixel patterning, which may lead to metal precipitation and leakage and other device failure problems.

[0097] Step S3: performing pixel isolation on a plurality of continuous pixel units, and preparing a reflective cavity structure surrounding the pixel units, wherein the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel units.

[0098] Specifically, Figure 6 As shown, pixel isolation is further performed on the pixel units 210 that are continuous in the first semiconductor layer 213, and the structure of the compound pixel is completely isolated to obtain completely isolated pixel units 210. During the pixel isolation process, a reflective cavity structure 220 is prepared around each pixel unit 210, and the reflective cavity structure 220 is connected to the outer edges of the first semiconductor layer 213, the reflector layer 212, and the bonding structure 211 in the pixel unit 210.

[0099] It can be understood that the reflective cavity structure forms a cylindrical cavity structure for the pixel unit, in which the light waves emitted by the pixel unit can be reflected back and forth to provide optical positive feedback, thereby greatly improving the luminous efficiency of the device.

[0100] In a possible implementation, before pixel isolation is performed on multiple consecutive pixel units, the following steps are also included: insulating medium is deposited on the outer surface of the multiple consecutive pixel units to prepare a passivation layer; and insulating medium is deposited again on the surface of the passivation layer to prepare a sidewall structure.

[0101] Specifically, in Figure 5 After the structure shown, and Figure 6 Before the structure shown, Figure 7 As shown, a passivation layer 230 and a sidewall structure 240 are further prepared on the pixel unit 210 after the active layer 214 is separated. The passivation layer 230 is used to passivate and protect the pixel unit 210, and the sidewall structure 240 is used to provide support for the subsequent formation of the reflective cavity structure 220. The passivation layer 230 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride. The sidewall structure 240 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.

[0102] In one embodiment, the compound pixel is patterned and etched through a silicon nitride hard mask, retaining a 100nm first semiconductor layer, and then passivation treatment is performed to form a passivation layer, which can be a dielectric layer of silicon oxide, silicon oxide, or silicon nitride, and the thickness of the passivation layer is 10nm to 200nm.

[0103] After preparing the passivation layer and the side wall structure, the above step S3 may further specifically include: performing a first step of etching the side wall structure to retain the side wall structure of the side wall portion of each pixel unit; performing a second step of etching the continuous passivation layer, the first semiconductor layer, the reflector layer and the bonding structure between adjacent pixel units to complete the preparation of the pixel isolation and the reflective cavity structure.

[0104] The second etching method includes any one of the following: IBE or NBE.

[0105] Specifically, a sidewall process is used to etch the sidewall structure on the upper surface of the pixel unit and between the pixel units, and only the sidewall structure of the sidewall portion of each pixel unit is retained to complete the etching of the sidewall structure, and then an etching scheme such as IBE or NBE is used to prepare a reflective cavity structure connected to the sidewall of the bottom layer of the pixel unit such as the first semiconductor layer, and this reflective cavity structure can achieve electrical enhancement. It can be understood that due to the above-mentioned preparation process, the specific material of the reflective cavity structure is the same as the metal part of the passivation layer, the first semiconductor layer, the reflector layer and the bonding structure during the second etching step.

[0106] Furthermore, after completing the second etching step, the following steps are also included: the isolated pixel units are filled with an insulating medium on the entire surface to prepare a first insulating layer; or, the isolated pixel units are covered with a film layer of an insulating medium to prepare a second insulating layer.

[0107] Specifically, an insulating layer is prepared on the device after pixel isolation is completed. The insulating layer can be filled on the entire surface to form a Figure 8 The first insulating layer 251 shown in the figure may also be covered by a non-filling film layer to form a Fig. 9 The second insulating layer 252 is shown. The first insulating layer 251 or the second insulating layer 252 includes one or a combination of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, and the present application does not impose any limitation on this.

[0108] Step S4: preparing a second conductive electrode on the top of the pixel unit after pixel isolation, and the second conductive electrode is electrically connected to the second electrode contact in the driving wafer.

[0109] In a possible implementation, step S4 may specifically include: making an opening at the top of the pixel unit to expose the second semiconductor layer of the pixel unit; depositing a conductive film on the top of each pixel unit to form a second conductive electrode, and the second conductive electrode connects the second semiconductor layers exposed by each pixel unit.

[0110] Specifically, Fig.10 As shown, an opening is prepared for contacting the second conductive electrode 280 at the top of the pixel unit 210, and the second conductive electrode 280 can be formed on the outer surface of each pixel unit 210 by coating. Figure 8 The structure after preparing the second conductive electrode 280 can be as follows Fig.11 shown.

[0111] In a possible implementation, the following steps are also included: preparing a first metal grid structure in the first insulating layer between adjacent pixel units, the top of the first metal grid structure is in contact with the second conductive electrode, and the bottom of the first metal grid structure is higher than the surface of the driving wafer.

[0112] Specifically, Fig.12 As shown, in order to achieve electrical enhancement of the second conductive electrode 280, a first metal grid structure 261 is prepared below the second conductive electrode 280. The first metal grid structure 261 may be an alloy or a laminate of a metal material, such as an alloy of Al, AlCu, AlNi, etc., an Al / TiN, AlCu / TiN laminate, a laminate of metals such as Al / Ni / Ti / Au, or an alloy or a laminate of metals such as Au / Ge / Ni / Au.

[0113] In a possible implementation, the method further includes the following step: preparing a connected metal filling structure between the second conductive electrode and the second electrode contact.

[0114] Specifically, Fig.12 or Fig.13 As shown, in order to achieve electrical connection of the second conductive electrode 280, metal filling is performed between the second conductive electrode 280 and the second electrode contact 120 in the driving wafer 100 to prepare a metal filling structure 262 connecting the two. The metal filling structure 262 is made of a metal material, such as Al / Ti / Cu, or Al / TiN / Cu, or Al / Ni / Cu, or Al / NiV / Cu, or Al / Ta / Cu, or Al / TaN / Cu, and the above Cu can also be replaced by W, and there can be no Al in the above structure. The present application does not limit the specific type of the metal material.

[0115] It is understandable that the number of the second electrode contact 120 may be one or more. Fig.14 or Fig.15 In addition to the second electrode contacts 120 outside the pixel area, one or more second electrode contacts 120 are also set in the pixel area. The second electrode contacts 120 in the pixel area can directly contact the second conductive electrode 280, or a metal filling structure 262 connected to the second conductive electrode 280 can be set for each second electrode contact 120, and the second electrode contact 120 is in contact with the second conductive electrode 280 through the metal filling structure 262.

[0116] In a possible implementation manner, the following step is further included: during the preparation process of the pixel unit, a redundant structure is simultaneously prepared around the outer periphery of the pixel unit.

[0117] Among them, the redundant structure is a structure prepared synchronously with the preparation of the pixel unit. Unlike the pixel unit, the redundant structure does not need to contact the first electrode contact in the driving wafer, and the size of the redundant structure may be different from the size of the pixel unit.

[0118] Specifically, Figures 2 to 15As shown, between the peripheral common cathode and the pixel area, some compound pixels are retained to form a redundant structure 270, forming a higher filling density, improving some steps and density requirements of subsequent semiconductor processes, such as glue tailing, chemical mechanical polishing (CMP), etc. The redundant structure 270 can be a pixel array redundancy or a compound dam structure surrounding the periphery of the pixel array, and the distribution width of the redundant structure 270 is not less than the minimum value of the pixel unit size in the pixel area. Exemplarily, the distribution width of the redundant structure 270 is not less than 10um.

[0119] In a possible implementation manner, the following step is further included: preparing a second metal grid structure on top of the second conductive electrode.

[0120] Specifically, in order to achieve electrical enhancement of the second conductive electrode, a second metal grid structure is prepared above the second conductive electrode. The second metal grid structure may be an alloy or laminate of a metal material, such as an alloy of Al, AlCu, AlNi, etc., an Al / TiN, AlCu / TiN laminate, a laminate of metals such as Al / Ni / Ti / Au, or an alloy or laminate of metals such as Au / Ge / Ni / Au.

[0121] In a possible implementation, optical enhancement structures such as microlenses and metasurfaces are prepared on the final structure to achieve optical enhancement or optical alignment. Fig.16 , Fig.17 As shown, a microlens 290 is prepared as an optical enhancement structure. The microlens 290 can be hemispherical or semi-rugby, and redundant microlenses 290 are prepared on the periphery of the pixel array to achieve diffuse reflection on the periphery of the pixel array and reduce optical anomalies such as "ghosting" caused by excessive reflection in the optical module.

[0122] In summary, the preparation method of the optoelectronic device array structure provided in the present application is to bond and integrate the driving wafer and the compound pixel through the bonding structure on their respective surfaces to form a bonded device, and a reflector layer and a first semiconductor layer are stacked on the surface of the bonding structure corresponding to the compound pixel on the side away from the driving wafer; pixelization is performed on the compound pixel in the bonded device, and the first semiconductor layer of part of the compound pixel is etched so that the first semiconductor layer of another part is retained, so as to obtain a plurality of continuous pixel units on the first semiconductor layer, and each pixel unit is electrically connected to the first electrode contact in the driving wafer; pixel isolation is performed on the plurality of continuous pixel units, and A reflective cavity structure surrounding the pixel unit is prepared, and the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel unit; a second conductive electrode is prepared on the top of the pixel unit after the pixel is isolated, and the second conductive electrode is electrically connected to the second electrode contact in the driving wafer; so that when a bottom reflector layer is provided in the device, the electrical connection of the retained part of the first semiconductor layer and the reflective cavity structure is enhanced, and while solving the electrical connection when there is no transparent conductive film or the transparent conductive film is extremely thin and the leakage problem when the pixel is etched to the metal, the loss of light between the compound and the reflector metal is greatly reduced, thereby achieving the best brightness improvement.

[0123] In this application, if Figure 5 As shown, an optoelectronic device array intermediate structure is also provided, and the optoelectronic device array intermediate structure includes: a driving wafer 100 and a compound pixel.

[0124] The compound pixel and the driving wafer 100 are respectively provided with bonding structures 211, and the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100, and the bonding structure 211 corresponding to the compound pixel is in contact with the reflector layer 212 in the compound pixel on the side surface away from the driving wafer 100. The compound pixel includes a plurality of pixel units 210, and the plurality of pixel units 210 are continuous on the first semiconductor layer 213 in the compound pixel, and the first semiconductor layer 213 is provided on the side surface of the reflector layer 212 away from the driving wafer 100, and each pixel unit 210 is electrically connected to the first electrode contact 110 in the driving wafer 100.

[0125] The driver wafer 100 may be an active design that is a combination of one or more thin film transistors (TFT), low temperature polysilicon (LTPS), CMOS integrated circuits, high mobility transistors (HEMT), and the like.

[0126] The material of the compound pixel corresponding to the pixel unit 210 can be as follows:

[0127] Taking the Micro-LED field as an example, the materials of some compound pixels involved in the embodiments of the present application are shown in the following table. In some practical applications, the film layer of the compound will be more complicated, or there will be cross-use of materials, which typically mainly include P-type contact, N-type contact, and active layer and other functional layers sandwiched between the two:

[0128]

[0129] The contact of the compound is divided into a P-type contact and an N-type contact, which are in contact with the P-contact layer and the N-contact layer respectively. The barrier layer, the limiting layer or the waveguide layer corresponding to the P-type contact and the barrier layer, the limiting layer or the waveguide layer corresponding to the N-type contact may correspond to the first semiconductor layer 213 and the second semiconductor layer 215. In the embodiment, the P-type contact material used includes a single layer or a stack of transparent metal oxides such as ITO, IZO, and ZnO, or a single layer or a stack of metals such as Ni, Cr, Au, Ag, Zn, Be, and Al, or an alloy, or a stack of transparent metal oxides and metals; the N-type contact material used includes a single layer or a stack of transparent metal oxides such as ITO, IZO, and ZnO, or a single layer or a stack of metals such as Ni, Cr, Ti, Au, Ge, and Al, or an alloy, or a stack of transparent metal oxides and metals. The semiconductor contact layer may be deposited by CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), or the like.

[0130] In a possible implementation, a first semiconductor contact layer is provided between the reflector layer 212 and the first semiconductor layer 213, and the thickness of the first semiconductor contact layer is not greater than 70 nm. By thinning the first semiconductor layer, the influence of the excessive thickness of the first semiconductor contact layer on the optical performance of the device is avoided.

[0131] In summary, the intermediate array structure of the optoelectronic device provided in the present application includes a driving wafer and a compound pixel; bonding structures are respectively arranged on the surfaces of the compound pixel and the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the reflector layer in the compound pixel on the side surface away from the driving wafer; the compound pixel includes a plurality of pixel units, and the plurality of pixel units are continuous on the first semiconductor layer in the compound pixel, and the first semiconductor layer is arranged on the side surface of the reflector layer away from the driving wafer, and each pixel unit is electrically connected to the first electrode contact in the driving wafer; thereby, by retaining part of the first semiconductor layer, it is avoided that the pixel is over-etched to the metal during patterning etching, resulting in metal precipitation and leakage and other device failure problems.

[0132] Furthermore, based on the above-mentioned optoelectronic device array intermediate structure, a final optoelectronic device array structure can be further prepared.

[0133] In this application, if Fig.11 or Fig.14 As shown, a photoelectric device array structure is also provided, the photoelectric device array structure includes: a driving wafer 100 and compound pixels.

[0134] The compound pixel and the driving wafer 100 are provided with bonding structures 211 on their surfaces respectively, and the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100, and the bonding structure 211 corresponding to the compound pixel on one side away from the driving wafer 100 is in contact with the reflector layer 212 in the compound pixel. The compound pixel includes a plurality of pixel units 210, and each pixel unit 210 is electrically connected to the first electrode contact 110 in the driving wafer 100. The outer periphery of the pixel unit 210 is surrounded by a reflection cavity structure 220, and the reflection cavity structure 220 is connected to the outer edge of the first semiconductor layer 213, the reflector layer 212, and the bonding structure 211 in the pixel unit 210, and the first semiconductor layer 213 includes at least a stacked first partial layer and a second partial layer, the first partial layer is in contact with the reflector layer 212, and the projection of the second partial layer on the driving wafer 100 is within the projection of the first partial layer on the driving wafer 100. A second conductive electrode 280 is disposed on the top of the pixel unit 210 . The second conductive electrode 280 is electrically connected to the second electrode contact 120 in the driving wafer 100 .

[0135] Furthermore, a passivation layer 230 is attached to the outer surface of the pixel unit 210, and the reflective cavity structure 220 is also connected to the outer edge of the passivation layer 230. The passivation layer 230 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.

[0136] Furthermore, a sidewall structure 240 is provided between the reflective cavity structure 220 and the passivation layer 230 on the sidewall surface of the pixel unit 210. The sidewall structure 240 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.

[0137] Further, such as Fig.11 As shown, the entire outer periphery of the pixel unit 210 is filled with a first insulating layer 251; or Fig.14 As shown, the outer periphery of the pixel unit 210 is covered with a thin film-style second insulating layer 252. The first insulating layer 251 or the second insulating layer 252 includes one or a combination of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, which is not limited in the present application.

[0138] Further, such as Fig.12 As shown, the first insulating layer 251 is filled with a first metal grid structure 261, the top of the first metal grid structure 261 is in contact with the second conductive electrode 280, and the bottom of the first metal grid structure 261 is higher than the surface of the driving wafer 100, so that the electrical connection is enhanced through the first metal grid structure 261. The first metal grid structure 261 can be an alloy or a laminate of a metal material, such as an alloy of Al, AlCu, AlNi, etc., an Al / TiN, AlCu / TiN laminate, a laminate of metals such as Al / Ni / Ti / Au, or an alloy or a laminate of metals such as Au / Ge / Ni / Au.

[0139] Further, such as Fig.13 As shown, a metal filling structure 262 is provided between the second conductive electrode 280 and the second electrode contact 120, and the electrical connection is enhanced by the metal filling structure 262. The metal filling structure 262 is made of a metal material, such as Al / Ti / Cu, or Al / TiN / Cu, or Al / Ni / Cu, or Al / NiV / Cu, or Al / Ta / Cu, or Al / TaN / Cu, wherein Cu can be replaced by W, and Al can be absent in the above structure, and the present application does not limit the specific type of the metal material.

[0140] Furthermore, a second metal grid structure is disposed on the top of the second conductive electrode 280. The second metal grid structure may be an alloy or a laminate of a metal material, such as an alloy of Al, AlCu, AlNi, an Al / TiN, AlCu / TiN laminate, an Al / Ni / Ti / Au laminate, or an Au / Ge / Ni / Au alloy or laminate.

[0141] Further, such as Fig.14As shown, at least one second electrode contact 120 is disposed inside the pixel region of the driving wafer 100 to enhance electrical connection.

[0142] Furthermore, a first semiconductor contact layer is disposed between the reflector layer 212 and the first semiconductor layer 213. To prevent the first semiconductor contact layer from being too thick, the thickness of the first semiconductor contact layer is not greater than 70 nm.

[0143] Furthermore, a redundant structure 270 is disposed around the outer periphery of the pixel unit 210. In addition, the distribution width of the redundant structure 270 is not less than the minimum value of the pixel unit size in the pixel area.

[0144] In summary, the optoelectronic device array structure provided by the present application includes a driving wafer and a compound pixel; bonding structures are respectively arranged on the surfaces of the compound pixel and the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the reflector layer in the compound pixel on the side surface away from the driving wafer; the compound pixel includes a plurality of pixel units, each of which is electrically connected to the first electrode contact in the driving wafer; the outer periphery of the pixel unit is surrounded by a reflective cavity structure, the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel unit, and the first semiconductor layer is electrically connected to the reflector layer. The body layer at least includes a first partial layer and a second partial layer stacked together, the first partial layer is in contact with the reflector layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer; a second conductive electrode is arranged on the top of the pixel unit, and the second conductive electrode forms an electrical connection with a second electrode contact in the driving wafer; thus, when a bottom reflector layer is arranged in the device, the electrical connection of the retained part of the first semiconductor layer and the reflective cavity structure is enhanced, and while solving the electrical connection when there is no transparent conductive film or the transparent conductive film is extremely thin and the leakage problem when the pixel is etched to the metal, the loss of light between the compound and the reflector metal is greatly reduced, thereby achieving the best brightness improvement.

[0145] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0146] It should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an optoelectronic device array structure, characterized in that: The method comprises: The driving wafer and the compound pixel are bonded and integrated through the bonding structures on their respective surfaces to form a bonded device, wherein a reflector layer and a first semiconductor layer are stacked on a surface of the bonding structure corresponding to the compound pixel on a side away from the driving wafer; Pixelating the compound pixel in the bonded device, etching a portion of the first semiconductor layer in the compound pixel so that another portion of the first semiconductor layer remains, and obtaining a plurality of continuous pixel units on the first semiconductor layer, each of the pixel units being electrically connected to a first electrode contact in the driving wafer; Performing pixel isolation on a plurality of continuous pixel units, and preparing a reflective cavity structure surrounding the pixel units, wherein the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel units; A second conductive electrode is prepared on the top of the pixel unit after pixel isolation, and the second conductive electrode is electrically connected to the second electrode contact in the driving wafer.

2. The method according to claim 1, characterized in that Before performing pixel isolation on a plurality of consecutive pixel units, the method further includes: Depositing an insulating medium on the outer surfaces of a plurality of consecutive pixel units to prepare a passivation layer; An insulating dielectric is deposited again on the surface of the passivation layer to prepare a sidewall structure.

3. The method according to claim 2, characterized in that The pixel isolation of a plurality of continuous pixel units and the preparation of a reflective cavity structure surrounding the pixel units include: Performing a first step of etching on the sidewall structure to retain the sidewall structure of the sidewall portion of each pixel unit; The continuous passivation layer, the first semiconductor layer, the reflector layer and the bonding structure between adjacent pixel units are etched in a second step to complete the pixel isolation and the preparation of the reflective cavity structure.

4. The method according to claim 3, characterized in that The method used in the second step of etching includes any one of the following: IBE or NBE.

5. The method according to claim 3, characterized in that: After completing the second etching step, the method further includes: Filling the entire surface of the isolated pixel unit with an insulating medium to prepare a first insulating layer; or, The isolated pixel units are covered with a film layer of an insulating medium to prepare a second insulating layer.

6. The method according to claim 5, characterized in that After the first insulating layer is prepared and before the second conductive electrode is prepared, the method further includes: A first metal grid structure is prepared in the first insulating layer between adjacent pixel units, the top of the first metal grid structure is in contact with the second conductive electrode, and the bottom of the first metal grid structure is higher than the surface of the driving wafer.

7. The method according to claim 1, characterized in that The second conductive electrode is prepared on the top of the pixel unit after pixel isolation, comprising: An opening is made at the top of the pixel unit to expose the second semiconductor layer of the pixel unit; A conductive film is deposited on the top of each pixel unit to form the second conductive electrode, and the second conductive electrode connects the second semiconductor layer exposed by each pixel unit.

8. The method according to claim 7, characterized in that Before forming the second conductive electrode, the method further includes: A connected metal filling structure is prepared between the second conductive electrode and the second electrode contact.

9. The method according to claim 1, characterized in that: In the process of preparing the pixel unit, the method further includes: A redundant structure is simultaneously prepared around the outer periphery of the pixel unit.

10. The method according to claim 1, characterized in that The method further comprises: A second metal grid structure is formed on top of the second conductive electrode.

11. The method according to claim 1, characterized in that: The preparation process of the compound pixel includes: The reflector layer is directly formed on the first semiconductor layer of the compound pixel.

12. An optoelectronic device array structure, characterized in that: The optoelectronic device array structure includes: a driving wafer and compound pixels; The compound pixel and the driving wafer are respectively provided with bonding structures, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the reflector layer in the compound pixel; The compound pixel includes a plurality of mutually isolated pixel units, each of which is electrically connected to a first electrode contact in the driving wafer; The outer periphery of the pixel unit is surrounded by a reflective cavity structure, the reflective cavity structure is connected to the first semiconductor layer, the reflector layer, and the outer edge of the bonding structure in the pixel unit, and the first semiconductor layer at least includes a stacked first partial layer and a second partial layer, the first partial layer is in contact with the reflector layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer; A second conductive electrode is disposed on the top of the pixel unit, and the second conductive electrode is electrically connected to a second electrode contact in the driving wafer.

13. The optoelectronic device array structure according to claim 12, characterized in that: A passivation layer is attached to the outer surface of the pixel unit; The reflective cavity structure is also connected to the outer edge of the passivation layer.

14. The optoelectronic device array structure according to claim 13, characterized in that: A sidewall structure is provided between the reflective cavity structure and the passivation layer on the sidewall surface of the pixel unit.

15. The optoelectronic device array structure according to claim 12, characterized in that: The entire outer periphery of the pixel unit is filled with a first insulating layer; or, The outer periphery of the pixel unit is covered with a second insulating layer in a thin film style.

16. The optoelectronic device array structure according to claim 15, characterized in that: The first insulating layer is filled with a first metal grid structure, the top of the first metal grid structure is in contact with the second conductive electrode, and the bottom of the first metal grid structure is higher than the surface of the driving wafer.

17. The optoelectronic device array structure according to claim 12, characterized in that: A interconnected metal filling structure is provided between the second conductive electrode and the second electrode contact.

18. The optoelectronic device array structure according to claim 12, characterized in that: A second metal grid structure is also disposed on the top of the second conductive electrode.

19. The optoelectronic device array structure according to claim 12, characterized in that: At least one second electrode contact is disposed inside the pixel area of ​​the driving wafer.

20. The optoelectronic device array structure according to claim 12, characterized in that: A first semiconductor contact layer is disposed between the reflector layer and the first semiconductor layer.

21. The optoelectronic device array structure according to claim 20, characterized in that: The thickness of the first semiconductor contact layer is no more than 70 nm.

22. The optoelectronic device array structure according to claim 12, characterized in that: A redundant structure is arranged around the outer periphery of the pixel unit.

23. The optoelectronic device array structure according to claim 22, characterized in that: The distribution width of the redundant structure is not less than the minimum value of the pixel unit size in the pixel area.

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