Arithmetic square root approximate calculation device and calculation method based on random calculation

Abstract

The present invention proposes a device and method for approximating arithmetic square roots based on random computation, belonging to the field of integrated circuit design. The device comprises a random sequence generation unit and a square root calculation unit; the random sequence generation unit includes a linear feedback shift register and a comparator; the square root calculation unit includes a square root settlement unit, an uncorrelated median generation unit, a half-value scaling unit, and a data coupling unit. The device for approximating arithmetic square roots based on random computation, described in the present application, achieves high computational accuracy when performing square root calculations on a 3- to 10-digit binary number X, with low average root mean square error and average mean absolute error.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design and relates to an arithmetic square root approximate calculation device and calculation method based on random calculation. Background Art

[0002] In recent years, stochastic computing, as an emerging computing method, has garnered increasing attention. Stochastic computing utilizes random sequences generated by random number generators to represent and process digital information. By converting complex mathematical operations (such as square roots) into simple logic gate operations, the computational process can be simplified. The core advantages of stochastic computing lie in its low-cost computational form and high tolerance to soft errors, enabling significant resource savings and high efficiency in implementing complex functions.

[0003] In modern computing and signal processing, square root calculation is a fundamental and important task, widely used in image processing, digital signal analysis, and various scientific calculations. Traditional square root calculation methods typically require complex logic circuits to meet square root calculation requirements. To this end, this application has developed an arithmetic square root approximation calculation device and calculation method based on random calculation using simple logic circuits. Summary of the Invention

[0004] In response to the above-mentioned defects and deficiencies in the prior art, the present application proposes an arithmetic square root approximate calculation device and calculation method based on random calculation.

[0005] In order to achieve the above-mentioned object, the present invention adopts the following technical solutions:

[0006] An arithmetic square root approximate calculation device based on random calculation includes a random sequence generation unit and a square root calculation unit; wherein the random sequence generation unit includes a linear feedback shift register and a comparator; the square root calculation unit includes a square root settlement unit, a non-correlated median generation unit, a half-value scaling unit and a data coupling unit;

[0007] In the present application, one input end of the comparator serves as the input end of the entire arithmetic square root approximate calculation device based on random calculation, the other input end of the comparator is connected to the output end of the linear feedback shift register, and the output end of the comparator is connected to one input end of the square root settlement unit;

[0008] The output end of the square root settlement unit is also connected to the input end of the non-correlated median generation unit and one of the input ends of the half-value scaling unit, the output end of the non-correlated median generation unit is connected to the other input end of the half-value scaling unit and the input end K of the data coupling unit, the output end of the half-value scaling unit is connected to the input end J of the data coupling unit, and the output end Q of the data coupling unit is connected to the other input end of the square root settlement unit; the probability value of the occurrence of the bit "1" in the random sequence composed of the bits output by the output end of the square root settlement unit in all clock cycles according to the time sequence is the square root calculation result of the arithmetic square root approximation calculation device based on random calculation described in this application

[0009] Preferably, the square root settlement unit is an "OR" logic gate.

[0010] Preferably, the data coupling unit is a JK flip-flop.

[0011] Preferably, the half-value scaling unit is an AND logic gate.

[0012] Preferably, the non-correlated median generating unit is a T flip-flop.

[0013] A square root calculation method using the arithmetic square root approximation calculation device based on random calculation comprises the following steps:

[0014] S1. Perform multiple charge and discharge operations on the linear feedback shift register in the random sequence generation unit so that the register has an initial state that is not entirely "0"; perform one charge and discharge operation on the non-correlated median generation unit and the data coupling unit respectively so that the non-correlated median generation unit and the data coupling unit respectively have their own initial bits;

[0015] S2. Input an N-bit binary number X from the input end of the entire random calculation-based arithmetic square root approximation calculation device, where the N-bit binary number X is the data to be squared, and N is the same as the number of bits of the linear feedback shift register; a comparator compares the internal state of the linear feedback shift register with the binary number X; wherein, in the first clock cycle, the internal state of the linear feedback shift register refers to the initial state obtained by the linear feedback shift register through multiple charge and discharge cycles in step S1;

[0016] S3. Using the square root settlement unit, perform an OR logic operation on the bit output by the comparator and the bit output by the data coupling unit; wherein, in the first clock cycle, the bit output by the data coupling unit refers to the initial bit obtained by the data coupling unit through a single charge and discharge in step S1;

[0017] S4. Using the non-correlated median generation unit, perform an exclusive OR logic operation on the bit output by the square root settlement unit and the current internal state of the non-correlated median generation unit; wherein, in the first clock cycle, the bit output by the non-correlated median generation unit refers to the initial bit obtained by the non-correlated median generation unit through a single charge and discharge operation in step S1;

[0018] S5. Using the half-value scaling unit, perform an AND logic operation on the bits output by the non-correlated median generation unit and the bits output by the square root settlement unit;

[0019] S6, using the data coupling unit to couple the bits output by the half-value scaling unit and the bits output by the uncorrelated median generation unit, and transmit the calculation results to the square root settlement unit to complete the calculation process of one clock cycle; then, according to the clock signal, the internal state of the linear feedback shift register is shifted and updated to obtain a new state different from the previous state; then, the calculation process described in steps S2 to S6 is repeated. N -2 times to get the final calculation result. In this application, a total of 2 N -1 clock cycle calculation process.

[0020] Preferably, in step S2, if the binary number X is greater than the internal state of the linear feedback shift register, the comparator outputs a bit "1", and if the binary number X is less than the internal state of the linear feedback shift register, the comparator outputs a bit "0".

[0021] Preferably, in step S4, the bits output by the uncorrelated median generating unit in all clock cycles form a random sequence in time sequence, the probability value of the occurrence of bit "1" in the random sequence is 0.5, and the random sequence is uncorrelated with the input of the uncorrelated median generating unit; the input of the uncorrelated median generating unit refers to another random sequence formed by the bits input by the uncorrelated median generating unit in all clock cycles in time sequence.

[0022] Preferably, in step S4, the correlation represents the degree of overlap of the positions of the bit "1" in the two random sequences. When the positions of the bit "1" in the two random sequences completely overlap, the correlation is maximum and is regarded as 1. When the value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences is equal to the product of the values ​​represented by the above two random sequences, it is regarded as no correlation, that is, the correlation is 0. The correlation value calculation method of the present application is as follows: a) calculating the absolute value of the difference between the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences and the product of the numerical values ​​represented by the above two random sequences; b) calculating the difference between the minimum numerical value among the numerical values ​​represented by the above two random sequences and the product of the numerical values ​​represented by the above two random sequences; c) calculating the ratio between the absolute value of the difference obtained in step a) and the difference calculated in step b); this ratio is the correlation value; when the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences is equal to the product of the numerical values ​​represented by the above two random sequences, the difference between the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences and the product of the numerical values ​​represented by the above two random sequences is 0, and therefore, the correlation is 0.

[0023] The correlation between the two random sequences is the ratio of the difference between the result of the bitwise AND logic operation and the product of the "1" probability values ​​represented by the two and the minimum value of the two.

[0024] Preferably, the non-correlated median generation unit uses a T flip-flop to implement the function, and the state transition characteristic formula of the T flip-flop is shown in formula (1):

[0025]

[0026] In formula (1), Indicates the next state of the T flip-flop, T represents the current input bit, Indicates the current state of the T flip-flop.

[0027] Preferably, the probability value PT of the bit "1" appearing in the random sequence composed of the bits output by the T flip-flop in all clock cycles according to the time sequence is expressed as follows:

[0028]

[0029] In formula (2), PT represents the probability value of the bit "1" appearing in the random sequence of bits output by the uncorrelated median generation unit (i.e., the T flip-flop) in all clock cycles according to the time sequence. The probability value represented by PT is also the value represented by the random sequence of bits output by the T flip-flop in all clock cycles according to the time sequence.

[0030] Preferably, the half-value scaling unit is used to perform an AND logic operation on the bits output by the uncorrelated median generation unit and the bits output by the square root settlement unit, and output a bit; the half-value scaling unit outputs a bit in each clock cycle, and the relationship between the probability value PJ of the bit "1" appearing in the random sequence composed of the bits output in all clock cycles according to the time sequence, PT and PO is as shown in formula (3):

[0031]

[0032] In formula (3), PJ represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the half-value scaling unit in all clock cycles according to the time sequence, and also represents the probability value of the bit "1" appearing in the random sequence composed of the bits input by the input terminal J of the data coupling unit in all clock cycles according to the time sequence; PT represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the uncorrelated median generation unit (i.e., T flip-flop) in all clock cycles according to the time sequence; PO represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence.

[0033] Preferably, the probability value PK of the bit "1" appearing in the random sequence composed of the bits input at the input terminal K of the data coupling unit in all clock cycles according to the time sequence is as shown in formula (4):

[0034]

[0035] In formula (4), PK represents the probability value of the bit "1" appearing in the random sequence composed of the bits input by the input terminal K of the data coupling unit in all clock cycles according to the time sequence, that is, the value represented by this random sequence; PT represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the uncorrelated median generation unit (i.e., T flip-flop) in all clock cycles according to the time sequence.

[0036] Preferably, the data coupling unit uses a JK trigger to implement the function, and the state transition formula of the JK trigger is shown in formula (5):

[0037]

[0038] In formula (5), Indicates the next state of the JK flip-flop, J represents the bit currently input to the JK flip-flop input J, and K represents the bit currently input to the JK flip-flop input K. Indicates the current state of the JK flip-flop, and Indicates the state of the JK flip-flop in two different clock cycles.

[0039] Preferably, the relationship between the probability value PQ of the occurrence of bit "1" in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence and the probability value PO of the occurrence of bit "1" in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence is as shown in formula (7):

[0040]

[0041] In formula (7), PQ represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence; PO represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence.

[0042] Preferably, the probability value PO of the bit "1" appearing in the random sequence composed of bits output by the square root settlement unit in all clock cycles according to the time sequence is calculated using formula (8):

[0043] PX+PQ-PX×PQ=PO (8)

[0044] In formula (8), PX represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the comparator in all clock cycles according to the time sequence; PQ represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence.

[0045] Compared with the prior art, the present invention has the following advantages:

[0046] In the arithmetic square root approximation calculation device based on random calculation described in the present application, the probability value PT of the bit "1" appearing in the random sequence composed of the bits output by the uncorrelated median unit (i.e., T trigger) in all clock cycles according to the time sequence is 1 / 2, and the random sequence composed of the bits output by the uncorrelated median unit in all clock cycles according to the time sequence and the input of the uncorrelated median unit (the input of the uncorrelated median unit refers to the random sequence composed of the bits input by the uncorrelated median unit in all clock cycles according to the time sequence) are uncorrelated; the half-value scaling unit is used to perform "AND" on the bits output by the uncorrelated median generation unit and the bits output by the square root settlement unit. Logical operation, and output a bit, the half-value scaling unit will output a bit in each clock cycle, the bits output in all clock cycles in accordance with the random sequence composed of the time sequence, the probability value PJ of the bit "1" appearing is equal to PO / 2; the data coupling unit couples the bits output by the half-value scaling unit and the bits output by the uncorrelated median generation unit for calculation, and the probability value PQ of the bit "1" appearing in the random sequence composed of the bits output at the output end Q of the data coupling unit in all clock cycles in accordance with the time sequence and the probability value PO of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles in accordance with the time sequence meet The square root settlement unit performs an "OR" logic operation on the bits output by the comparator and the bits output by the data coupling unit. The probability value PO of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence is the square root calculation result of this device. By performing approximate square root calculations on binary numbers using the random calculation-based arithmetic square root approximation calculation device described in the present application, better test accuracy can be achieved. In particular, when the linear feedback shift register is a 7-bit linear feedback shift register and the input data to be squared is a 7-bit binary number X, higher accuracy can be achieved when calculating the square root using the random calculation-based arithmetic square root approximation calculation device described in the present application. Tests have shown that when the linear feedback shift register is a 7-bit linear feedback shift register and the input data to be squared is a 7-bit binary number X, when the square root is calculated using the random calculation-based arithmetic square root approximation calculation device described in the present application, the average value of the root mean square error (MAE) reaches 0.071, and the average value of the mean absolute error (MSE) reaches 0.008. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 1 is a structural diagram of the arithmetic square root approximate calculation device based on random calculation according to the present invention;

[0048] Figure 2 It is a state transition table without associated median unit (i.e. T flip-flop);

[0049] Figure 3 It is the state transition table of the data coupling unit (ie, JK flip-flop). DETAILED DESCRIPTION

[0050] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings. The description herein is only used to explain the present invention and is not intended to limit the present invention.

[0051] like Figure 1 As shown, the present invention proposes an arithmetic square root approximate calculation device based on random calculation, including a random sequence generation unit and a square root calculation unit; wherein the random sequence generation unit includes a linear feedback shift register and a comparator; the square root calculation unit includes a square root settlement unit, an uncorrelated median generation unit, a half-value scaling unit and a data coupling unit; the square root settlement unit is an "OR" logic gate, the data coupling unit is a JK flip-flop, the half-value scaling unit is an "AND" logic gate, and the uncorrelated median generation unit is a T flip-flop; the linear feedback shift register in this application is a prior art, for example, the linear feedback shift register described in this application can be the linear feedback shift register disclosed in CN 111428196 A, a non-monotonic function approximate calculation device based on random calculation;

[0052] In the present application, one input end of the comparator serves as the input end of the entire arithmetic square root approximate calculation device based on random calculation, the other input end of the comparator is connected to the output end of the linear feedback shift register, and the output end of the comparator is connected to one input end of the square root settlement unit;

[0053] The output end of the square root settlement unit is also connected to the input end of the non-correlated median generation unit and one of the input ends of the half-value scaling unit, the output end of the non-correlated median generation unit is connected to the other input end of the half-value scaling unit and the input end K of the data coupling unit, the output end of the half-value scaling unit is connected to the input end J of the data coupling unit, and the output end Q of the data coupling unit is connected to the other input end of the square root settlement unit; the probability value of the occurrence of the bit "1" in the random sequence composed of the bits output by the output end of the square root settlement unit in all clock cycles according to the time sequence is the square root calculation result of the arithmetic square root approximation calculation device based on random calculation described in this application

[0054] A square root calculation method using the arithmetic square root approximation calculation device based on random calculation comprises the following steps:

[0055] S1. Perform multiple charge and discharge operations on the linear feedback shift register in the random sequence generation unit so that the register has an initial state that is not entirely "0"; perform one charge and discharge operation on the non-correlated median generation unit and the data coupling unit respectively so that the non-correlated median generation unit and the data coupling unit respectively have their own initial bits;

[0056] S2. Input an N-bit binary number X from an input terminal of the entire random calculation-based arithmetic square root approximation calculation device (i.e., one input terminal of the comparator), where the N-bit binary number X is the data to be squared, and N is the same as the number of bits of the linear feedback shift register. The comparator compares the internal state of the linear feedback shift register with the binary number X. If the binary number X is greater than the internal state of the linear feedback shift register, the comparator outputs a bit "1", and if the binary number X is less than the internal state of the linear feedback shift register, the comparator outputs a bit "0". In the first clock cycle, the internal state of the linear feedback shift register refers to the initial state of the linear feedback shift register obtained by multiple charge and discharge cycles in step S1.

[0057] In the present application, the comparator compares the internal state of the linear feedback shift register with the binary number X in each clock cycle. If the binary number X is greater than the internal state of the linear feedback shift register, the comparator outputs a bit "1". If the binary number X is less than the internal state of the linear feedback shift register, the comparator outputs a bit "0". After all clock cycles are completed, the bits output by the comparator in all clock cycles form a random sequence in a time sequence. The probability value of the bit "1" in the random sequence is the same as the value represented by the binary number X. Since the probability value of the bit "1" in the random sequence is the same as the value represented by the binary number X, the random sequence can be used to represent the binary number X to be squared.

[0058] S3. Using the square root settlement unit, perform an OR logic operation on the bit output by the comparator and the bit output by the data coupling unit; wherein, in the first clock cycle, the bit output by the data coupling unit refers to the initial bit obtained by the data coupling unit through a single charge and discharge in step S1;

[0059] In step S3 of the present application, the data coupling unit outputs a bit in each clock cycle. After all clock cycles are completed, the bits output by the data coupling unit in all clock cycles form a random sequence according to the time sequence. The probability value of the bit "1" appearing in the random sequence is the square root calculation result of the binary number X.

[0060] S4. Using the non-correlated median generation unit, perform an exclusive OR logic operation on the bit output by the square root settlement unit and the current internal state of the non-correlated median generation unit; wherein the bit output by the non-correlated median generation unit refers to the initial bit obtained by the non-correlated median generation unit through a single charge and discharge operation in step S1;

[0061] In the present application, the uncorrelated median generating unit outputs a bit in each clock cycle. After all the clock cycles are over, the bits output by the uncorrelated median generating unit in all the clock cycles form a random sequence in time sequence. The random sequence has no correlation with the input of the uncorrelated median generating unit, and the probability value of the bit "1" appearing in the random sequence is 0.5; wherein, the input of the uncorrelated median generating unit refers to the random sequence composed of the bits input by the uncorrelated median generating unit in all the clock cycles in time sequence; in the present application, the correlation represents the overlap of the positions of the bit "1" appearing in the two random sequences. When the positions of the bit "1" appearing in the two random sequences completely overlap, the correlation is the largest and is regarded as 1; when the value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences is equal to the value represented by the random sequence (the value represented by the random sequence is the probability value of the bit "1" appearing in the random sequence) and the above two random sequences respectively When the products of the numerical values ​​represented by the two random sequences are equal, it is considered that there is no correlation, that is, the correlation is 0; the correlation value calculation method of the present application is: a) calculating the absolute value of the difference between the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences and the product of the numerical values ​​represented by the above two random sequences; b) calculating the difference between the minimum numerical value among the numerical values ​​represented by the above two random sequences and the product of the numerical values ​​represented by the above two random sequences; c) calculating the ratio between the absolute value of the difference obtained in step a) and the difference calculated in step b); this ratio is the correlation value; when the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences is equal to the product of the numerical values ​​represented by the above two random sequences, the difference between the numerical value represented by the random sequence obtained after the bitwise "AND" logic operation of the two random sequences and the product of the numerical values ​​represented by the above two random sequences is 0, therefore, the correlation is 0.

[0062] Specifically, with respect to the non-correlated median generating unit, the bits output by the non-correlated median generating unit in all clock cycles form a random sequence according to the time sequence, and the bits input to the non-correlated median generating unit in all clock cycles form another random sequence according to the time sequence. The value represented by the random sequence obtained after a bitwise "AND" logic operation of the two random sequences is equal to the product of the values ​​respectively represented by the two random sequences. Therefore, the random sequence formed by the bits output by the non-correlated median generating unit in all clock cycles according to the time sequence and the other random sequence formed by the bits input to the non-correlated median generating unit in all clock cycles according to the time sequence are non-correlated, that is, the correlation is 0;

[0063] S5. Using the half-value scaling unit, perform an AND logic operation on the bits output by the non-correlated median generation unit and the bits output by the square root settlement unit;

[0064] In this application, the half-value scaling unit outputs a bit in each clock cycle. After all clock cycles are completed, the bits output by the half-value scaling unit in all clock cycles form a random sequence in the order of time sequence. The probability value of the occurrence of the bit "1" in the random sequence is the same as The values ​​represented are the same, that is, the value represented by the random sequence is half the value represented by the random sequence composed of the bits input to the half-value scaling unit in all clock cycles according to the time sequence;

[0065] S6. Using the data coupling unit, the bits output by the half-value scaling unit and the bits output by the uncorrelated median generation unit are coupled and calculated, and the calculation result is transmitted to the square root settlement unit, completing the calculation process of one clock cycle; then, the internal state of the linear feedback shift register is shifted and updated according to the clock signal to obtain a new state different from the previous state;

[0066] S7, repeat the calculation process 2 described in step S2 to step S6. N -2 times to get the final calculation result. In this application, a total of 2 N -1 clock cycle calculation process.

[0067] In this application, the working principles of the uncorrelated median generation unit (i.e., T flip-flop), half-value scaling unit (i.e., "AND" logic gate), data coupling unit (i.e., JK flip-flop), and square root settlement unit (i.e., "OR" logic gate) are as follows:

[0068] The uncorrelated median generation unit uses a T flip-flop to implement its function. The state transition characteristic formula of the T flip-flop is shown in formula (1):

[0069]

[0070] In formula (1), Indicates the next state of the T flip-flop, T represents the current input bit, Represents the current state of the T flip-flop; according to this characteristic formula, combined with Figure 2 , it can be seen that the input of the T flip-flop will frequently perform "exclusive OR" logic operations with its internal state, and each clock cycle will output a bit. The probability value PT of the bit "1" appearing in the random sequence composed of the bits output by the T flip-flop in all clock cycles according to the time sequence is about 1 / 2. In random calculation, it is considered to be 1 / 2. Therefore, the probability value PT of the bit "1" appearing in the random sequence composed of the bits output by the T flip-flop in all clock cycles according to the time sequence can be expressed by formula (2):

[0071]

[0072] In formula (2), PT represents the probability value of the bit "1" appearing in the random sequence of bits output by the uncorrelated median generation unit (i.e., the T flip-flop) in all clock cycles according to the time sequence. The probability value represented by PT is also the value represented by the random sequence of bits output by the T flip-flop in all clock cycles according to the time sequence.

[0073] In this application, the half-value scaling unit is used to perform an AND logic operation on the bits output by the uncorrelated median generation unit and the bits output by the square root settlement unit, and output a bit. The half-value scaling unit outputs a bit in each clock cycle. The relationship between the probability value PJ of the bit "1" appearing in the random sequence composed of the bits output in all clock cycles according to the time sequence and PT and PO is shown in formula (3):

[0074]

[0075] In formula (3), PJ represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the half-value scaling unit in all clock cycles according to the time sequence, and also represents the probability value of the bit "1" appearing in the random sequence composed of the bits input by the input terminal J of the data coupling unit in all clock cycles according to the time sequence, that is, the value represented by the random sequence; PT represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the uncorrelated median generation unit (i.e., T flip-flop) in all clock cycles according to the time sequence; PO represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence.

[0076] In the present application, since the random sequence of bits output by the uncorrelated median generation unit (i.e., T trigger) in all clock cycles according to the timing sequence is uncorrelated with the random sequence of bits input by the uncorrelated median generation unit in all clock cycles according to the timing sequence, and the random sequence of bits input by the uncorrelated median generation unit in all clock cycles according to the timing sequence is the random sequence of bits output by the square root settlement unit in all clock cycles according to the timing sequence, therefore, the random sequence of bits output by the uncorrelated median generation unit (i.e., T trigger) in all clock cycles according to the timing sequence is uncorrelated with the random sequence of bits output by the square root settlement unit in all clock cycles according to the timing sequence, therefore, the probability value PJ of the bit "1" appearing in the random sequence of bits composed of the bits output by the half-value scaling unit in all clock cycles by performing "AND" logic operations on the bits output by the uncorrelated median generation unit and the bits output by the square root settlement unit is equal to

[0077] Combine Figure 1 From the circuit structure, it can be seen that the probability value PK of the bit "1" appearing in the random sequence composed of the bits input at the input terminal K of the data coupling unit in all clock cycles according to the time sequence can be expressed as follows:

[0078]

[0079] In formula (4), PK represents the probability value of the bit "1" appearing in the random sequence composed of the bits input by the input terminal K of the data coupling unit in all clock cycles according to the time sequence, that is, the value represented by this random sequence; PT represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the uncorrelated median generation unit in all clock cycles according to the time sequence.

[0080] In this application, the data coupling unit uses a JK flip-flop to implement the function. The state transition formula of the JK flip-flop is shown in formula (5):

[0081]

[0082] In formula (5), Indicates the next state of the JK flip-flop, J represents the bit currently input to the JK flip-flop input J, and K represents the bit currently input to the JK flip-flop input K. Indicates the current state of the JK flip-flop. and Indicates the states of the JK flip-flop in two different clock cycles. From the perspective of all clock cycles, they belong to the same random sequence.

[0083] Substitute equations (3) and (4) into equation (5), and combine Figure 3, it can be known that the relationship between the probability value PQ of the occurrence of bit "1" in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles and the probability value PO of the occurrence of bit "1" in the random sequence composed of the bits output by the square root settlement unit in all clock cycles is as shown in formula (6):

[0084]

[0085] In formula (6), the probability value of the bit "1" appearing in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence is the value represented by this random sequence.

[0086] By simplifying formula (6), we can obtain the relationship between the probability value PQ of the bit "1" appearing in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence and the probability value PO of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence, as shown in formula (7):

[0087]

[0088] In formula (7), the probability value of the bit "1" appearing in the random sequence composed of the bits output by the output terminal Q of the data coupling unit in all clock cycles according to the time sequence; PO represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence.

[0089] In the present application, the square root settlement unit is used to perform an "OR" logical operation on the bits output by the comparator and the bits output by the data coupling unit, and output a bit; the probability value of the bit "1" appearing in the random sequence composed of bits output by the square root settlement unit in all clock cycles is PO.

[0090] In the present application, the relationship between the probability value PO of the occurrence of bit "1" in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence, the probability value PQ of the occurrence of bit "1" in the random sequence composed of the bits output by the data coupling unit in all clock cycles according to the time sequence, and the probability value PX of the occurrence of bit "1" in the random sequence composed of the bits output by the comparator in all clock cycles according to the time sequence is as shown in formula (8):

[0091] PX+PQ-PX×PQ=PO (8)

[0092] In formula (8), PX represents the probability value of the bit "1" appearing in the random sequence composed of the bits output by the comparator in all clock cycles according to the time sequence, that is, the value represented by this random sequence.

[0093] Substituting formula (7) into formula (8), we can obtain formula (9):

[0094]

[0095] Since the value represented by the input N-bit binary number X of the device in this application is equal to the probability value PX of the bit "1" appearing in the random sequence composed of the bits output by the comparator in all clock cycles according to the time sequence, the square root calculation method of this device can be obtained, as shown in formula (10):

[0096]

[0097] test:

[0098] This application performs numerical simulation calculations based on MATLAB software, simulates the arithmetic square root approximate calculation device based on random calculation described in this application, and simulates all data that can be represented by 3- to 10-bit linear feedback shift registers. The data are compared with the theoretical values, and the root mean square error and mean absolute error between the simulation results and the theoretical values ​​are calculated. The above process is then repeated 20,000 times, and the average value of the root mean square error (MAE) and the average value of the mean absolute error (MSE) are respectively calculated to reflect the calculation accuracy of the arithmetic square root approximate calculation device based on random calculation described in this application. The test results are shown in Table 1:

[0099] Table 1

[0100]

[0101] As can be seen from Table 1, the arithmetic square root approximation calculation device based on random calculation described in the present application can achieve high calculation accuracy when performing square root calculation on a 3- to 10-bit binary number X, and the average value of the root mean square error and the average value of the mean absolute error are both small. In particular, when the linear feedback shift register is a 7-bit linear feedback shift register and the input data to be squared is a 7-bit binary number X, the arithmetic square root approximation calculation device based on random calculation described in the present application achieves the highest accuracy when calculating the square root, with the average value of the root mean square error (MAE) reaching 0.071 and the average value of the mean absolute error (MSE) reaching 0.008.

Claims

1. A device for approximating arithmetic square roots based on random calculation, characterized in that: The apparatus comprises a random sequence generation unit and a square root calculation unit; wherein the random sequence generation unit comprises a linear feedback shift register and a comparator; the square root calculation unit comprises a square root settlement unit, an uncorrelated median generation unit, a half-value scaling unit and a data coupling unit; one input end of the comparator serves as the input end of the entire arithmetic square root approximate calculation device based on random calculation, the other input end of the comparator is connected to the output end of the linear feedback shift register, and the output end of the comparator is connected to an input end of the square root settlement unit; the output end of the square root settlement unit is also connected to the input end of the uncorrelated median generation unit and one of the input ends of the half-value scaling unit, the output end of the uncorrelated median generation unit is connected to the other input end of the half-value scaling unit and the input end K of the data coupling unit, the output end of the half-value scaling unit is connected to the input end J of the data coupling unit, and the output end Q of the data coupling unit is connected to the other input end of the square root settlement unit; the probability value of the occurrence of bit 1 in the random sequence composed of bits output by the square root settlement unit in all clock cycles according to the time sequence is the square root calculation result of the arithmetic square root approximate calculation device based on random calculation , X is the data to be squared; The bits output by the non-correlated median generating unit in all clock cycles form a random sequence according to the time sequence, and the random sequence output by the non-correlated median generating unit is uncorrelated with the input of the non-correlated median generating unit; The probability value PJ of bit 1 appearing in the random sequence composed of the bits output by the uncorrelated median generation unit and the bits output by the square root settlement unit by the half-value scaling unit in all clock cycles is equal to PO / 2; PO represents the probability value of bit 1 appearing in the random sequence composed of the bits output by the square root settlement unit in all clock cycles according to the time sequence.

2. The arithmetic square root approximate calculation device based on random calculation according to claim 1, characterized in that: The square root settlement unit is an OR logic gate.

3. The arithmetic square root approximate calculation device based on random calculation according to claim 1, characterized in that: The data coupling unit is a JK trigger.

4. The arithmetic square root approximate calculation device based on random calculation according to claim 1, characterized in that: The half-value scaling unit is an AND logic gate.

5. The arithmetic square root approximate calculation device based on random calculation according to claim 1, characterized in that: The non-correlated median generating unit is a T flip-flop.

6. A square root calculation method applied to the arithmetic square root approximation calculation device based on random calculation as claimed in claim 1, characterized in that: The square root calculation method comprises the following steps: S1. Perform multiple charge and discharge operations on the linear feedback shift register in the random sequence generation unit so that the register has an initial state that is not all zeros; perform one charge and discharge operation on the non-correlated median generation unit and the data coupling unit respectively so that the non-correlated median generation unit and the data coupling unit respectively have their own initial bits; S2. An N-bit binary number X is input from the input terminal of the entire random calculation-based arithmetic square root approximation calculation device, where N is the same as the number of bits in the linear feedback shift register; a comparator compares the internal state of the linear feedback shift register with the binary number X; wherein, in the first clock cycle, the internal state of the linear feedback shift register refers to the initial state of the linear feedback shift register; S3. Performing an OR logic operation on the bit output by the comparator and the bit output by the data coupling unit using the square root settlement unit; wherein, in the first clock cycle, the bit output by the data coupling unit refers to the initial bit obtained by the data coupling unit through a single charge and discharge in step S1; S4. Performing an exclusive-OR logic operation on the bit output by the square root settlement unit and the current internal state of the non-correlated median generation unit using the non-correlated median generation unit; wherein, in the first clock cycle, the bit output by the non-correlated median generation unit refers to the initial bit obtained by the non-correlated median generation unit through a single charge and discharge in step S1; S5. Using a half-value scaling unit, perform an AND logic operation on the bits output by the non-correlated median generation unit and the bits output by the square root settlement unit; S6. Using the data coupling unit, the bits output by the half-value scaling unit and the bits output by the uncorrelated median generation unit are coupled and calculated, and the calculation result is transmitted to the square root settlement unit, completing the calculation process of one clock cycle; then, the internal state of the linear feedback shift register is shifted and updated according to the clock signal to obtain a new state different from the previous state; S7. Repeat the calculation process from step S2 to step S6 2N-2 times to obtain the final calculation result.

7. The square root calculation method for an arithmetic square root approximation calculation device based on random calculation according to claim 6, characterized in that: In step S2, if the binary number X is greater than the internal state of the linear feedback shift register, the comparator outputs a bit 1; if the binary number X is less than the internal state of the linear feedback shift register, the comparator outputs a bit 0.

8. The square root calculation method for an arithmetic square root approximation calculation device based on random calculation according to claim 6, characterized in that: In step S4, the bits output by the non-correlated median generating unit in all clock cycles form a random sequence in time sequence, the probability value of bit 1 appearing in the random sequence output by the non-correlated median generating unit is 0.5, and the random sequence output by the non-correlated median generating unit is uncorrelated with the input of the non-correlated median generating unit; wherein the input of the non-correlated median generating unit refers to another random sequence formed by the bits input by the non-correlated median generating unit in all clock cycles in time sequence.

9. The square root calculation method for an arithmetic square root approximation calculation device based on random calculation according to claim 8, characterized in that: In step S4, the correlation represents the degree of overlap of the positions of bit 1 in the two random sequences. When the positions of bit 1 in the two random sequences completely overlap, the correlation is maximum and is considered to be 1. When the value represented by the random sequence obtained after the bitwise AND logic operation of the two random sequences is equal to the product of the values ​​represented by the two random sequences respectively, it is considered to be uncorrelated, that is, the correlation is 0.

10. The square root calculation method for an arithmetic square root approximation calculation device based on random calculation according to claim 6, characterized in that: The uncorrelated median generation unit uses a T flip-flop to implement its function. The state transition characteristic formula of the T flip-flop is shown in formula (1): （1） In formula (1), represents the next state of the current state of the T flip-flop, T represents the current input bit, Indicates the current state of the T flip-flop.

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