Data caching method and related device of on-chip logic analyzer

Abstract

This application relates to the field of data processing, and in particular to a data caching method and related device for an on-chip logic analyzer. The method includes: obtaining input data to be processed through a trigger unit; using a significant bit mask to mark corresponding data bits to be analyzed in the input data; comparing whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; controlling the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer. This method can flexibly set trigger conditions according to specific analysis requirements, meet different debugging and analysis scenarios, more accurately capture data related to target events, improve the adaptability, debugging efficiency of the logic analyzer, and the utilization rate of storage resources, and provide strong support for in-depth data analysis.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to a triggering method for a logic analyzer and related devices. Background Art

[0002] An on-chip logic analyzer (OCLA), as a dedicated tool integrated inside an integrated circuit (IC), is designed as a tool specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logical level states of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application fields.

[0003] In related technologies, an on-chip logic analyzer includes a trigger unit. The trigger unit is usually used to set capture conditions, such as specific signal combinations or edge trigger conditions. Currently, the trigger unit usually only supports fixed trigger conditions, such as level trigger, edge trigger, etc. However, in complex integrated circuits, the changes of signals are often more complex and diverse, and a single trigger condition may not meet the accurate capture requirements for specific signal changes. This may cause engineers to miss key signals during the debugging process, thereby increasing the difficulty of fault troubleshooting.

[0004] Therefore, there is an urgent need to design a technical solution to solve the technical problems existing in the trigger unit in related technologies. Summary of the Invention

[0005] This application aims at the technical problems existing in the prior art, and provides a data caching method for an on-chip logic analyzer and related devices, so as to solve the technical problems that the trigger conditions of the on-chip logic analyzer in related technologies are single and it is difficult to troubleshoot faults due to the inability to capture specific model changes.

[0006] In a first aspect, an embodiment of this application provides a data caching method for an on-chip logic analyzer. The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer. The trigger unit at least includes a custom storage array. The method includes:

[0007] Obtain input data to be processed through the trigger unit;

[0008] Use a significant bit mask to mark corresponding data bits to be analyzed in the input data;

[0009] Compare whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; wherein, the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer;

[0010] Control the data storage processes of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0011] In a second aspect, an embodiment of the present application provides an on-chip logic analyzer, which at least includes the following structures: a trigger unit and a ping-pong buffer, and the trigger unit at least includes a custom storage array; wherein,

[0012] A trigger unit, configured to obtain input data to be processed; mark corresponding data bits to be analyzed in the input data by using a significant bit mask; compare whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; wherein, the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer; control the data storage processes of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer;

[0013] A ping-pong buffer, configured to receive the target input data input through the custom storage array.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, which includes:

[0015] At least one processor, a memory, and an input / output unit;

[0016] Wherein, the memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the data caching method of the on-chip logic analyzer in the first aspect.

[0017] In a fourth aspect, a computer-readable storage medium is provided, which includes instructions that, when the instructions are run on a computer, cause the computer to execute the data caching method of the on-chip logic analyzer in the first aspect.

[0018] The present application provides a data caching method and related devices for an on-chip logic analyzer. In this technical solution, first, an input unit obtains input data to be processed. Further, a significant bit mask is used to mark corresponding data bits to be analyzed in the input data. Then, it is determined whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed. Here, the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer. Finally, according to the matching result and / or the data caching method in which the trigger unit is located, the data storage processes of a custom storage array and a ping-pong buffer are controlled, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0019] In the technical solution of the present application, through the collaborative control of the significant bit mask, the pattern mask, the custom storage array, and the ping-pong buffer, the trigger conditions can be flexibly set according to specific analysis requirements, meeting different debugging and analysis scenarios, more accurately capturing data related to target events, improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization rate of storage resources, and further providing strong support for in-depth data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic flowchart of a data caching method for an on-chip logic analyzer according to an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of the principle of a data caching method for an on-chip logic analyzer according to an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of the structure of an on-chip logic analyzer according to an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of the structure of a media device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0026] On-chip Logic Analyzer (OCLA), as a dedicated tool integrated inside an integrated circuit, is designed specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logical level status of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application fields.

[0027] In related technologies, the on-chip logic analyzer includes a trigger unit. The trigger unit is usually used to set capture conditions, such as specific signal combinations or edge trigger conditions. Currently, the trigger unit usually only supports fixed trigger conditions, such as level trigger, edge trigger, etc. However, in complex integrated circuits, the signal changes are often more complex and diverse, and a single trigger condition may not meet the accurate capture requirements for specific signal changes. This may cause engineers to miss key signals during the debugging process, thus increasing the difficulty of fault troubleshooting.

[0028] In addition, in related technologies, the trigger bits of traditional on-chip logic analyzers are usually limited and may not be able to monitor and process a large number of signal lines simultaneously. In highly integrated circuits, the number of signal lines is often very large, and the limited trigger bits will limit the monitoring range of the on-chip logic analyzer, making some important signals unable to be captured and analyzed. In related technologies, the trigger modes of traditional on-chip logic analyzers are usually relatively fixed and may not be able to adapt to the requirements in different application scenarios. For example, in some cases, engineers may need to trigger the capture according to a specific signal pattern or timing, but traditional logic analyzers may not provide such flexibility.

[0029] In summary, there is an urgent need to design a technical solution to overcome at least one of the technical problems of the trigger unit in related technologies, such as single trigger condition, limited trigger bits, and fixed trigger mode.

[0030] To solve at least one of the technical problems in related technologies, the embodiments of this application provide a data caching method and related device for an on-chip logic analyzer.

[0031] In the technical solution provided by this application, first, the trigger unit is used to obtain the input data to be processed. Then, the valid bit mask is used to mark the corresponding data bits to be analyzed in the input data. Next, it is compared whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed. Among them, the pattern mask is used to indicate the data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer. Finally, according to the matching result and / or the data caching method where the trigger unit is located, the data storage process of the custom storage array and the ping-pong buffer is controlled, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0032] In the technical solution of this application, the data bits to be analyzed are marked in the input data through the significant bit mask, which can focus on the key data part and avoid processing a large amount of irrelevant data. At the same time, the data flag bits corresponding to specific trigger events are identified through the pattern mask, enabling the user to flexibly set the trigger conditions according to specific analysis requirements to meet different debugging and analysis scenarios. It is no longer limited to fixed trigger conditions, and can capture data related to the target event more accurately, improving the adaptability and practicality of the logic analyzer. For example, in different chip designs, different pattern masks can be set to trigger data caching according to the functions of the chips and possible problems. Finally, according to the matching results and the data caching methods of the trigger units, the data storage processes of the custom storage array and the ping-pong buffer are controlled. On the one hand, it can optimize the utilization of storage resources, avoid problems such as waste or insufficiency of storage resources that may occur in traditional methods, enable more reasonable allocation and use of storage resources, and improve the overall performance and stability of the system. On the other hand, through various data caching methods (such as pre-trigger, mid-trigger, post-trigger, etc.), it can flexibly manage the required data types based on the user's debugging needs, ensure the integrity and accuracy of the data, and adapt to diverse data analysis requirements. Whether it is for chip function verification, performance evaluation, or fault troubleshooting, accurate and useful data can be obtained by setting appropriate pattern masks and data caching methods, providing strong support for in-depth data analysis.

[0033] In the technical solution of this application, through the coordinated control of the significant bit mask, pattern mask, custom storage array, and ping-pong buffer, the trigger conditions can be flexibly set according to specific analysis requirements to meet different debugging and analysis scenarios, capture data related to the target event more accurately, improve the adaptability and practicality of the logic analyzer, effectively improve the debugging efficiency and the utilization rate of storage resources, and further provide strong support for in-depth data analysis.

[0034] The data caching scheme of the on-chip logic analyzer provided by the embodiments of this application can also be executed by an electronic device, which can be a server, a server cluster, or a cloud server. The electronic device can also be a terminal device such as a mobile phone, a computer, a tablet computer, a wearable device, or a dedicated device (such as a dedicated terminal device with a data caching method system of an on-chip logic analyzer, etc.). These electronic devices can also be equipped with the chips introduced in the above embodiments. Or, these electronic devices can also install a service program for executing the data caching scheme of the on-chip logic analyzer.

[0035] Figure 1 It is a schematic flowchart of a data caching method for an on-chip logic analyzer provided by an embodiment of this application, as Figure 1As shown in the figure, the method includes the following steps:

[0036] Step 101: Obtain the input data to be processed through a trigger unit;

[0037] Step 102: Use a significant bit mask to mark the corresponding data bits to be analyzed in the input data;

[0038] Step 103: Compare whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed;

[0039] Step 104: Control the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching mode where the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0040] The embodiment of the present application is applied to an on-chip logic analyzer. The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer. Further, the trigger unit at least includes a custom storage array. Specifically, the trigger unit filters out irrelevant data bits from the input data through a significant bit mask, reduces the amount of data to be processed subsequently, and improves the analysis pertinence. For example, for a wide-bit data, when only some key bits are concerned, this module can be used to achieve this. The custom storage array is used to temporarily store the data processed by the significant bit mask. Further optionally, this array works according to the first-in first-out principle, can cache data to a certain extent, wait for comparison with the pattern mask and subsequent processing, and prevent data loss or untimely processing. The trigger unit stores the data flag bits corresponding to specific trigger events through the pattern mask, compares them with the data temporarily stored in the custom storage array, determines whether the trigger conditions are met, and then generates a control signal to control the ping-pong buffer. Under the action of the control signal generated by the comparison result of the pattern mask in the trigger unit, the ping-pong buffer stores the target input data that meets the caching requirements, playing the role of data caching and transfer, and ensuring that the data can be transmitted to the host computer orderly and stably. The host computer receives the data from the ping-pong buffer and performs subsequent analysis, display and other operations to help the user intuitively understand the data situation collected by the on-chip logic analyzer.

[0041] See Figure 2 In the structural schematic diagram of the on-chip logic analysis shown in the figure, the input data first enters the significant bit mask module in the trigger logic unit (i.e., the trigger unit), and the processed data flows into the FIFO (i.e., the custom storage array). The input data in the FIFO will be compared with the pattern mask, and the data storage of the ping-pong buffer is controlled according to the control signal generated by the comparison result. Further, the ping-pong buffer is connected to the host computer, and the data stored in the ping-pong buffer is used as the basis for data analysis by the host computer.

[0042] Further optionally, the custom storage array and the ping-pong buffer in the trigger unit are set as a multi-level first-in first-out (FIFO) storage array. The FIFO depth and the number of layers corresponding to the custom storage array and the ping-pong buffer can both be dynamically configured based on the trigger mode in which the trigger unit is located.

[0043] Specifically, the custom storage array and the ping-pong buffer can utilize the storage resources in an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), such as block RAM (BRAM) or distributed RAM (DRAM), to construct the FIFO. In an FPGA, the internal FIFO IP core can be directly called, and its depth (the number of stored data) and width (the bit width of each data) can be defined by setting parameters. For example, if 32-bit data needs to be stored and the FIFO depth is expected to be 1024, the corresponding settings can be made in the IP core configuration interface. In ASIC design, a dedicated circuit structure needs to be designed according to the storage requirements to implement the FIFO function, including an address generator, read-write control logic, etc. The working principle can be that data is written into the FIFO in the order of entry, and when reading, it is also read according to the first-in first-out principle. When new data arrives, it is written into the FIFO when the write enable signal is valid; when data needs to be read, it is read out from the FIFO when the read enable signal is valid. At the same time, there will also be full and empty signals to indicate whether the FIFO is full or empty, to avoid data overflow or read-empty errors. In the on-chip logic analyzer, the FIFO can be used to temporarily store the data after the valid bit mask processing, waiting to be compared with the pattern mask.

[0044] In another example, the custom storage array and the ping-pong buffer can be implemented based on SRAM (Static Random Access Memory). Specifically, the SRAM chip is connected to the control logic circuit of the on-chip logic analyzer, including address lines, data lines, and control lines. The address lines are used to specify the address of the storage unit to be accessed, the data lines are used to transmit data, and the control lines include signals such as read enable and write enable to control the read and write operations of the SRAM. In FPGA design, the SRAM chip can be interfaced through the I / O pins of the FPGA, and the corresponding control logic code can be written; in ASIC design, the SRAM interface circuit needs to be integrated into the chip interior.

[0045] Based on the above structure, by controlling the logic circuit to send addresses and read / write control signals to the SRAM, random read and write operations of data are realized. When writing data, the data and the corresponding address are sent to the SRAM, and the data is stored in the specified address unit when the write enable signal is valid; when reading data, the address and the read enable signal are sent, and the data is read from the specified address unit. This method can flexibly access any position in the storage array according to needs, and is suitable for scenarios that require random storage and reading of data, such as recording specific data before and after triggering in a custom storage array.

[0046] In another example, the custom storage array and the ping-pong buffer can be implemented based on a register file. Specifically, it consists of multiple registers, and each register can store data with a certain bit width. The size of the register file and the bit width of each register can be customized according to specific requirements. For example, if 8 32-bit data need to be stored, a register file containing 8 32-bit registers can be constructed. In FPGA design, the structure and operation logic of the register file can be directly described using HDL (Hardware Description Language, such as Verilog or VHDL); in ASIC design, it is implemented by designing a dedicated register circuit.

[0047] Based on the above structure, the registers in the register file are read and written by controlling the logic circuit. Each register usually has independent read and write enable signals. When the write enable signal of a certain register is valid, data can be written into the register; when the read enable signal is valid, data can be read from the register. The register file has a relatively fast read and write speed and is suitable for scenarios with high requirements for data storage and access speed, such as quickly storing and processing temporary data in the trigger logic unit.

[0048] Furthermore, in the application scenario of the on-chip logic analyzer, the custom storage array and the ping-pong buffer in the trigger unit are set as multi-level first-in-first-out storage arrays (FIFOs), and their respective corresponding FIFO depths and the number of levels can be dynamically configured based on the trigger mode in which the trigger unit is located. The following is a detailed introduction.

[0049] The multi-level FIFO in the custom storage array is used to temporarily store the data after being processed by the valid bit mask. Each level of the FIFO can be regarded as an independent data storage queue, and the data flows through each level of the FIFO in turn according to the first-in-first-out principle. This multi-level structure can increase the data caching ability and provide more intermediate stages for data processing, facilitating complex pattern detection and data processing operations.

[0050] The multi-level FIFO of the ping-pong buffer is mainly used to store target input data that meets the caching requirements. It works in coordination with the FIFO of the custom storage array. When the data in the custom storage array meets the trigger condition, the data will be transferred to the FIFO of the ping-pong buffer for storage. The multi-level structure of the ping-pong buffer can achieve continuous data storage and processing, improving the efficiency and stability of data storage.

[0051] Based on the aforementioned multi-level structure, the FIFO depth configuration in the pre-trigger mode can be to store the data for a period of time before the trigger event occurs. Therefore, the FIFO depths of the custom storage array and the ping-pong buffer need to be configured according to the length of the historical data to be traced. For example, if you want to record the data of 100 clock cycles before the trigger event, then the FIFO depth should be set to at least 100. This can ensure that when the trigger event occurs, the relevant data before that can be obtained completely. The FIFO layer configuration in the pre-trigger mode can be configured according to the complexity of data processing and the requirements for data analysis. If more complex pattern detection is required, the number of FIFO layers may need to be increased to perform different processing and analysis at different levels. For example, preliminary data screening can be performed in the first-layer FIFO, and more refined pattern matching can be performed in the second-layer FIFO.

[0052] The FIFO depth configuration in the mid-trigger mode can be that the mid-trigger mode needs to record the data at and around the time when the trigger event occurs. Therefore, the configuration of the FIFO depth should comprehensively consider the amount of data to be stored before and after the trigger event. For example, if you want to record the data of 50 clock cycles before the trigger event and 50 clock cycles after the trigger event, then the FIFO depth should be set to at least 100. At the same time, the FIFO depth can be further adjusted according to the configurable additional storage length. Similarly, the number of layers is configured according to the requirements of data processing and analysis. To comprehensively analyze the whole process of the trigger event, more layers may be required for data processing and storage at different stages. For example, the key data before, during, and after the trigger can be stored in different layers for subsequent detailed comparison and analysis.

[0053] The FIFO depth configuration in the post-trigger mode can mainly focus on data storage after the trigger event occurs. The FIFO depth can be configured according to the time length of the post-trigger data that one wants to observe. For example, if one hopes to record data for 200 clock cycles after the trigger event, then the FIFO depth is set to 200. In addition, factors such as the time when the ping-pong buffer is full and the data input rate also need to be considered to ensure that the key post-trigger data can be stored completely. At the same time, the number of layers can be configured according to the processing requirements for the post-trigger data. If multi-stage processing and analysis are required for the post-trigger data, such as first performing a preliminary screening of the data and then conducting a detailed pattern analysis, the number of layers of the FIFO can be increased.

[0054] Thus, by dynamically configuring the FIFO depth and the number of layers based on the trigger mode, the performance of the storage array and the buffer can be flexibly adjusted according to different debugging and analysis requirements. In different application scenarios, it can quickly adapt to various trigger conditions and data processing requirements, improving the versatility and adaptability of the on-chip logic analyzer. Moreover, the problem of resource waste or insufficiency caused by fixed configuration can be avoided. When a large amount of data storage is not required, the FIFO depth and the number of layers can be reduced to save the storage resources of the chip; while when complex data needs to be processed and in-depth analysis is required, the corresponding configuration can be increased to ensure that the actual needs can be met. In summary, setting the custom storage array and the ping-pong buffer as a multi-level FIFO and dynamically configuring its depth and the number of layers based on the trigger mode can provide a more flexible and efficient data storage and processing ability for the on-chip logic analyzer, meeting diverse debugging and analysis needs.

[0055] In the embodiments of this application, the input data refers to the data stream related to the function to be monitored and analyzed from inside or outside the chip. These data can be of various types, such as binary data transmitted in a digital circuit, the digital representation corresponding to an analog signal after analog-to-digital conversion, etc. For example, in a processor chip, the instruction data, arithmetic data, etc. transmitted on the internal bus of the processor can all be used as the input data of the on-chip logic analyzer. In a communication chip, the packet data transmitted in the communication link can also become the input data. It covers all data information generated or received during the operation of the chip that needs to be monitored and analyzed.

[0056] In the embodiments of the present application, the significant bit mask is a binary number used to filter out the key data bits in the input data. Its bit width is the same as that of the input data, and the attention to the corresponding bits in the input data is indicated by setting "1" and "0" in the mask. When a certain bit in the mask is "1", it means that the corresponding bit in the input data is the valid data bit that the user really cares about; if it is "0", it means that this bit can be ignored in the current analysis. For example, if the input data is 32 bits and the user only cares about the data bits from the 8th to the 15th, then the significant bit mask can be set to 00000000111111110000000000000000. When the on-chip logic analyzer is working, the input data is logically ANDed with the significant bit mask to obtain the filtered data containing only the valid data bits, thereby reducing the amount of data for subsequent processing and focusing on the key information for analysis.

[0057] In the embodiments of the present application, the pattern mask is used to indicate the data flag bits corresponding to specific trigger events. Here, the specific trigger events are associated with the data analysis process performed by the on-chip logic analyzer.

[0058] Specifically, the pattern mask is a binary number, and its bit width is usually the same as that of the input data. It is like a "data key" used to filter out the data that meets specific requirements. Each bit in the mask corresponds to the corresponding bit in the input data. When a certain bit in the pattern mask is set to a specific value (such as "1" or "0"), it means that when judging the trigger condition, the corresponding bit in the input data needs to match it; if it is set to a wildcard (such as "X"), it means that this bit does not need to pay attention to the specific value when judging. For example, for 32-bit input data, if the pattern mask is 1010XXXX1100XXXX, it means that the 1st, 2nd, 5th, 6th, 9th, and 10th bits of the input data are concerned, and it is required that the 1st, 2nd, 9th, and 10th bits are 1, 0, 1, and 0 respectively, while the other bits marked with "X" are not strictly required when triggering the judgment.

[0059] Specific trigger events refer to the key events that users hope to focus on monitoring or analyzing during the operation of the chip. These events can be various. For example, it is triggered when a certain or a group of specific values appear on a specific data line, such as a specific memory address appears on the address bus of the processor, or a key instruction code appears on the data bus. For example, it is triggered when the signal changes from low level to high level, or from high level to low level, such as the rising edge or falling edge of the clock signal, the effective / invalid state switch of a certain control signal, etc. For example, it is triggered when the data in multiple consecutive clock cycles conforms to a pre-set pattern, such as the data sequence of "A-B-C" appears continuously. For example, for a chip containing a state machine, it is triggered when the state machine enters a specific state to analyze the operation of the chip in this state.

[0060] Thus, the occurrence of a specific trigger event is the "switch" to initiate the data analysis process. Once the pattern mask matches the input data, indicating the appearance of a specific trigger event, the on-chip logic analyzer will start collecting, storing, and analyzing relevant data according to the preset process. For example, after detecting a specific data pattern match, all relevant data within a period of time before and after the trigger is recorded for subsequent in-depth analysis of the background, process, and impact of the event occurrence.

[0061] Different specific trigger events correspond to different key points of data analysis. For example, if the trigger event is a change in a certain control signal, the data analysis process may focus on checking the values of relevant registers before and after the change of this signal, the synchronous changes of other signals, etc., to determine whether the control signal is working properly and its impact on the entire system; if the trigger event is an abnormal data value appearing on the data bus, the data analysis process will analyze around the source of this data value, the transmission path, and its impact on subsequent data processing.

[0062] In addition, users can define different specific trigger events by setting different pattern masks according to specific debugging and analysis requirements, and then customize the corresponding data analysis process. At different stages of chip design or when troubleshooting different types of problems, the pattern mask and the corresponding analysis process can be flexibly adjusted, enabling the on-chip logic analyzer to adapt to diverse analysis tasks and improving the efficiency of debugging and fault finding.

[0063] In the embodiments of this application, first, by using the significant bit mask to mark the data bits to be analyzed in the input data, it is possible to focus on the key data part and avoid processing a large amount of irrelevant data. This can reduce the data processing volume, improve the speed and efficiency of data processing, especially when dealing with wide-bit data or data containing a large amount of redundant information, and can significantly improve the analysis efficiency. For example, for a 128-bit data, if only 32-bit key data is concerned, the significant bit mask can directly locate these 32 bits without processing the entire 128-bit data.

[0064] Second, the pattern mask is used to indicate the data flag bits corresponding to specific trigger events, and the specific trigger events are associated with the data analysis process. This enables users to flexibly set trigger conditions according to specific analysis requirements, meeting different debugging and analysis scenarios. No longer limited to fixed trigger conditions, it can more accurately capture the data related to the target event, improving the adaptability and practicality of the logic analyzer. For example, in different chip designs, different pattern masks can be set to trigger data caching according to the functions of the chip and possible problems.

[0065] In addition, since specific trigger events are associated with the data analysis process performed by the on-chip logic analyzer, this technical solution can adapt to diverse data analysis requirements. Whether it is for verifying chip functions, evaluating performance, or troubleshooting faults, accurate and useful data can be obtained by setting appropriate mode masks and data caching methods, providing strong support for in-depth data analysis.

[0066] Furthermore, according to the matching result and the data caching method in which the trigger unit is located, the data storage processes of the custom storage array and the ping-pong buffer are controlled. This enables the target input data that meets the caching requirements to be accurately stored in the ping-pong buffer, avoiding unnecessary data storage and saving storage resources. At the same time, effective control and management can be carried out for different data caching methods (such as pre-trigger, mid-trigger, post-trigger, etc.) to ensure data integrity and accuracy. For example, in the mid-trigger mode, relevant data before and after the trigger event can be accurately stored according to the matching result.

[0067] It can be understood that the combined use of the custom storage array and the ping-pong buffer, as well as the precise control of the data storage process, can optimize the utilization of storage resources. It avoids the problems of storage resource waste or insufficiency that may occur in traditional methods, enabling more reasonable allocation and use of storage resources and improving the overall performance and stability of the system.

[0068] Furthermore, it can be understood that the embodiments of this application do not depend on a specific chip architecture or data type and can be applied to a variety of different on-chip logic analyzers, with strong versatility. Whether processing simple digital signals or complex mixed signals, efficient data caching and analysis can be achieved by adjusting parameters such as the significant bit mask and the mode mask, expanding the application scope of the logic analyzer.

[0069] The specific implementation methods of each step are introduced below with examples.

[0070] In step 101, the input data to be processed is obtained through the trigger unit. For example, the trigger unit first receives the data signal stream from inside or outside the chip, and these signal streams contain various input data to be processed. Then, the custom storage array in the trigger unit will perform real-time monitoring and comparison on the input data according to the preset trigger conditions, such as the specific data pattern indicated by the mode mask. When the input data matches the preset trigger conditions, the trigger unit will be activated.

[0071] The activated trigger unit will store a certain amount of input data before and after the current and trigger points in a custom storage array for subsequent processing and analysis. At the same time, it will also send a signal to the ping-pong buffer to transfer the relevant data to the ping-pong buffer for further caching and processing, ensuring that the data is not lost and can be processed orderly.

[0072] For example, assume that the input data is a series of 32-bit binary numbers, and the pattern mask is set to 1010XXXX1100XXXX. When the data received by the trigger unit, such as 1010111111000010, matches the pattern mask, the trigger unit is activated. It will store this 32-bit data and several pieces of data before and after the trigger point in a custom storage array, such as the previous data 1111000011110000 and the next data 0011110000111100, and at the same time transfer these data to the ping-pong buffer to complete the acquisition of the input data to be processed.

[0073] In the above or below embodiments, before step 101, a target trigger mode that matches the caching requirement can also be selected from multiple trigger modes configured by the trigger unit. Among them, the caching requirement is obtained based on a user input instruction; or the caching requirement is determined by the data analysis of the on-chip logic analyzer. Furthermore, the attribute parameters in the target trigger mode are set to configure a valid bit mask, a pattern mask, and the data caching method in which the trigger unit is located that match the caching requirement.

[0074] Specifically, first, the trigger unit provides multiple preset trigger modes, such as pre-trigger, mid-trigger, and post-trigger modes. When the user inputs an instruction or the data analysis of the on-chip logic analyzer determines the cache requirement, the system selects a target trigger mode that matches the cache requirement from these trigger modes. If the cache requirement is to obtain the data before the trigger event occurs, the pre-trigger mode will be selected. If it is necessary to obtain the data when and around the trigger event occurs, the mid-trigger mode will be selected. If only the data after the trigger event is of concern, the post-trigger mode will be selected. After selecting the target trigger mode, the attribute parameters in this mode need to be set. For the significant bit mask, according to the cache requirement, determine the key data bits to be concerned, set the corresponding bits to 1, and the remaining bits to 0. For example, if the input data is 32 bits and only the 8th to 15th bits are of concern, the significant bit mask is set to 00000000111111110000000000000000. The mode mask is set according to a specific trigger event. For example, if it is desired that the trigger event is the data pattern 10101010, the mode mask is set to 10101010. The data caching method is also configured according to the target trigger mode and the cache requirement. In the pre-trigger mode, data is continuously stored from the beginning to the custom storage array and the ping-pong buffer until the trigger condition is met; in the mid-trigger mode, data is continuously stored and a certain amount of data is stored after the trigger condition is met; in the post-trigger mode, data storage starts only after the trigger condition is met. For example, when the user inputs an instruction to obtain the data before the abnormal trigger of a certain chip, the system selects the pre-trigger mode. Set the significant bit mask to focus on the relevant bits of the key control signals of the chip, and set the mode mask to the corresponding mode of the abnormal signal. The data caching method is to continuously store data until the abnormal signal trigger is detected, achieving a configuration that matches the cache requirement.

[0075] Further optionally, the structure and storage depth of the custom storage array are determined by the data caching method configured in the target trigger mode.

[0076] In the pre-trigger mode, it is necessary to record the data before the trigger event occurs. The structure design of the custom storage array should be able to continuously store data until the trigger event appears. Usually, a continuous FIFO (First In First Out) structure can be adopted to ensure that the data is stored in chronological order. The storage depth depends on the time length of the pre-trigger data that is desired to be recorded. For example, if the system clock period is T, assume that the data for N clock cycles before the trigger is to be recorded, and one data unit is generated per clock cycle, then the storage depth should be set to N. In this way, when the trigger event occurs, the data for N clock cycles before the trigger is saved in the storage array.

[0077] The middle trigger mode requires recording data before, during, and after the trigger event occurs. At this time, the custom storage array can be designed as a multi-level FIFO structure. The first-level FIFO is used to store data before the trigger, the second-level FIFO is used to store data during the trigger, and the third-level FIFO is used to store data after the trigger. Data transfer and switching between each level of FIFO are carried out through control logic. The storage depth needs to comprehensively consider the amount of data to be recorded before and after the trigger. Suppose it is desired to record data for M clock cycles before the trigger, 1 clock cycle during the trigger, and K clock cycles after the trigger. Then the total storage depth should be M + 1 + K. Among them, the depth of the first-level FIFO is M, the depth of the second-level FIFO is 1, and the depth of the third-level FIFO is K.

[0078] The post-trigger mode mainly focuses on the data after the trigger event occurs. The custom storage array can adopt a FIFO structure that is initially empty and starts storing data after the trigger event occurs. The storage depth is determined according to the time length of the data after the trigger that is desired to be recorded. If it is desired to record data for P clock cycles after the trigger, the storage depth is set to P.

[0079] Thus, by accurately configuring the structure and storage depth of the custom storage array according to different trigger modes, it can be ensured that the required data can be completely recorded in various situations. For example, in the pre-trigger mode, historical data before the trigger event can be accurately obtained, providing strong support for analyzing the root cause of problems; in the middle trigger mode, the entire process of the trigger event can be comprehensively recorded, including signal changes before and after; in the post-trigger mode, the system response data after the trigger event can be focused on. Reasonable configuration avoids waste of storage resources. For different trigger modes, only the necessary storage depth is allocated, without occupying too many chip resources due to over-allocation, and at the same time, the actual caching requirements can be met, improving the resource utilization efficiency. This way of dynamically configuring the storage array according to the trigger mode enables the on-chip logic analyzer to flexibly adapt to different debugging and analysis scenarios. Whether it is necessary to analyze historical data, comprehensively understand the event process, or focus on subsequent reactions, the requirements can be met by adjusting the structure and depth of the storage array, enhancing the versatility and practicality of the system.

[0080] Exemplarily, in the above steps, setting the attribute parameters in the target trigger mode to configure the valid bit mask, mode mask, and the data caching method in which the trigger unit is located that match the caching requirements includes: identifying the data analysis type in the caching requirements; determining the data bits currently required for analysis according to the data analysis type, the data type to which the input data belongs, and the historical analysis method, and generating the corresponding valid bit mask.

[0081] The significant bit mask is a binary number with the same width as the input data bits, used to mark which bits in the input data are the key data bits that users are concerned about. A "1" in the mask indicates that the bit is valid (to be retained), and a "0" indicates that the bit is invalid. Through a logical AND operation, the significant bit mask can extract the part that the user cares about from the input data, reducing the amount of data for subsequent processing.

[0082] In an on-chip logic analyzer, the significant bit mask is a binary number with the same width as the input data. Its function is to filter out the key data bits that users are concerned about in the input data, which is specifically achieved through a logical AND operation. Exemplarily, the specific data analysis type is determined based on cache requirements. If it is functional verification, the focus will be on specific instructions or register bits; if it is performance analysis, it is necessary to monitor data throughput or timing relationships; for troubleshooting, it is necessary to locate abnormal signals or error codes. For example, in functional verification, a specific instruction code in a processor will become the focus of attention; in performance analysis, the data transfer rate of the bus is the key; in troubleshooting, an abnormal value output by a sensor is crucial.

[0083] When the input data is 32 bits, different types of data have different bit segment divisions. For address bus data, the upper 16 bits represent the address space, and the lower 16 bits are the offset. In sensor data, the first 8 bits are the device ID, and the last 24 bits are the measurement value. Taking address bus data as an example, the upper 8 bits may correspond to the page number, which needs to be monitored during functional verification. Determine the bit segments that are prone to problems based on past debugging experience. For example, in the past, the 16th - 24th bits (temperature value) of sensor data often had faults, so this part of the bit segment needs to be focused on in subsequent analysis. Generate corresponding masks according to different scenarios. In the functional verification scenario, if you want to verify the page number (upper 8 bits) of the address bus, the mask will be set to FF000000 (the first 8 bits in binary are 1); in the troubleshooting scenario, if you want to monitor the sensor temperature value (the 16th - 24th bits), the mask will be set to 00FF0000 (the 16th - 24th bits in binary are 1). Furthermore, the mask can be dynamically updated according to the actual situation. If it is found in subsequent analysis that additional bits need to be concerned, such as the lower 4 bits of the sensor ID, the mask can be updated to 000000F0 (only the 4th - 7th bits are retained).

[0084] Thus, by only processing the valid bits, the data processing volume is greatly reduced. Taking 32-bit data as an example, if only 8 bits are concerned, the amount of computation can be reduced by 75%. At the same time, the trigger condition matching time is also shortened, and the real-time performance is improved. The application of the valid bit mask reduces the storage requirement, and the ping-pong buffer only needs to store the valid bit data. In addition, power consumption is saved, and the transmission and calculation of redundant data are reduced. The user can dynamically adjust the mask according to different analysis targets to adapt to various scenarios. For example, when debugging a network protocol, the mask can focus on the IP address segment. When verifying an encryption algorithm, the mask focuses on the key-related bits. The combination of historical analysis and the mask can quickly reproduce and locate historical faults. For example, by retaining the fault-related bits with the mask, the abnormal data pattern can be automatically captured when triggered. The valid bit mask greatly improves the efficiency and flexibility of the on-chip logic analyzer by dynamically screening the key data bits. It combines the data analysis type, data characteristics, and historical experience to accurately generate the mask, achieving the dual goals of resource optimization and problem location.

[0085] Another example, in the above steps, setting the attribute parameters in the target trigger mode to configure the valid bit mask, mode mask, and the data caching method of the trigger unit that match the cache requirement, includes: determining the data transition form of the data to be observed in the cache requirement; the data transition form includes at least one of: data change value, data change trend, data change amplitude, data timing, data repetition times; dynamically configuring the corresponding mode mask according to the determined data transition form.

[0086] In an on-chip logic analyzer, the pattern mask is a binary number with the same width as the input data bits, used to define the target data pattern corresponding to the trigger event. It filters the input data through logical matching (such as AND, OR, XOR), and supports wildcards (such as X representing don't care bits), thus flexibly matching specific data features. For example, if it is necessary to detect that the upper 8 bits of 32-bit data are 1010 and the lower 8 bits are arbitrary, the pattern mask can be set to 1010XXXXXXXXXXXX. Specifically, the pattern mask is dynamically configured according to the data transition form to be observed in the cache requirement. For example, if the data transition form is the data change value, the pattern mask can be set to match a specific value (such as "deadbeef"); if it is the data change trend, the increasing or decreasing pattern can be defined by comparing the data in consecutive clock cycles; if it is the data timing, a multi-level FIFO is configured to record the consecutive data sequence (such as "A-B-C"). Taking the data repetition count as an example, if it is necessary to detect that a specific pattern (such as "55AA") appears continuously 3 times, the pattern mask can be configured in combination with a counter to trigger when it is continuously matched 3 times. This dynamic configuration mechanism significantly improves the flexibility of the trigger condition. Traditional fixed pattern triggering cannot adapt to complex scenarios, while this solution can accurately match events such as signal mutations, abnormal sequences, or timing violations by analyzing the data transition form. For example, in high-speed bus debugging, if it is found that the data bursts with high-frequency jitter (the change amplitude exceeds the threshold), the pattern mask can be updated in real time to "XX……XX" (retaining the key bits) and the amplitude threshold can be set to accurately capture the abnormal data.

[0087] Thus, by matching the data transition form, false triggers are reduced, for example, filtering accidental noise and only capturing the signals that conform to the expected pattern. Dynamic adjustment of the mask is supported to meet diverse requirements such as timing analysis and anomaly detection. For example, in processor debugging, the instruction sequence "LDR-ADD-STR" is matched through the pattern mask to trigger the recording of context data. Only the matching data is stored, reducing the storage pressure. For example, in the post-trigger mode, storage is only started when the data transition conforms to the mask, avoiding redundant data. Combining with the significant bit mask can quickly locate the root cause of the problem. For example, when the sensor data is abnormal, the temperature value bits are retained through the mask and the mutation pattern is matched to quickly reproduce the fault. In summary, through dynamic adaptation to the data transition form, the pattern mask realizes the intelligent configuration of the trigger condition, significantly enhancing the debugging ability of the on-chip logic analyzer for complex scenarios.

[0088] Another example is that the data caching method is jointly determined by the data type to be analyzed and the time period when the data is located. In the above steps, setting the attribute parameters in the target trigger mode to configure the significant bit mask, pattern mask, and the data caching method where the trigger unit is located that match the cache requirement includes:

[0089] Determine the data type required for analysis and the time period in which the data is located in the cache requirement; according to the data type required for analysis and the time period in which the data is located, select the corresponding target data caching method from a variety of pre-configured data caching methods.

[0090] In an on-chip logic analyzer, the data caching method refers to a mechanism that selects a specific strategy to store data related to trigger events according to debugging requirements and data characteristics. Common methods include pre-trigger, mid-trigger, post-trigger, and custom combination modes. The core lies in controlling the starting point, duration, and coverage of data storage to balance storage resources and analysis requirements. Specifically, it is necessary to first determine the data type (such as instruction stream, sensor data, bus transaction) and the time period (before trigger, during trigger, after trigger) in the cache requirement. For example, if the analysis target is "abnormal instruction sequence before a fault", the data type is an instruction stream, and the time period is before the trigger, then select the pre-trigger mode to continuously store data until a specific instruction pattern is detected; if it is necessary to verify "the system response after a sudden change in the sensor signal", the data type is the analog-to-digital value, and the time period is after the trigger, then adopt the post-trigger mode to only record the data stream after the mutation.

[0091] Taking processor debugging as an example, if the data type is an address bus transaction and the time period requirement covers 50 cycles before the trigger and 100 cycles after the trigger, the mid-trigger mode can be configured: the pre-trigger part caches the historical addresses, and the subsequent data is appended and stored after the trigger. At this time, the ping-pong buffer depth needs to be set to 150 to ensure the complete capture of the context.

[0092] Thus, by matching the data type and the time period, redundant storage is avoided. For example, for high-frequency bus data that only needs to be analyzed after the trigger, the post-trigger mode can save more than 90% of the storage space. Dynamic mode switching is supported. For example, when switching from performance analysis (mid-trigger) to fault reproduction (pre-trigger), no hardware modification is required, only the parameters need to be reconfigured. For timing-sensitive data (such as DDR bus handshake signals), the mid-trigger mode can ensure the complete recording of signal interactions before and after the trigger event, facilitating the analysis of setup / hold time violations. For example, in an automotive electronic chip, if it is necessary to analyze the airbag control logic after a collision signal trigger, the post-trigger mode can directly capture the sensor data and control instructions within 200 ms after the trigger, quickly locating the response delay problem. In summary, the data caching method realizes the refined management of storage resources by combining the data type and time period requirements, enabling the on-chip logic analyzer to efficiently handle diverse debugging scenarios.

[0093] As an alternative embodiment, the triggering unit further includes a significant bit mask module. In 102, a significant bit mask is used to mark corresponding data bits to be analyzed in the input data. Specifically, through the significant bit mask module, the input data is covered with the significant bit mask to cover the invalid data bits in the input data and retain the data bits to be analyzed in the input data.

[0094] The main function of the significant bit mask module is to accurately filter out the data bits that need to be analyzed during the data processing, eliminate the interference of irrelevant data, improve the efficiency and accuracy of data processing, and reduce resource occupancy. For example, assume that a 32-bit sensor data register value needs to be analyzed, where the high 8 bits represent the sensor type code and the low 24 bits represent the sensor measurement data. In the current analysis task, only the measurement data, that is, the low 24 bits, need to be concerned. At this time, the significant bit mask module can play a role. It will generate a significant bit mask, such as 0x00FFFFFF (binary representation: 00000000111111111111111111111111). This mask is logically ANDed with the input 32-bit sensor data to mask out the high 8-bit sensor type code and only retain the low 24-bit measurement data.

[0095] In this way, in the subsequent links of data processing, whether it is storage, transmission, or analysis and calculation, only operations need to be performed on these 24 valid data bits, instead of processing the entire 32-bit data. In this way, in terms of data storage, it can reduce the occupancy of storage resources. For example, originally a 32-bit storage unit was required to store data, but now only a 24-bit storage unit is needed; during data transmission, it can also reduce the amount of data transmitted and improve the transmission efficiency; during data analysis, unnecessary data processing is reduced, the analysis speed can be accelerated, the accuracy and efficiency of analysis can be improved, and the analysis results can be more focused on key information.

[0096] As an alternative embodiment, in step 103, comparing whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed can be implemented as the following steps:

[0097] Step 1031, detecting the data values of the data bits to be analyzed in each clock cycle to determine whether there are data bits to be analyzed that are the same as the data values indicated by the pattern mask;

[0098] After detecting the data bits to be analyzed that are the same as the data values indicated by the pattern mask, step 1032, determining whether the repetition times and / or occurrence order of the data values in the data bits to be analyzed are the same as the repetition times and / or occurrence order of the data values indicated by the pattern mask;

[0099] Step 1033, if the number of repetitions and / or the order of occurrence of the data values in the data bits to be analyzed are the same as the pattern mask, it is determined that the data bits to be analyzed match the pattern mask;

[0100] Step 1034, if no data bit to be analyzed that is consistent with the data value indicated by the pattern mask is detected, or the number of repetitions and / or the order of occurrence of the data values in the data bits to be analyzed are different from the pattern mask, then the data bits to be analyzed do not match the pattern mask.

[0101] The following details the specific steps and principles for comparing the matching situation between the data bits to be analyzed and the pattern mask in this optional embodiment.

[0102] In step 1031, the consistency between the data bits to be analyzed and the data values of the pattern mask is detected in each clock cycle. During the operation of the on-chip logic analyzer, data bits to be analyzed are generated in each clock cycle. The pattern mask predefines the expected matching data values. The system continuously monitors the data values of the data bits to be analyzed in each clock cycle and compares them bit by bit with the data values indicated by the pattern mask. For example, if the pattern mask is "1010" and the data bit to be analyzed generated in clock cycle 1 is "1100", then this data bit does not match the pattern mask; if the data bit to be analyzed generated in clock cycle 2 is "1010", then a data bit to be analyzed that is consistent with the data value indicated by the pattern mask is detected.

[0103] In step 1032, the number of repetitions and / or the order of occurrence of the data values are judged. After detecting a data bit to be analyzed that is consistent with the data value indicated by the pattern mask, the system also needs to further check whether the number of repetitions and the order of occurrence of the data values meet the requirements of the pattern mask. This step is to handle more complex matching scenarios, such as a specific data sequence needs to repeat a specific number of times to be regarded as a valid trigger. For example, assume that the pattern mask requires the data sequence "1010" to repeat continuously 3 times. After detecting the first "1010", the system will continue to monitor the data in subsequent clock cycles. If "1010" also appears in the next two clock cycles, then the number of repetitions and the order of occurrence of the data values are the same as the pattern mask; if other data sequences, such as "1100", appear during this process, then it does not meet the requirements.

[0104] In step 1033, if the number of repetitions and / or the order of occurrence of the data values in the data bits to be analyzed are the same as the pattern mask, it can be determined that the data bits to be analyzed match the pattern mask. This means that the current data stream meets the preset trigger condition, and the logic analyzer can perform corresponding operations according to this matching result, such as starting to store data in the ping-pong buffer, etc.

[0105] In step 1034, if during the entire monitoring process, no data bits to be analyzed that match the data values indicated by the pattern mask are detected, or although matching data values are detected, the repetition count and / or the order of occurrence of the data values are different from the pattern mask, then it is determined that the data bits to be analyzed do not match the pattern mask. In this case, the logic analyzer does not trigger the corresponding storage or other operations and continues to monitor the subsequent data stream.

[0106] Through the above steps, the on-chip logic analyzer can accurately determine whether the data bits to be analyzed match the pattern mask, thereby achieving precise data triggering and analysis to meet different debugging and monitoring requirements.

[0107] As an optional embodiment, multiple trigger modes for the ping-pong buffer are set in the trigger unit. Further, the multiple trigger modes of the ping-pong buffer include: pre-trigger mode, mid-trigger mode, and post-trigger mode. Specifically, the data caching method of the pre-trigger mode is: storing the first target data bits in the input data that are before the pattern mask. The data caching method of the mid-trigger mode is: storing the second target data bits in the input data from before the pattern mask to after the pattern mask. The data caching method of the post-trigger mode is: storing the third target data bits in the input data that are after the pattern mask.

[0108] For different trigger modes, data signals in different time periods can be recorded. During logic analysis and debugging, the trigger type determines the specific time period for data capture. The pre-trigger mode, mid-trigger mode, and post-trigger mode respectively indicate different strategies for capturing data before and after the trigger signal event. The pre-trigger mode (Pre-Trigger) captures the signal state for a period of time before the trigger event. This mode helps to understand the historical background of the system behavior before the trigger event and is very helpful for diagnosing the root cause of problems. The mid-trigger mode (Mid-Trigger) captures data at and around the trigger event. It provides a comprehensive perspective, including signal changes before and after the event. This mode is suitable for situations where a comprehensive analysis of the entire process of the trigger event is desired. The post-trigger mode (Post-Trigger) captures the signal state for a period of time after the trigger event. This mode focuses on observing the reaction after the trigger event and helps to analyze the consequences of the trigger event.

[0109] As an optional embodiment, in step 104, according to the matching result and / or the data caching method in which the trigger unit is located, control the data storage process of the custom storage array and the ping-pong buffer, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer, including:

[0110] After switching to the trigger mode in which the trigger unit is located, instruct the custom storage array and / or the ping-pong buffer to start the data writing process for the input data; and / or, if the data bit to be analyzed matches the pattern mask, instruct the ping-pong buffer to start or stop the data writing process for the input data, so as to extract the target data bits to be cached from the input data as the target input data.

[0111] When the on-chip logic analyzer is working, according to the actual debugging requirements, the trigger mode will be set in advance, such as pre-trigger, mid-trigger, post-trigger mode, etc. When switching to the specified trigger mode, this is an important start signal for the entire data storage process. After the trigger mode switching is completed, it will instruct the custom storage array and / or the ping-pong buffer to start the data writing process for the input data. For example, in the pre-trigger mode, the custom storage array will start continuously storing the input data before the trigger event occurs, so as to record the relevant data information before the trigger event. If the ping-pong buffer is also required to participate in data caching at the same time, the ping-pong buffer will also start writing data synchronously to ensure the continuity and integrity of the data.

[0112] After comparing the data bit to be analyzed in the input data with the pattern mask, if it is found that the data bit to be analyzed matches the pattern mask, this means that the current input data meets the pre-set trigger condition. At this time, if the ping-pong buffer was in an unwritten state before, it will instruct the ping-pong buffer to start the data writing process for the input data. For example, when debugging a communication protocol, the pattern mask is set to match a specific protocol header. When the same header as the pattern mask appears in the input data, the ping-pong buffer starts writing data and stores the subsequent data for subsequent analysis of the entire protocol frame.

[0113] Similarly, when the data bit to be analyzed matches the pattern mask, if the ping-pong buffer was in a written state before, it can also instruct the ping-pong buffer to stop writing data according to specific requirements. For example, in a scenario where only a fixed length of data after the trigger event needs to be recorded, when the pattern mask is matched and the specified length of data has been stored, the ping-pong buffer will be instructed to stop writing to avoid storing too much unnecessary data and save storage resources.

[0114] By controlling the start and stop writing processes of the ping-pong buffer, the target data bits to be cached can be accurately extracted from the input data, and these target data bits together constitute the target input data. These target input data are crucial for subsequent data analysis and debugging work, and can help engineers quickly locate problems, verify functions, etc.

[0115] Through the above two methods, the data storage process of the custom storage array and the ping-pong buffer can be flexibly controlled according to the matching results and trigger modes, and the target input data that meets the cache requirements can be accurately stored in the ping-pong buffer.

[0116] The following specifically introduces the specific mechanism for enabling or stopping writing in the ping-pong buffer with examples:

[0117] The principle of the control mechanism based on trigger conditions is that when the data bits to be analyzed match the pre-set pattern mask, corresponding control signals will be triggered. The pattern mask defines the data flag bits corresponding to specific trigger events. For example, when debugging a communication system, the pattern mask may be set to match the start flag of a specific data packet. When the input data is processed and the data bits to be analyzed are consistent with the pattern mask, a matching signal will be generated.

[0118] Enabling writing: This matching signal will be sent to the control logic part of the ping-pong buffer. If the ping-pong buffer is in an idle state at this time, the control logic will enable the write enable signal to start the data writing process. For example, when a specific protocol header is detected, the write enable signal becomes high level, allowing data to flow into the ping-pong buffer from the data source.

[0119] Stopping writing: In some cases, when specific conditions are met, such as when a preset number of data has been stored or a specific time threshold has been reached, the control logic will revoke the write enable signal to stop data writing. For example, if it is set to record only one complete data packet, when the end flag of the data packet is detected, the write enable signal becomes low level to stop writing.

[0120] Trigger modes include pre-trigger, mid-trigger, post-trigger, etc. When the system switches to a specific trigger mode, a corresponding mode switching signal will be generated. Different trigger modes correspond to different data storage requirements. Taking the pre-trigger mode as an example, before the trigger event occurs, the system will instruct the ping-pong buffer to start writing according to the mode switching signal. For example, when debugging the instruction execution process of a processor, setting the pre-trigger mode, before detecting the possible abnormal instruction trigger event, the ping-pong buffer starts writing instruction data to record the state before the trigger event occurs. For the post-trigger mode, when the trigger event occurs, writing starts, and when the preset storage depth is reached or other stop conditions are met, writing stops. For example, after detecting a certain fault signal trigger, start recording subsequent data, and stop writing when the ping-pong buffer is full or the fault recovery signal appears.

[0121] The control logic of the ping-pong buffer is usually implemented by a state machine. The state machine has different states, such as the idle state, the write state, the stop state, etc. By receiving input signals such as trigger signals and mode switching signals, the state machine switches between different states. For example, when a trigger signal that matches the mode mask is received, the state machine switches from the idle state to the write state to start writing; when the stop condition is met, it switches from the write state to the stop state to stop writing. Further, in order to control the length and time of writing, a counter and a timer are used in the control logic. The counter can record the number of data that has been written, and when the counter reaches a preset value, writing stops. The timer can set the length of the writing time, and when the time arrives, writing stops.

[0122] In the hardware circuit of the ping-pong buffer, there is a dedicated write enable pin. The control logic controls this pin by outputting high and low level signals, thereby realizing the start and stop of writing. When the write enable signal is high, data can be written into the ping-pong buffer; when it is low, the write operation is prohibited. In addition to the write enable signal, the switch of the data path also needs to be controlled. When writing is enabled, the data path is turned on, allowing data to be transmitted from the data source to the ping-pong buffer; when writing stops, the data path is cut off to prevent data from continuing to flow in.

[0123] Example 1: Pre-trigger mode.

[0124] First, in the above steps, after the trigger unit switches to the pre-trigger mode, a first write signal for enabling the data storage function is generated; the data writing function of the ping-pong buffer is started through the first write signal; the input data is sequentially transmitted to the ping-pong buffer in the received order through the custom storage array. Furthermore, in the above steps, after the data bit to be analyzed is detected to match the mode mask in the custom storage array, a first stop signal for immediately stopping the data storage function is generated; the data writing function of the ping-pong buffer is turned off through the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the first target data bit.

[0125] It can be understood that when the trigger unit receives an instruction to switch to the pre-trigger mode, the internal control logic will perform corresponding state transitions to generate a first write signal for enabling the data storage function. This signal can be a level signal (e.g., high level indicates validity), which is used to notify the ping-pong buffer and the custom storage array that the data storage operation is about to start. The first write signal is sent to the ping-pong buffer. After the control circuit of the ping-pong buffer receives this signal, it will enable the relevant circuit modules for writing, such as turning on the switch of the data input port to allow data to flow in. At this time, the ping-pong buffer is ready to receive data from the custom storage array. After receiving the first write signal, the custom storage array starts to sequentially transfer the input data to the ping-pong buffer according to the order of data reception. During this process, the custom storage array may use internal caches and data transfer logic to ensure stable data transfer. For example, it can send a data unit to the data bus of the ping-pong buffer in each clock cycle. During the continuous data transfer of the custom storage array, the internal comparison module will continuously detect whether the data bits to be analyzed match the pattern mask.

[0126] When it is detected that the two match, the comparison module will trigger the control logic to generate a first stop signal for immediately stopping the data storage function. This signal can also be a level signal. The first stop signal is sent to the ping-pong buffer and the custom storage array. After the ping-pong buffer receives this signal, it will turn off the writing function, such as turning off the switch of the data input port to prevent new data from flowing in. At the same time, the custom storage array will also stop transferring data to the ping-pong buffer, cutting off the data connection between the two. In this way, the data stored in the ping-pong buffer is the target data bits from the start of storage to the detection of the match, that is, the first target data bits.

[0127] Thus, the pre-trigger mode can start storing data before the trigger event occurs, ensuring that when the trigger event occurs, the complete data information before the trigger can be obtained. This is very helpful for analyzing the causes and background of the trigger event. For example, when analyzing a circuit fault, the circuit state and data changes before the fault can be viewed. By matching the pattern mask with the data bits to be analyzed to stop data storage, the moment when the trigger event occurs can be accurately located, so that the stored data contains the most relevant information, reducing the storage of irrelevant data and improving the efficiency and pertinence of data storage. The first target data bits stored in the ping-pong buffer provide an accurate data basis for subsequent fault troubleshooting and system analysis. Engineers can analyze the system state changes before and after the trigger event based on this data, quickly locate the problem, and improve the efficiency of debugging and maintenance. The implementation method of the pre-trigger mode enables users to flexibly configure the pattern mask and trigger conditions according to specific requirements to adapt to different application scenarios and analysis purposes. It can provide effective data support both in hardware debugging and software function verification.

[0128] Example 2: Middle-trigger mode.

[0129] First, in the above steps, after the trigger unit switches to the middle-trigger mode, a first write signal for enabling the data storage function is generated, and the data storage function of the custom storage array is started; the data writing function of the ping-pong buffer is started through the first write signal; the input data is sequentially transmitted to the ping-pong buffer by the custom storage array according to the reception order. Further, in the above steps, after the data bits to be analyzed are detected to match the pattern mask in the custom storage array, a second stop signal for stopping the data storage function after a preset clock cycle is generated according to the pre-configured storage rule; the number of preset clock cycles is determined by the preset number of bits to be stored after the pattern mask. Finally, the data writing function of the ping-pong buffer is delayed from being closed, and the data transmission between the custom storage array and the ping-pong buffer is delayed from being stopped through the second stop signal, so that the target data bits stored in the ping-pong buffer are the second target data bits.

[0130] It can be understood that when the trigger unit receives an instruction to switch to the middle-trigger mode, its internal logic undergoes a state transition to generate a first write signal for enabling the data storage function. On the one hand, this signal starts the data storage function of the custom storage array to start caching the input data; on the other hand, it is sent to the ping-pong buffer, so that the control circuit of the ping-pong buffer enables the write module and opens the data input port to prepare to receive data. The custom storage array sequentially transmits the input data to the ping-pong buffer according to the reception order, and during this process, the data continuously flows in and is stored.

[0131] While the custom storage array continuously receives and transmits data, the internal comparison module therein detects in real time whether the data bits to be analyzed match the pattern mask. Once the match is detected, the control logic of the trigger unit generates a second stop signal according to the pre-configured storage rules. Here, the storage rules are related to the preset clock cycles, and the number of preset clock cycles is determined by the number of preset bits to be stored after the pattern mask. For example, if 32 bits of data are transmitted per clock cycle and it is preset to store 128 bits of data after the pattern mask match, then the number of preset clock cycles is 4.

[0132] After the second stop signal is generated, it does not take effect immediately. It will be sent to the ping-pong buffer and the custom storage array after passing through the preset number of clock cycles. When the ping-pong buffer receives the second stop signal, it will close the write function, close the data input port, and prevent new data from flowing in; at the same time, the custom storage array will also stop transmitting data to the ping-pong buffer, cutting off the data connection between the two. At this time, the data stored in the ping-pong buffer is the target data bits stored from the start of storage to after the pattern mask match and then after the preset clock cycles, that is, the second target data bits.

[0133] Thus, the mid-trigger mode can not only record the data before the trigger event occurs, but also continue to store a certain amount of data according to the preset rules after the trigger event occurs. This enables users to comprehensively understand the whole process of the trigger event, including the state before the trigger, the situation at the time of the trigger, and the system response after the trigger, which is very helpful for in-depth analysis of the causes and impacts of the event. By pre-configuring the storage rules and determining the preset clock cycles according to the number of preset bits to be stored after the pattern mask, users can flexibly control the storage depth of the data. The storage length can be adjusted according to specific analysis requirements, ensuring that sufficient information is obtained while avoiding storing too much unnecessary data, thereby improving the utilization efficiency of storage resources. In many practical applications, analyzing only the data before or after the trigger may not meet the requirements. The mid-trigger mode provides a compromise solution that can adapt to various complex analysis scenarios. For example, when debugging complex digital circuits or software systems, this mode can help engineers more accurately locate problems and improve the efficiency of fault troubleshooting and system optimization. This mode makes the on-chip logic analyzer more intelligent and flexible in data acquisition and storage, better meeting the debugging needs of different users and different projects, enhancing the overall debugging ability of the system, and providing engineers with a more powerful tool to verify and optimize the design.

[0134] Example 3: Post-trigger mode.

[0135] First, in the above steps, after the trigger unit switches to the post-trigger mode, a first stop signal for immediately stopping the data storage function is generated; the data writing function of the ping-pong buffer is turned off through the first stop signal. Further, in the above steps, after the data bit to be analyzed is detected to match the pattern mask in the custom storage array, according to the pre-configured storage rule, a second write signal for starting the data storage function is generated; the data writing function of the ping-pong buffer is started through the second write signal; the input data is sequentially transmitted to the ping-pong buffer by the custom storage array in the order of reception. Finally, in the above steps, after a preset clock cycle, the first stop signal is generated; wherein, the number of preset clock cycles is determined by the number of preset bits to be stored after the pattern mask. The data writing function of the ping-pong buffer is turned off through the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the third target data bit.

[0136] It should be noted that when the trigger unit receives an instruction to switch to the post-trigger mode, its internal logic quickly reacts and generates a first stop signal for immediately stopping the data storage function. This signal is sent to the ping-pong buffer. After the control circuit of the ping-pong buffer receives this signal, it immediately turns off the writing function, closes the data input port, and prevents the input data from flowing into the ping-pong buffer. At this time, the ping-pong buffer is in a state of not storing data.

[0137] During the period when the custom storage array stops storing data in the ping-pong buffer, it continuously receives input data and analyzes the data. The comparison module inside it continuously detects whether the data bit to be analyzed matches the pattern mask. Once it detects a match between the two, the control logic of the trigger unit will generate a second write signal for starting the data storage function according to the pre-configured storage rule. In the storage rule, the number of preset clock cycles is determined by the number of preset bits to be stored after the pattern mask. For example, if 64 bits of data are transmitted per clock cycle and it is preset to store 256 bits of data after the pattern mask match, then the number of preset clock cycles is 4.

[0138] The second write signal is sent to the ping-pong buffer. After the control circuit of the ping-pong buffer receives this signal, it enables the writing module, opens the data input port, and starts receiving data. The custom storage array sequentially transmits the input data to the ping-pong buffer in the order of reception, and the data starts to flow in and be stored continuously.

[0139] After a preset number of clock cycles, the trigger unit generates the first stop signal again. This signal is sent to the ping-pong buffer and the custom storage array. After receiving the signal, the ping-pong buffer closes the write function, shuts down the data input port, and prevents new data from flowing in. The custom storage array also stops transmitting data to the ping-pong buffer, cutting off the data connection between the two. At this time, the data stored in the ping-pong buffer is the target data bits from when the pattern mask matching started until the first stop signal is received again, that is, the third target data bits.

[0140] Thus, the post-trigger mode focuses on storing relevant data after the trigger event occurs, and is very suitable for scenarios where only the system state changes and responses after the trigger event are concerned. For example, after detecting a system fault signal, a series of data after the fault occurs can be accurately obtained through the post-trigger mode, which helps to analyze the specific causes and impact ranges of the fault. By pre-configuring the storage rules and determining the preset clock cycles according to the preset number of bits to be stored after the pattern mask, the stored data content and length can be precisely controlled. This avoids storing too much irrelevant historical data, improves the utilization efficiency of storage resources, and also makes subsequent data processing and analysis more efficient because the amount of data to be processed is relatively small and more targeted. In some application scenarios, such as paying attention to the execution situation after a specific function call in software debugging or the system response after a certain signal change in hardware testing, the post-trigger mode can well meet these specific analysis requirements. It provides a flexible way to obtain the data of interest and enhances the applicability of the on-chip logic analyzer in different application scenarios. Since only the relevant data after the trigger is stored, the complexity and amount of data processing are reduced, simplifying the data processing flow. Engineers can analyze and interpret the stored data more quickly, improving the efficiency of fault troubleshooting and system optimization, and helping to solve problems and improve the design faster.

[0141] In the embodiments of the present application, through the collaborative control of the significant bit mask, the pattern mask, the custom storage array, and the ping-pong buffer, the trigger conditions can be flexibly set according to specific analysis requirements, meeting different debugging and analysis scenarios, more accurately capturing the data related to the target event, improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization rate of storage resources, and further providing strong support for in-depth data analysis.

[0142] In another embodiment of the present application, an on-chip logic analyzer is further provided. Refer to Figure 3 As described, the on-chip logic analyzer at least includes the following structures: a trigger unit, a ping-pong buffer, and the trigger unit at least includes a custom storage array; wherein,

[0143] A trigger unit, configured to obtain input data to be processed; use a significant bit mask to mark corresponding data bits to be analyzed in the input data; compare whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; wherein, the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process performed by the on-chip logic analyzer; control the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer;

[0144] A ping-pong buffer, configured to receive target input data input through a custom storage array.

[0145] Further optionally, the trigger unit further includes a significant bit mask module; the trigger unit, using a significant bit mask to mark corresponding data bits to be analyzed in the input data, is configured to:

[0146] Through the significant bit mask module, use the significant bit mask to perform a masking process on the input data to mask the invalid data bits in the input data and retain the data bits to be analyzed in the input data.

[0147] Further optionally, before the trigger unit obtains the input data to be processed through the trigger unit, it is further configured to:

[0148] Select a target trigger mode that matches the caching requirements from multiple trigger modes configured by the trigger unit; wherein, the caching requirements are obtained based on a user input instruction; or the caching requirements are determined by the data analysis of the on-chip logic analyzer;

[0149] Set the attribute parameters in the target trigger mode to configure a significant bit mask, a pattern mask, and the data caching method in which the trigger unit is located that match the caching requirements.

[0150] Further optionally, the structure and storage depth of the custom storage array are determined by the data caching method configured in the target trigger mode.

[0151] Further optionally, the trigger unit, setting the attribute parameters in the target trigger mode to configure a significant bit mask, a pattern mask, and the data caching method in which the trigger unit is located that match the caching requirements, is configured to:

[0152] Identify the data analysis type in the caching requirements; determine the data bits that need to be analyzed currently according to the data analysis type, the data type to which the input data belongs, and the historical analysis method, and generate a corresponding significant bit mask.

[0153] Further optionally, the trigger unit sets the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and the data caching method in which the trigger unit is located that match the cache requirement, and is configured to:

[0154] Determine the data transition form of the data to be observed in the cache requirement; the data transition form includes at least one of: data change value, data change trend, data change amplitude, data time sequence, and data repetition times; dynamically configure a corresponding mode mask according to the determined data transition form.

[0155] Further optionally, the data caching method is jointly determined by the data type to be analyzed and the time period in which the data is located; the trigger unit sets the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and the data caching method in which the trigger unit is located that match the cache requirement, and is configured to:

[0156] Determine the data type to be analyzed and the time period in which the data is located in the cache requirement; select a corresponding target data caching method from multiple pre-configured data caching methods according to the data type to be analyzed and the time period in which the data is located.

[0157] Further optionally, the trigger unit compares whether the data bit to be analyzed matches the mode mask to obtain a matching result of the data bit to be analyzed, and is configured to:

[0158] Detect the data value of the data bit to be analyzed in each clock cycle to determine whether there is a data bit to be analyzed that is the same as the data value indicated by the mode mask;

[0159] After detecting a data bit to be analyzed that is the same as the data value indicated by the mode mask, determine whether the repetition times and / or the occurrence order of the data values in the data bit to be analyzed are the same as the repetition times and / or the occurrence order of the data values indicated by the mode mask;

[0160] If the repetition times and / or the occurrence order of the data values in the data bit to be analyzed are the same as the mode mask, determine that the data bit to be analyzed matches the mode mask;

[0161] If no data bit to be analyzed that is the same as the data value indicated by the mode mask is detected, or the repetition times and / or the occurrence order of the data values in the data bit to be analyzed are different from the mode mask, the data bit to be analyzed does not match the mode mask.

[0162] Further optionally, multiple trigger modes for the ping-pong buffer are set in the trigger unit; the multiple trigger modes of the ping-pong buffer include: pre-trigger mode, middle-trigger mode, and post-trigger mode; the data caching method of the pre-trigger mode is: storing the first target data bits in the input data before the mode mask; the data caching method of the pre-trigger mode is: storing the second target data bits in the input data from before the mode mask to after the mode mask; the data caching method of the pre-trigger mode is: storing the third target data bits in the input data after the mode mask.

[0163] Further optionally, the trigger unit controls the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer, and is configured as:

[0164] After switching to the trigger mode in which the trigger unit is located, indicating the custom storage array and / or the ping-pong buffer to start the data writing process of the input data; and / or

[0165] If the data bit to be analyzed matches the mode mask, indicating the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits to be cached from the input data as the target input data.

[0166] Further optionally, the trigger unit indicating the custom storage array and / or the ping-pong buffer to start the data writing process of the input data is configured as:

[0167] After the trigger unit switches to the pre-trigger mode, generating a first write signal for enabling the data storage function;

[0168] Starting the data writing function of the ping-pong buffer through the first write signal;

[0169] Transmitting the input data to the ping-pong buffer in sequence according to the receiving order through the custom storage array;

[0170] The trigger unit, if the data bit to be analyzed matches the mode mask, indicating the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits to be cached from the input data as the target input data, is configured as:

[0171] After detecting that the data bit to be analyzed matches the mode mask in the custom storage array, generating a first stop signal for immediately stopping the data storage function;

[0172] The data writing function of the ping-pong buffer is turned off through the first stop signal, and the data transfer between the custom storage array and the ping-pong buffer is stopped, so that the target data bits stored in the ping-pong buffer are the first target data bits.

[0173] Further optionally, the trigger unit, which indicates the custom storage array and / or the ping-pong buffer to start the data writing process of the input data, is configured as:

[0174] After the trigger unit switches to the medium trigger mode, a first write signal for starting the data storage function is generated, and the data storage function of the custom storage array is started;

[0175] The data writing function of the ping-pong buffer is started through the first write signal;

[0176] The input data is sequentially transferred to the ping-pong buffer by the custom storage array in the received order;

[0177] The trigger unit, if the data bit to be analyzed matches the pattern mask, indicates the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits to be cached from the input data as the target input data, and is configured as:

[0178] After it is detected in the custom storage array that the data bit to be analyzed matches the pattern mask, according to the pre-configured storage rule, a second stop signal for stopping the data storage function after a preset clock cycle is generated; wherein, the number of preset clock cycles is determined by the preset number of bits to be stored after the pattern mask;

[0179] The data writing function of the ping-pong buffer is delayed from being turned off through the second stop signal, and the data transfer between the custom storage array and the ping-pong buffer is delayed from being stopped, so that the target data bits stored in the ping-pong buffer are the second target data bits.

[0180] Further optionally, the trigger unit, if the data bit to be analyzed matches the pattern mask, indicates the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits to be cached from the input data as the target input data, and is configured as:

[0181] After the trigger unit switches to the post-trigger mode, a first stop signal for immediately stopping the data storage function is generated;

[0182] The data writing function of the ping-pong buffer is turned off through the first stop signal;

[0183] After detecting that the data bit to be analyzed matches the pattern mask in the custom storage array, a second write signal for starting the data storage function is generated according to a pre-configured storage rule;

[0184] Start the data writing function of the ping-pong buffer through the second write signal;

[0185] Transmit the input data to the ping-pong buffer in sequence according to the reception order through the custom storage array;

[0186] After a preset clock cycle, generate the first stop signal; wherein, the number of preset clock cycles is determined by the preset number of bits to be stored after the pattern mask;

[0187] Close the data writing function of the ping-pong buffer through the first stop signal, and stop the data transmission between the custom storage array and the ping-pong buffer, so that the target data bit stored in the ping-pong buffer is the third target data bit.

[0188] Further optionally, the custom storage array and the ping-pong buffer in the trigger unit are set as a multi-level first-in first-out storage array FIFO; the FIFO depth and the number of layers corresponding to the custom storage array and the ping-pong buffer can be dynamically configured based on the trigger mode in which the trigger unit is located.

[0189] The system can implement various steps in the above method embodiments, which will not be elaborated here for the time being.

[0190] In the embodiment of the present application, by using an on-chip logic analyzer and through the cooperative control of the significant bit mask, the pattern mask, the custom storage array, and the ping-pong buffer, the trigger condition can be flexibly set according to specific analysis requirements, meeting different debugging and analysis scenarios, more accurately capturing the data related to the target event, improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization rate of storage resources, and further providing strong support for in-depth data analysis.

[0191] Please refer to Figure 4 , Figure 4 which is a schematic diagram of an embodiment of the electronic device provided by the embodiment of the present application. As Figure 4As shown in the figure, an embodiment of the present application provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored on the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, the following steps are implemented: obtaining input data to be processed through a trigger unit; marking corresponding data bits to be analyzed in the input data by using a significant digit mask; comparing whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer; controlling the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0192] Please refer to Figure 5 , Figure 5 which is a schematic diagram of an embodiment of a computer-readable storage medium provided by an embodiment of the present application. As Figure 5 shown, this embodiment provides a computer-readable storage medium 600, on which computer program information 611 is stored. When the computer program information 611 is executed by a processor, the following steps are implemented: obtaining input data to be processed through a trigger unit; marking corresponding data bits to be analyzed in the input data by using a significant digit mask; comparing whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate data flag bits corresponding to specific trigger events; the specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer; controlling the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0193] It should be noted that in the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0194] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0195] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present application.

[0196] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A data caching method for an on-chip logic analyzer, characterized in that The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer. The trigger unit at least includes a custom storage array. The method includes: Obtaining input data to be processed through the trigger unit. Multiple trigger modes for the ping-pong buffer are set in the trigger unit. The multiple trigger modes of the ping-pong buffer include: a pre-trigger mode, a mid-trigger mode, and a post-trigger mode. Using a significant bit mask to mark corresponding data bits to be analyzed in the input data. Comparing whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed. Among them, the pattern mask is used to indicate data flag bits corresponding to specific trigger events. The specific trigger events are associated with the data analysis process executed by the on-chip logic analyzer. Controlling the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer. Among them, after switching to the trigger mode in which the trigger unit is located, it is indicated that the custom storage array and / or the ping-pong buffer start the data writing process of the input data; and / or, if the data bits to be analyzed match the pattern mask, it is indicated that the ping-pong buffer starts or stops the data writing process of the input data, so as to extract target data bits that need to be cached from the input data as the target input data. Among them, the data caching method in the pre-trigger mode is: storing first target data bits in the input data that are before the pattern mask. The indicating that the custom storage array and / or the ping-pong buffer start the data writing process of the input data includes: after the trigger unit switches to the pre-trigger mode, generating a first write signal for starting the data storage function; starting the data writing function of the ping-pong buffer through the first write signal; and sequentially transmitting the input data to the ping-pong buffer through the custom storage array according to the reception order. The if the data bits to be analyzed match the pattern mask, indicating that the ping-pong buffer starts or stops the data writing process of the input data, so as to extract target data bits that need to be cached from the input data as the target input data includes: after detecting that the data bits to be analyzed match the pattern mask in the custom storage array, generating a first stop signal for immediately stopping the data storage function; closing the data writing function of the ping-pong buffer through the first stop signal, and stopping the data transmission between the custom storage array and the ping-pong buffer, so that the target data bits stored in the ping-pong buffer are the first target data bits.

2. The data caching method of the on-chip logic analyzer according to claim 1, wherein The trigger unit further includes a significant bit mask module. The using a significant bit mask to mark corresponding data bits to be analyzed in the input data includes: Through the significant bit mask module, using the significant bit mask to perform a covering process on the input data to cover invalid data bits in the input data and retain the data bits to be analyzed in the input data.

3. The data caching method of the on-chip logic analyzer according to claim 1, characterized in that, Before obtaining the input data to be processed through the trigger unit, it further includes: Select a target trigger mode that matches the caching requirement from multiple trigger modes configured by the trigger unit; wherein, the caching requirement is obtained based on a user input instruction; or the caching requirement is determined by data analysis of the on-chip logic analyzer; Set the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data caching method in which the trigger unit is located that match the caching requirement.

4. The data caching method of the on-chip logic analyzer according to claim 3, wherein The structure and storage depth of the custom storage array are determined by the data caching method configured in the target trigger mode.

5. The data caching method of the on-chip logic analyzer according to claim 3, characterized in that, The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data caching method in which the trigger unit is located that match the caching requirement includes: Identify the data analysis type in the caching requirement; Determine the data bits required for current analysis according to the data analysis type, the data type to which the input data belongs, and the historical analysis method, and generate a corresponding valid bit mask.

6. The data caching method of the on-chip logic analyzer according to claim 3, wherein The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data caching method in which the trigger unit is located that match the caching requirement includes: Determine the data transition form of the data to be observed in the caching requirement; the data transition form includes at least one of: data change value, data change trend, data change amplitude, data timing, data repetition count; Dynamically configure a corresponding mode mask according to the determined data transition form.

7. The data caching method of the on-chip logic analyzer according to claim 3, characterized in that The data caching method is jointly determined by the data type required for analysis and the time period in which the data is located; The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data caching method in which the trigger unit is located that match the caching requirement includes: Determine the data type required for analysis and the time period in which the data is located in the caching requirement; Select a corresponding target data caching method from multiple pre-configured data caching methods according to the data type required for analysis and the time period in which the data is located.

8. The data caching method of the on-chip logic analyzer according to claim 1, wherein The comparison of whether the data bits to be analyzed match the mode mask to obtain the matching result of the data bits to be analyzed includes: Detect the data value of the data bits to be analyzed in each clock cycle to determine whether there are data bits to be analyzed that are consistent with the data value indicated by the mode mask; After detecting the data bits to be analyzed that are consistent with the data value indicated by the mode mask, determine whether the repetition count and / or the order of occurrence of the data values in the data bits to be analyzed are the same as the repetition count and / or the order of occurrence of the data value indicated by the mode mask; If the repetition count and / or the order of occurrence of the data values in the data bits to be analyzed are the same as the mode mask, determine that the data bits to be analyzed match the mode mask; If no data bits to be analyzed that are consistent with the data value indicated by the mode mask are detected, or the repetition count and / or the order of occurrence of the data values in the data bits to be analyzed are different from the mode mask, the data bits to be analyzed do not match the mode mask.

9. The data caching method of the on-chip logic analyzer according to claim 1, wherein The data caching method in the pre-trigger mode is: storing the second target data bits in the input data from before the mode mask to after the mode mask; The data caching method in the pre-trigger mode is: storing the third target data bits in the input data after the mode mask.

10. The data caching method of the on-chip logic analyzer according to claim 9, characterized in that, The indication to enable the data writing process of the input data for the custom storage array and / or the ping-pong buffer includes: After the trigger unit switches to the mid-trigger mode, generating a first write signal for enabling the data storage function and starting the data storage function of the custom storage array; Starting the data writing function of the ping-pong buffer through the first write signal; Sequentially transmitting the input data to the ping-pong buffer in the received order through the custom storage array; If the data bit to be analyzed matches the mode mask, indicating to enable or stop the data writing process of the input data for the ping-pong buffer to extract the target data bits to be cached from the input data as the target input data, includes: After detecting that the data bit to be analyzed matches the mode mask in the custom storage array, generating a second stop signal for stopping the data storage function after a preset clock cycle according to the pre-configured storage rule; where the number of preset clock cycles is determined by the preset number of bits to be stored after the mode mask; Delaying the closing of the data writing function of the ping-pong buffer and delaying the stopping of the data transmission between the custom storage array and the ping-pong buffer through the second stop signal, so that the target data bits stored in the ping-pong buffer are the second target data bits.

11. The data caching method of the on-chip logic analyzer according to claim 9, wherein If the data bit to be analyzed matches the mode mask, indicating to enable or stop the data writing process of the input data for the ping-pong buffer to extract the target data bits to be cached from the input data as the target input data, includes: After the trigger unit switches to the post-trigger mode, generating a first stop signal for immediately stopping the data storage function; Closing the data writing function of the ping-pong buffer through the first stop signal; After detecting that the data bit to be analyzed matches the mode mask in the custom storage array, generating a second write signal for starting the data storage function according to the pre-configured storage rule; Starting the data writing function of the ping-pong buffer through the second write signal; Sequentially transmitting the input data to the ping-pong buffer in the received order through the custom storage array; Generating the first stop signal after a preset clock cycle; where the number of preset clock cycles is determined by the preset number of bits to be stored after the mode mask; Closing the data writing function of the ping-pong buffer and stopping the data transmission between the custom storage array and the ping-pong buffer through the first stop signal, so that the target data bits stored in the ping-pong buffer are the third target data bits.

12. The data caching method of the on-chip logic analyzer according to claim 1, characterized in that The custom storage array and the ping-pong buffer in the trigger unit are set as a multi-level first-in-first-out storage array FIFO; The FIFO depth and the number of layers corresponding to the custom storage array and the ping-pong buffer can be dynamically configured based on the trigger mode in which the trigger unit is located.

13. An on-chip logic analyzer, characterized in that, The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer. The trigger unit at least includes a custom storage array. Among them, The trigger unit is configured to obtain input data to be processed. Multiple trigger modes for the ping-pong buffer are set in the trigger unit. The multiple trigger modes of the ping-pong buffer include: a pre-trigger mode, a mid-trigger mode, and a post-trigger mode. The corresponding data bits to be analyzed are marked in the input data using a significant bit mask. Compare whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed. Among them, the pattern mask is used to indicate the data flag bits corresponding to specific trigger events. The specific trigger events are associated with the data analysis process performed by the on-chip logic analyzer. Control the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer. The ping-pong buffer is configured to receive the target input data input through the custom storage array. The trigger unit, according to the matching result and / or the data caching method in which the trigger unit is located, controls the data storage process of the custom storage array and the ping-pong buffer, so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer, and is configured to: after switching to the trigger mode in which the trigger unit is located, instruct the custom storage array and / or the ping-pong buffer to start the data writing process of the input data; and / or, if the data bits to be analyzed match the pattern mask, instruct the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits required for caching from the input data as the target input data. Among them, the data caching method in the pre-trigger mode is: store the first target data bits in the input data before the pattern mask. The trigger unit, instructing the custom storage array and / or the ping-pong buffer to start the data writing process of the input data, is configured to: after the trigger unit switches to the pre-trigger mode, generate a first write signal for enabling the data storage function; start the data writing function of the ping-pong buffer through the first write signal; and sequentially transmit the input data to the ping-pong buffer through the custom storage array according to the received order. The trigger unit, if the data bits to be analyzed match the pattern mask, instructs the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits required for caching from the input data as the target input data, and is configured to: after detecting that the data bits to be analyzed match the pattern mask in the custom storage array, generate a first stop signal for immediately stopping the data storage function; close the data writing function of the ping-pong buffer through the first stop signal, and stop the data transmission between the custom storage array and the ping-pong buffer, so that the target data bits stored in the ping-pong buffer are the first target data bits.

14. An electronic device, characterized in that, Including: A memory for storing computer software programs. A processor for reading and executing the computer software program, thereby implementing the data caching method of the on-chip logic analyzer according to any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer software program is stored in the storage medium, and when the computer software program is executed by the processor, it implements the data caching method of the on-chip logic analyzer according to any one of claims 1-12.

16. A chip, characterized in that, The computer software program and / or hardware unit is loaded in the chip, and the computer software program and / or hardware unit is used to implement the data caching method of the on-chip logic analyzer according to any one of claims 1-12.

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