Cascade LED drive control circuit capable of dormancy

Abstract

A cascade LED drive control circuit capable of dormancy comprises an all-digital clock extraction circuit used for performing frequency detection according to an input data input signal to generate a suitable frequency signal, and the frequency signal outputs a plurality of clock control signals related to a clock through numerical control oscillation and counting operation; the four-channel enable signal generation circuit generates a red channel enable signal, a green channel enable signal, a blue channel enable signal and a white channel enable signal; the four-channel serial-to-parallel signal generation circuit adjusts the brightness and color output control of a white light emitting diode chip, a red light emitting diode chip, a green light emitting diode chip and a blue light emitting diode chip in the LED driving circuit; the dormancy signal generation circuit controls the system to enter a dormancy state. According to the invention, the problem that a four-channel LED driving circuit capable of controlling and directly driving a white light LED at present supports a sleep instruction and turns off a global power supply to enter deep sleep under the condition that global sleep is needed is solved.

Description

Technical Field

[0001] The invention relates to the field of circuit design, and in particular to a dormant cascade LED drive control circuit. Background Art

[0002] The current single-line return-to-zero code LED driver control chip generally only supports three-channel RGB LED driving. In scenarios where low-power white light is required, the white light effect is achieved by mixing red, green, and blue LEDs. However, this RGB mixing method of producing white light usually requires precise matching of the driving currents of the red, green, and blue LEDs to obtain an effect close to that of pure white light. The process is complex and requires fine calibration and adjustment of different batches of LEDs to obtain uniform white light output. In addition, the efficiency of RGB mixed white light is usually lower than that of a single white light LED, and there is energy loss in the color mixing process, especially when the conversion efficiency between the red, green, and blue light sources is inconsistent.

[0003] From the above, it can be seen that in the current scenario where the single-line return-to-zero code LED driver control chip needs to use low-power white light, a four-channel LED driver circuit is proposed to directly drive the white light LED, avoiding the complexity and low energy efficiency brought by RGB mixed light. Therefore, a new technical solution of a dormant cascade LED driver control circuit is currently needed to control the four-channel LED driver circuit that directly drives the white light LED, while supporting dormancy instructions, and turning off the global power supply to enter deep dormancy when global dormancy is required. Summary of the invention

[0004] The present application provides a dormant cascade LED drive control circuit, which solves the problem that the current four-channel LED drive circuit can control the direct drive of white light LEDs, and supports dormancy instructions, and shuts down the global power supply to enter deep dormancy when global dormancy is required.

[0005] In order to solve the above problems, the present application provides a dormant cascade LED drive control circuit for controlling an LED drive circuit, comprising: a fully digital clock extraction circuit, a data identification and processing circuit, a four-channel enable signal generation circuit, a four-channel serial-to-parallel signal generation circuit, and a dormant signal generation circuit, wherein: The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal and generate a suitable frequency signal. The frequency signal outputs a plurality of clock control signals related to the clock through digital control oscillation and counting operations; the clock control signals related to the clock include a global start signal, a data clock 4-frequency division signal and a data clock 4-frequency division inverted signal; The data identification and processing circuit is used to receive a data input signal, a data clock divided-by-4 frequency signal and a reset signal in a cross-clock domain processing logic to generate a sampled data signal; The four-channel enable signal generating circuit is used to generate a red channel enable signal, a green channel enable signal, a blue channel enable signal and a white channel enable signal according to a received series of parallel circuit reset signals and a data clock 4-division inverted signal; The four-channel serial-to-parallel signal generating circuit is used to receive a sampling data signal, a data clock 4-frequency division signal, a data input signal, a power reset signal, and a red channel enable signal, a green channel enable signal, a blue channel enable signal, and a white channel enable signal, and generate a red channel parallel signal, a green channel parallel signal, a blue channel parallel signal, and a white channel parallel signal to send to the LED driving circuit to adjust the brightness and color output control of the white light emitting diode chip, the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip in the LED driving circuit; The sleep signal generating circuit is used to generate a sleep control signal through logic operation according to the rising edge of the received data clock 4-frequency division signal and the sleep signal, thereby controlling the LED driving circuit to enter a sleep state.

[0006] Furthermore, the above circuit may also include: the all-digital clock extraction circuit includes a differential frequency detector, a digitally controlled oscillator and a counter, The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal and generate a suitable frequency signal. The frequency signal outputs multiple clock-related clock control signals through digitally controlled oscillation and counting operations, specifically: the all-digital clock extraction circuit performs frequency detection according to the data input signal through a differential frequency detector, generates a suitable frequency signal with the data clock signal or the data clock inversion signal, and then transmits it to the digitally controlled oscillator; the digitally controlled oscillator generates a corresponding control signal according to the output of the differential frequency detector and transmits it to the counter; the counter generates a global start signal, a data clock 2-division signal and a data clock 4-division signal, as well as a data clock 2-division inversion signal and a data clock 4-division inversion signal through the received control signal.

[0007] Furthermore, the above circuit may also include: a frame-breaking signal generating circuit, the frame-breaking signal generating circuit is used to generate a frame-breaking signal for resetting the system when a data frame error occurs through the received LED driving clock signal, the LED driving clock 5-frequency division signal, the data input signal and the power reset signal; the frame-breaking signal generating circuit includes a frame-breaking signal generating circuit_not gate, a frame-breaking signal generating circuit_AND gate, four frame-breaking signal generating circuit_D flip-flops and a frame-breaking signal generating circuit_AND gate, the LED driving clock 5-frequency division signal is used as the clock input signal of the four frame-breaking signal generating circuit_D flip-flops to drive the flip-flops, After the data input signal and the power reset signal generate a signal as the reset signal of the first frame break signal generating circuit_D flip-flop through the frame break signal generating circuit_AND gate, the output of the first frame break signal generating circuit_D flip-flop is used as the input of the second frame break signal generating circuit_D flip-flop, and so on... Four frame break signal generating circuit_D flip-flops are connected in series in sequence to form a cascade structure; the outputs of the four frame break signal generating circuit_D flip-flops are connected to a frame break signal generating circuit_AND gate, and the frame break signal generating circuit_AND gate outputs a frame break signal; wherein, the LED drive clock signal and the LED drive clock 5-division frequency signal are used for synchronous drive control, and the power reset signal is used for initialization when the system is powered on or reset.

[0008] Furthermore, the above circuit may also include: a single-bit reset signal generating circuit, the single-bit reset signal generating circuit is used to generate a single-bit reset signal for system reset control after logical operation processing based on the received broken frame signal, power reset signal, data clock signal, data clock 2-frequency inversion signal and data clock 4-frequency signal; the single-bit reset signal generating circuit includes a single-bit reset signal generating circuit_NOT gate, a single-bit reset signal generating circuit_AND gate, and two single-bit reset signal generating circuit_NOT gates; wherein, the broken frame signal passes through the single-bit reset signal generating circuit_NOT gate to obtain an inverted signal, and the inverted signal is input into the first single-bit reset signal generating circuit. The power reset signal is directly input into one input end of the first single-bit reset signal generating circuit_NAND gate, and the power reset signal is directly input into the other input end of the first single-bit reset signal generating circuit_NAND gate; after the data clock signal and the data clock 2-division inverted signal are processed by the single-bit reset signal generating circuit_AND gate, the obtained signal is input into the second single-bit reset signal generating circuit_NAND gate, and at the same time, the data clock 4-division signal is also input into the second single-bit reset signal generating circuit_NAND gate, and the output signal of the second single-bit reset signal generating circuit_NAND gate is used as the third input of the first single-bit reset signal generating circuit_NAND gate, and finally the first single-bit reset signal generating circuit_NAND gate outputs a single-bit reset signal.

[0009] Furthermore, the above-mentioned circuit may also include: a holding signal processing circuit, the holding signal processing circuit is used to generate an output holding signal for maintaining the circuit state after a logical operation based on the received single-bit reset signal, the data clock inversion signal, the data clock 2-division signal and the data clock 2-division inversion signal; the holding signal processing circuit includes a holding signal processing circuit_NOR gate and three holding signal processing circuit_NAND gates, wherein the data clock inversion signal and the data clock 2-division inversion signal are processed by the holding signal processing circuit_NOR gate to generate an output signal, and the output signal is connected to one input end of the holding signal processing circuit_NAND gate, and the single-bit reset signal is connected to the other input end of the holding signal processing circuit_NAND gate. After forming a feedback loop, an SR latch is formed, and finally a holding signal is output.

[0010] Furthermore, the above-mentioned circuit may also include: a resume transmission start signal generating circuit, the resume transmission start signal generating circuit is used to generate a resume transmission start signal for indicating the start of data resume transmission and a serial-to-parallel circuit reset signal through the received power reset signal and the frame break signal; wherein, the resume transmission start signal generating circuit includes a first resume transmission signal generating circuit_inverter, a resume transmission signal generating circuit_AND gate, a resume transmission signal generating circuit_D flip-flop, a second resume transmission signal generating circuit_inverter, and a resume transmission signal generating circuit_NAND gate; the power reset signal POR After passing through the first resume signal generating circuit_inverter, an inverted output signal is obtained, and the inverted output signal is input into the resume signal generating circuit_AND gate together with the broken frame signal SYS_RST to generate a new control signal; the output of the resume signal generating circuit_AND gate is used as the input of the resume signal generating circuit_D flip-flop, the resume signal generating circuit_D flip-flop is controlled by the clock signal, and the output Q end of the resume signal generating circuit_D flip-flop generates a resume start signal, and the resume start signal passes through the second resume signal generating circuit_inverter and is input into the resume signal generating circuit_NAND gate together with the broken frame signal, and finally generates a serial-to-parallel circuit reset signal.

[0011] Furthermore, the above-mentioned circuit may also include: a data retransmission processing circuit, which is used to generate a retransmission data output signal through the received hold signal, data input signal, sampled data, global start signal and retransmission start signal; wherein, the data retransmission processing circuit includes a retransmission processing circuit_three-input NOR gate, a retransmission processing circuit_NAND gate, a retransmission processing circuit_inverter, and a retransmission processing circuit_NAND gate; the retransmission processing circuit_three-input NOR gate processes the received hold signal, data input signal and sampled data signal, and outputs the inverted result to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate also receives the global start signal and outputs it to the retransmission processing circuit_inverter; the retransmission processing circuit_inverter inverts the obtained signal to generate a retransmission start signal, and passes it to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate generates a retransmission data output signal.

[0012] Furthermore, the above-mentioned circuit may also include: a wake-up signal generating circuit, the wake-up signal generating circuit is used to receive a broken frame signal and a power reset signal, and generate a wake-up control signal for restoring the system from a low power consumption state; wherein, after receiving the data input signal, the wake-up signal generating circuit determines whether there is a broken frame signal, and if there is a broken frame signal, the system is reset; if there is no broken frame signal, it is determined whether it is a single-bit reset signal and cached; then it is determined whether the LED driving circuit is in a sleep state, and if so, the wake-up signal is triggered to wake up the LED driving circuit and restore the normal working state; if the LED driving circuit is not in a sleep state, a data recognition operation is performed, and after data recognition, it is determined whether the input signal is a sleep instruction, and if so, the LED driving circuit is put into a sleep state; if not, the LED driving circuit continues to be displayed and driven; after completing the display drive, the data transmission stage is entered to process subsequent data input signals to realize the control of the LED driving circuit and power consumption control.

[0013] Furthermore, the above-mentioned circuit may also include: the data identification and processing circuit includes a data identification and processing circuit_D trigger, the data clock 4-division signal serves as the clock input signal of the data identification and processing circuit_D trigger, the data input signal serves as the D-end input signal of the data identification and processing circuit_D trigger, and the single-bit reset signal serves as the reset control signal of the data identification and processing circuit_D trigger; when the clock signal arrives, the data identification and processing circuit_D trigger performs output control according to the D-end input state, and finally outputs the sampled data signal.

[0014] Through the above scheme, the present application is applied, and a sleep signal is generated through a sleep signal generation circuit to allow the LED drive circuit to enter a sleep mode, greatly reducing the overall power consumption of the LED drive circuit, and at the same time shutting down the output of the LED drive circuit to avoid unnecessary power loss in the sleep state; and a wake-up signal is generated through a wake-up signal generation circuit to wake up the LED drive circuit from the sleep state, ensuring that the LED drive circuit can quickly recover from the sleep mode when needed. The present application is different from the traditional single-point single-pass LED control protocol and supports a four-channel LED control protocol. Through a four-channel enable signal generation circuit, the circuit receives independent control signals of the red, green, blue, and white (RGBW) channels, which are composed of logic gates and control devices to generate a red channel enable signal (RED_8-BIT_SELECT), a green channel enable signal (GREEN_8-BIT_SELECT), a blue channel enable signal (BLUE_8-BIT_SELECT), and a white channel enable signal (WHITE_8-BIT_SELECT). The four-channel serial-to-parallel signal generation circuit converts serial data into parallel signals to drive RGBW LEDs for more precise independent control, especially in single white light scenarios, where only white LEDs emit light, avoiding the energy efficiency loss of RGB mixed light. At the same time, the input data is frequency detected and divided by a fully digital clock extraction circuit to provide a stable clock signal to ensure the synchronization of each module. The differential frequency detector, digitally controlled oscillator, and counter circuits work together to generate a global start signal and multiple divided clock signals, which are used for timing control of each module to ensure the stable operation of the LED drive circuit in different states. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a schematic structural diagram of the dormant cascade LED driving control circuit 10 controlling the LED driving circuit 20 of the present application; Figure 2 Shown is a schematic structural diagram of a dormant cascade LED drive control circuit of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0017] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0018] like Figure 1 The structure diagram of the dormant cascade LED driving control circuit 10 controlling the LED driving circuit 20 of the present application is shown in FIG. Figure 2 The present application shows a dormant cascade LED drive control circuit, which is used to control an LED drive circuit and may include: a full digital clock extraction circuit 101, a single-bit reset signal generation circuit 104, a hold signal processing circuit 105, a data identification processing circuit 108, a data retransmission processing circuit 109, a frame break signal generation circuit 102, a retransmission start signal generation circuit 106, a four-channel enable signal generation circuit 111, a four-channel serial-to-parallel signal generation circuit 110, a dormancy signal generation circuit 103, and a wake-up signal generation circuit 107, wherein: The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal and generate a suitable frequency signal. The frequency signal outputs a plurality of clock control signals related to the clock through digital control oscillation and counting operations; the clock control signals related to the clock include a global start signal, a data clock 2-frequency division signal and a data clock 4-frequency division signal, as well as a data clock 2-frequency division inversion signal and a data clock 4-frequency division inversion signal; Specifically, the all-digital clock extraction circuit includes a differential frequency detector, a digitally controlled oscillator and a counter. The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal and generate a suitable frequency signal. The frequency signal outputs multiple clock control signals related to the clock through digital controlled oscillation and counting operations. Specifically, the all-digital clock extraction circuit performs frequency detection according to the data input signal through a differential frequency detector, generates a suitable frequency signal with the data clock signal or the data clock inversion signal, and transmits it to the digital controlled oscillator; the digital controlled oscillator generates a corresponding control signal according to the output of the differential frequency detector and transmits it to the counter; the counter generates a global start signal, a data clock 2-division signal (OSC_DATA_DIV2) and a data clock 4-division signal (OSC_DATA_DIV4), as well as a data clock 2-division inversion signal (OSC_DATA_DIV2_N) and a data clock 4-division inversion signal (OSC_DATA_DIV4_N) through the received control signal. The data input signal is frequency detected and divided by the all-digital clock extraction circuit to provide a stable clock signal and ensure the synchronization of each module. The differential frequency detector (DFD), numerically controlled oscillator (NCO), counter and other circuits work together to generate a global start signal (OSC_DATA_EN) and multiple divided clock signals (such as OSC_DATA_DIV2 and OSC_DATA_DIV4). These signals are used for timing control of each circuit module to ensure stable operation of the system in different states.

[0019] The frame-break signal generating circuit is used to generate a frame-break signal (SYS_RST) for resetting the system when a data frame error occurs through the received LED driving clock signal (OSC_PWM), the LED driving clock 5-frequency division signal (OSC_PWM_DIV5), the data input signal (DIN) and the power reset signal (POR); the frame-break signal generating circuit includes a frame-break signal generating circuit_NOT gate, a frame-break signal generating circuit_AND gate, four frame-break signal generating circuit_D flip-flops and a frame-break signal generating circuit_NOT gate. The LED driving clock 5-frequency division signal is used as the inverted signal generated by the frame-break signal generating circuit_NOT gate as the clock input signal of the four frame-break signal generating circuit_D flip-flops. , driving the flip-flop, the data input signal and the power reset signal are used as the reset signal of the first frame-break signal generating circuit_D flip-flop through the frame-break signal generating circuit_AND gate, and the output of the first frame-break signal generating circuit_D flip-flop is used as the input of the second frame-break signal generating circuit_D flip-flop, and so on... Four frame-break signal generating circuit_D flip-flops are connected in series in sequence to form a cascade structure; the outputs of the four frame-break signal generating circuit_D flip-flops are connected to a frame-break signal generating circuit_AND gate, and the frame-break signal generating circuit_AND gate outputs a frame-break signal; wherein, the LED driving clock signal and the LED driving clock 5-frequency division signal are used for synchronous driving control, and the power reset signal is used for initialization when the system is powered on or reset. The frame-break signal generating circuit can ensure that the system is reset and controlled when the input data frame is wrong, thereby improving the stability and fault tolerance of the system.

[0020] The single-bit reset signal generating circuit is used to generate a single-bit reset signal for system reset control after logic operation processing according to the received broken frame signal, power reset signal, data clock signal, data clock 2-division inverted signal and data clock 4-division signal; the single-bit reset signal generating circuit includes a single-bit reset signal generating circuit_not gate, a single-bit reset signal generating circuit_AND gate, and two single-bit reset signal generating circuit_NAND gates; wherein, the broken frame signal (SYS_RST) passes through the single-bit reset signal generating circuit_not gate to obtain an inverted signal, and the inverted signal is input to one input end of the first single-bit reset signal generating circuit_NAND gate, and the power reset signal (POR) is directly input to the other input end of the first single-bit reset signal generating circuit_NAND gate; the data clock signal (OSC_DATA) and the data clock 2-division inverted signal (OSC_DATA_DIV2_N) After being processed by the single-bit reset signal generating circuit_AND gate, the obtained signal is input into the second single-bit reset signal generating circuit_NAND gate, and the data clock 4-division signal (OSC_DATA_DIV4) is also input into the second single-bit reset signal generating circuit_NAND gate. The output signal of the second single-bit reset signal generating circuit_NAND gate is used as the third input of the first single-bit reset signal generating circuit_NAND gate, and finally the first single-bit reset signal generating circuit_NAND gate outputs a single-bit reset signal (BIT_RST). The single-bit reset signal generating circuit can process the reset signal in the cross-clock domain processing logic, reset the related circuits, ensure the synchronization and reliability of the sampling process, and improve the stability and fault tolerance of the system.

[0021] The holding signal processing circuit is used to generate and output a holding signal (SR_LATCH_Q) for holding the circuit state according to the received single-bit reset signal (BIT_RST), data clock inversion signal (OSC_DATA_N), data clock 2-division signal (OSC_DATA_DIV2) and data clock 2-division inversion signal (OSC_DATA_DIV2_N) through logical operation; the holding signal processing circuit includes a holding signal processing circuit_NOR gate and three holding signal processing circuit_NAND gates, wherein the data clock inversion signal (OSC_DATA_N) and the data clock 2-division inversion signal (OSC_DATA_DIV2_N) are processed by the holding signal processing circuit_NOR gate to generate an output signal, the output signal is connected to one input end of the holding signal processing circuit_NAND gate, the single-bit reset signal is connected to the other input end of the holding signal processing circuit_NAND gate, after forming a feedback loop, an SR latch (set / reset latch) is formed, and finally the holding signal (SR_LATCH_Q) is output. The hold signal processing circuit realizes the logic control and hold function of the input signal through the combination of logic gates to ensure the stability of the hold signal.

[0022] The data identification and processing circuit is used to receive the data input signal, the data clock 4-frequency signal and the reset signal (i.e., the single-bit reset signal) in the cross-clock domain processing logic to generate the sampled data signal; specifically, the data input signal is the main data source, the data clock 4-frequency signal provides the sampling timing, and the single-bit reset signal is used to reset the relevant circuit to ensure the synchronization and reliability of the sampling process. After processing these input signals, the data identification and processing circuit generates a sampled data signal (CODE_TRAC_SAMP_SDAT); the data identification and processing circuit includes a data identification and processing circuit_D flip-flop, and the input of the data identification and processing circuit includes a data clock 4-frequency signal (OSC_DATA_DIV4), a data input signal (DIN) and a single-bit reset signal (BIT_RST). The data clock 4-frequency signal (OSC_DATA_DIV4) is used as the clock input signal of the flip-flop, the data input signal (DIN) is used as the D-end input signal, and the single-bit reset signal (BIT_RST) is used as the reset control signal of the flip-flop. When the clock signal arrives, the D flip-flop performs output control according to the D-end input state, and finally outputs the sampled data signal. The above arrangement improves the accuracy of the whole system in processing the sampling data, while ensuring the synchronization and reliability of the sampling process, and improving the stability and reliability of the system.

[0023] The resume transmission start signal generating circuit is used to generate a resume transmission start signal (GET_DATA) indicating the start of data resume transmission and a serial-to-parallel circuit reset signal (GET_DATA_EN) through the received power reset signal (POR) and the frame break signal (SYS_RST); wherein the resume transmission start signal generating circuit includes a first resume transmission signal generating circuit_inverter, a resume transmission signal generating circuit_AND gate, a resume transmission signal generating circuit_D flip-flop, a second resume transmission signal generating circuit_inverter, and a resume transmission signal generating circuit_NAND gate; the power reset signal POR passes through the first resume transmission signal generating circuit_inverter to obtain an inverted output signal, and the inverted output signal is inverted with the frame break signal SYS_RST After inputting the resume signal generation circuit_AND gate together, a new control signal is generated; the output of the resume signal generation circuit_AND gate is used as the input of the resume signal generation circuit_D flip-flop, the resume signal generation circuit_D flip-flop is controlled by the clock signal, and the output Q end of the resume signal generation circuit_D flip-flop generates a resume start signal, which is input into the resume signal generation circuit_NAND gate together with the frame break signal after passing through the second resume signal generation circuit_inverter, and finally generates a serial-to-parallel circuit reset signal. The resume start signal generation circuit can ensure the continuity of the system's processing of input data, and can also perform reset control on the system, thereby improving the stability and fault tolerance of the system.

[0024] The data retransmission processing circuit is used to generate a retransmission data output signal (DOUT) through the received hold signal (SR_LATCH_Q), data input signal (DIN), sampled data (CODE_TRAC_SAMP_SDAT), global start signal (OSC_DATA_EN) and retransmission start signal (GET_DATA); wherein, the data retransmission processing circuit includes a retransmission processing circuit_three-input NOR gate, a retransmission processing circuit_NAND gate, a retransmission processing circuit_inverter, and a retransmission processing circuit_NAND gate; the retransmission processing circuit_three-input NOR gate processes the received hold signal, data input signal and sampled data signal, and outputs the inverted result to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate also receives the global start signal and outputs it to the retransmission processing circuit_inverter; the retransmission processing circuit_inverter inverts the obtained signal to generate a retransmission start signal, and transmits it to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate generates a retransmission data output signal. The data transmission processing circuit can ensure the continuity of the system's data processing and improve the system efficiency.

[0025] The four-channel enable signal generating circuit is used to generate a red channel enable signal, a green channel enable signal, a blue channel enable signal and a white channel enable signal according to a received series of parallel circuit reset signals and a data clock 4-division inverted signal; The four-channel serial-to-parallel signal generating circuit is used to receive a sampling data signal, a data clock 4-frequency division signal, a data input signal, a power reset signal, and a red channel enable signal, a green channel enable signal, a blue channel enable signal, and a white channel enable signal, and generate a red channel parallel signal, a green channel parallel signal, a blue channel parallel signal, and a white channel parallel signal to send to the LED driving circuit to adjust the brightness and color output control of the white light emitting diode chip, the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip in the LED driving circuit.

[0026] White light emitting diode chips use phosphor coating technology, which can convert electrical energy into white light more directly, so they are more energy efficient.

[0027] This application is different from the traditional single-point single-pass LED control protocol and supports a four-channel LED control protocol. Through a four-channel enable signal generation circuit, the four-channel enable signal generation circuit receives independent control signals for the red, green, blue, and white (RGBW) channels, and is composed of a combination of logic gates and control devices to generate a red channel enable signal (RED_8-BIT_SELECT), a green channel enable signal (GREEN_8-BIT_SELECT), a blue channel enable signal (BLUE_8-BIT_SELECT), and a white channel enable signal (WHITE_8-BIT_SELECT). The four-channel serial-to-parallel signal generation circuit converts serial data into parallel signals to drive the RGBW LED to achieve more precise independent control, especially in a single white light scenario, where only the white LED emits light, avoiding the energy efficiency loss of RGB mixed light.

[0028] The sleep signal generating circuit is used to generate a sleep control signal through logic operation according to the rising edge of the received data clock 4-frequency division signal and the sleep signal, thereby controlling the LED driving circuit to enter a sleep state.

[0029] The wake-up signal generating circuit is used to receive the broken frame signal and the power reset signal, and generate the wake-up control signal for restoring the system from the low power consumption state; wherein, after receiving the data input signal (DIN), the wake-up signal generating circuit determines whether there is a broken frame signal, and if there is a broken frame signal, the system is reset; if there is no broken frame signal, it is determined whether it is a single-bit reset signal and cached; then it is determined whether the LED driving circuit is in the sleep state, and if so, the wake-up signal is triggered to wake up the LED driving circuit and restore the normal working state; if it is not in the sleep state, a data recognition operation is performed, and after data recognition, it is determined whether the input signal is a sleep instruction, and if so, the LED driving circuit is put into the sleep state; if not, the LED driving circuit is continued to be displayed; after completing the display driving, the data retransmission stage is entered to process the subsequent data input signal to realize the control of the LED driving circuit and the power consumption control.

[0030] The above settings, through the sleep signal generation circuit, when receiving the 0x000000 instruction passed in by DIN, generate a sleep signal, so that the LED driver circuit enters the sleep mode, greatly reducing the overall power consumption of the LED driver circuit, and turning off the LED output to avoid unnecessary power loss in the sleep state. The sleep signal generation circuit is processed by multiple input signals such as the data clock 4-frequency division signal rising edge signal (OSC_DATA_DIV4_SP_CLK), sleep signal (SELECT_000000), power reset signal (POR), and frame break signal (SYS_RST) through NAND gates and logic gates to realize the generation of sleep signals.

[0031] The wake-up signal generation circuit generates a wake-up signal to wake up the LED driver circuit from sleep mode when receiving the wake-up command from DIN. The wake-up signal generation circuit generates a wake-up signal by receiving the power reset signal (POR) and the frame break signal (SYS_RST) and combining it with the NAND gate logic processing to ensure that the LED driver circuit can quickly recover from sleep mode when needed.

[0032] In the present application, each preferred scheme only focuses on describing the differences from other preferred schemes. As long as the preferred schemes do not conflict, they can be combined arbitrarily. The embodiments formed by the combination are also within the scope disclosed in this specification. Considering the simplicity of the text, this article will no longer separately describe the embodiments formed by the combination.

[0033] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0034] In this document, each preferred scheme only focuses on describing the differences from other preferred schemes. As long as the preferred schemes do not conflict, they can be combined arbitrarily. The embodiments formed by the combination are also within the scope disclosed in this specification. Considering the simplicity of the text, this document will no longer separately describe the embodiments formed by the combination.

[0035] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A dormant cascade LED drive control circuit, used to control an LED drive circuit, It is characterized in that It includes: a full digital clock extraction circuit, a data identification and processing circuit, a four-channel enable signal generation circuit, a four-channel serial-to-parallel signal generation circuit and a sleep signal generation circuit, wherein: The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal and generate a suitable frequency signal. The frequency signal outputs a plurality of clock control signals related to the clock through digital control oscillation and counting operations; the clock control signals related to the clock include a global start signal, a data clock 4-frequency division signal and a data clock 4-frequency division inverted signal; The data identification and processing circuit is used to receive a data input signal, a data clock divided-by-4 frequency signal and a reset signal in a cross-clock domain processing logic to generate a sampled data signal; The four-channel enable signal generating circuit is used to generate a red channel enable signal, a green channel enable signal, a blue channel enable signal and a white channel enable signal according to a received series of parallel circuit reset signals and a data clock 4-division inverted signal; The four-channel serial-to-parallel signal generating circuit is used to receive a sampling data signal, a data clock 4-frequency division signal, a data input signal, a power reset signal, and a red channel enable signal, a green channel enable signal, a blue channel enable signal, and a white channel enable signal, and generate a red channel parallel signal, a green channel parallel signal, a blue channel parallel signal, and a white channel parallel signal to send to the LED driving circuit to adjust the brightness and color output control of the white light emitting diode chip, the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip in the LED driving circuit; The sleep signal generating circuit is used to generate a sleep control signal through logic operation according to the rising edge of the received data clock 4-frequency division signal and the sleep signal, thereby controlling the LED driving circuit to enter a sleep state.

2. The dormant cascade LED drive control circuit according to claim 1, characterized in that: Also includes: The all-digital clock extraction circuit includes a differential frequency detector, a digitally controlled oscillator and a counter. The all-digital clock extraction circuit is used to perform frequency detection according to the input data input signal, generate a suitable frequency signal, and the frequency signal outputs multiple clock control signals related to the clock through digital controlled oscillation and counting operations, specifically: the all-digital clock extraction circuit performs frequency detection according to the data input signal through a differential frequency detector, generates a suitable frequency signal with the data clock signal or the data clock inversion signal, and transmits it to the digital controlled oscillator; The digitally controlled oscillator generates a corresponding control signal according to the output of the differential frequency detector and transmits it to the counter; the counter generates a global start signal, a data clock divided-by-2 signal and a data clock divided-by-4 signal, as well as a data clock divided-by-2 inverted signal and a data clock divided-by-4 inverted signal through the received control signal.

3. The dormant cascade LED driving control circuit according to claim 2, characterized in that: It also includes a frame-breaking signal generating circuit, which is used to generate a frame-breaking signal for resetting the system when a data frame error occurs through the received LED driving clock signal, the LED driving clock 5-frequency division signal, the data input signal and the power reset signal; the frame-breaking signal generating circuit includes a frame-breaking signal generating circuit_not gate, a frame-breaking signal generating circuit_AND gate, four frame-breaking signal generating circuit_D flip-flops and a frame-breaking signal generating circuit_AND-NAND gate. The LED driving clock 5-frequency division signal is used as the inverted signal generated by the frame-breaking signal generating circuit_not gate, which is used as the clock input signal of the four frame-breaking signal generating circuit_D flip-flops to drive the flip-flops. The data input signal After the signal and the power reset signal are generated by the frame-break signal generating circuit_AND gate as the reset signal of the first frame-break signal generating circuit_D flip-flop, the output of the first frame-break signal generating circuit_D flip-flop is used as the input of the second frame-break signal generating circuit_D flip-flop, and so on... Four frame-break signal generating circuit_D flip-flops are connected in series in sequence to form a cascade structure; the outputs of the four frame-break signal generating circuit_D flip-flops are connected to a frame-break signal generating circuit_AND gate, and the frame-break signal generating circuit_AND gate outputs a frame-break signal; wherein, the LED drive clock signal and the LED drive clock 5-division signal are used for synchronous drive control, and the power reset signal is used for initialization when the system is powered on or reset.

4. The dormant cascade LED drive control circuit according to claim 3, characterized in that: It also includes a single-bit reset signal generating circuit, which is used to generate a single-bit reset signal for system reset control after logical operation processing based on the received frame-breaking signal, power reset signal, data clock signal, data clock 2-frequency inversion signal and data clock 4-frequency signal; the single-bit reset signal generating circuit includes a single-bit reset signal generating circuit_not gate, a single-bit reset signal generating circuit_AND gate, and two single-bit reset signal generating circuits_NAND gates; wherein the frame-breaking signal passes through the single-bit reset signal generating circuit_not gate to obtain an inverted signal, and the inverted signal is input into the first single-bit reset signal generating circuit The power reset signal is directly input into the other input end of the first single-bit reset signal generating circuit_NAND gate; after the data clock signal and the data clock 2-frequency inverted signal are processed by the single-bit reset signal generating circuit_AND gate, the obtained signal is input into the second single-bit reset signal generating circuit_NAND gate, and at the same time, the data clock 4-frequency signal is also input into the second single-bit reset signal generating circuit_NAND gate, and the output signal of the second single-bit reset signal generating circuit_NAND gate is used as the third input of the first single-bit reset signal generating circuit_NAND gate, and finally the first single-bit reset signal generating circuit_NAND gate outputs a single-bit reset signal.

5. The dormant cascade LED driving control circuit according to claim 4, characterized in that: It also includes a holding signal processing circuit, which is used to generate an output holding signal for maintaining the circuit state after a logic operation based on the received single-bit reset signal, the data clock inversion signal, the data clock 2-division signal and the data clock 2-division inversion signal; the holding signal processing circuit includes a holding signal processing circuit_NOR gate and three holding signal processing circuits_NAND gates, wherein the data clock inversion signal and the data clock 2-division inversion signal are processed by the holding signal processing circuit_NOR gate to generate an output signal, and the output signal is connected to one input end of the holding signal processing circuit_NAND gate, and the single-bit reset signal is connected to the other input end of the holding signal processing circuit_NAND gate. After forming a feedback loop, an SR latch is formed, and finally a holding signal is output.

6. The dormant cascade LED drive control circuit according to claim 5, characterized in that: It also includes a resume transmission start signal generating circuit, which is used to generate a resume transmission start signal for indicating the start of data resume transmission and a serial-to-parallel circuit reset signal through the received power reset signal and the frame break signal; Among them, the resume start signal generating circuit includes a first resume signal generating circuit_inverter, a resume signal generating circuit_AND gate, a resume signal generating circuit_D flip-flop, a second resume signal generating circuit_inverter, and a resume signal generating circuit_NAND gate; the power reset signal POR passes through the first resume signal generating circuit_inverter to obtain an inverted output signal, and the inverted output signal is input into the resume signal generating circuit_AND gate together with the frame break signal SYS_RST to generate a new control signal; the output of the resume signal generating circuit_AND gate is used as the input of the resume signal generating circuit_D flip-flop, the resume signal generating circuit_D flip-flop is controlled by the clock signal, and the output Q end of the resume signal generating circuit_D flip-flop generates a resume start signal, and the resume start signal passes through the second resume signal generating circuit_inverter and is input into the resume signal generating circuit_NAND gate together with the frame break signal, and finally generates a serial-to-parallel circuit reset signal.

7. The dormant cascade LED driving control circuit according to claim 6, characterized in that: It also includes a data retransmission processing circuit, which is used to generate a retransmission data output signal through the received hold signal, data input signal, sampled data, global start signal and retransmission start signal; wherein, the data retransmission processing circuit includes a retransmission processing circuit_three-input NOR gate, a retransmission processing circuit_NAND gate, a retransmission processing circuit_inverter, and a retransmission processing circuit_NAND gate; the retransmission processing circuit_three-input NOR gate processes the received hold signal, data input signal and sampled data signal, and outputs the inverted result to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate also receives the global start signal and outputs it to the retransmission processing circuit_inverter; the retransmission processing circuit_inverter inverts the obtained signal to generate a retransmission start signal, and passes it to the retransmission processing circuit_NAND gate, and the retransmission processing circuit_NAND gate generates a retransmission data output signal.

8. The dormant cascade LED driving control circuit according to claim 7, characterized in that: It also includes a wake-up signal generating circuit, which is used to receive a broken frame signal and a power reset signal to generate a wake-up control signal for restoring the system from a low power consumption state; wherein, after receiving the data input signal, the wake-up signal generating circuit determines whether there is a broken frame signal, and if there is a broken frame signal, the system is reset; if there is no broken frame signal, it is determined whether it is a single-bit reset signal and cached; then it is determined whether the LED driving circuit is in a dormant state, and if so, the wake-up signal is triggered to wake up the LED driving circuit and restore the normal working state; if the LED driving circuit is not in a dormant state, a data recognition operation is performed, and after data recognition, it is determined whether the input signal is a dormant instruction, and if so, the LED driving circuit is put into a dormant state; if not, the LED driving circuit continues to be displayed; after completing the display drive, the data transmission stage is entered to process subsequent data input signals to realize the control of the LED driving circuit and power consumption control.

9. The dormant cascade LED driving control circuit according to claim 8, characterized in that: Further including: the data identification and processing circuit includes a data identification and processing circuit_D trigger, the data clock 4-division signal is used as the clock input signal of the data identification and processing circuit_D trigger, the data input signal is used as the D-end input signal of the data identification and processing circuit_D trigger, and the single-bit reset signal is used as the reset control signal of the data identification and processing circuit_D trigger; when the clock signal arrives, the data identification and processing circuit_D trigger performs output control according to the D-end input state, and finally outputs the sampled data signal.

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