SiC VDMOSFET structure with high heat dissipation performance and preparation method thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with high heat dissipation performance, which comprises a plurality of MOS cells arranged in parallel, and is characterized in that each MOS cell comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate oxide layer covering the surface of the metal source electrode, performing ion implantation in the semiconductor epitaxial layer to form an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer and a P well layer; source electrode doping layers are arranged on the two sides of a single MOS cell, the source electrode doping layers are in ohmic contact with the metal source electrodes, and the source electrode doping layers are made of gallium arsenide or gallium nitride or nichrome. According to the invention, the source electrode doping layer with the sinking design is arranged above the MOS cell, so that the N well layer can be in direct contact with the metal source electrode, and the N well layer can be in indirect contact with the metal source electrode through the source electrode doping layer, thereby reducing the ohmic resistance of the N well layer and the metal source electrode, and reducing the heating at the contact position.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a SiC VDMOSFET structure with high heat dissipation and a preparation method thereof. Background Art

[0002] The main failure mode of electronic equipment is thermal failure. According to statistics, 55% of electronic equipment failures are caused by temperatures exceeding the specified value. As the temperature increases, the failure rate of electronic equipment increases exponentially. Therefore, good thermal design is the basis for ensuring stable and reliable operation of equipment.

[0003] The existing patent discloses a power device heat dissipation structure and preparation method (CN115547953A), including a substrate; an active area island disposed above the substrate; a source-drain contact area and a gate disposed above the active area island; and a diamond film epitaxially surrounding the active area island; the source-drain contact area is isolated from the gate by the diamond film. In the technology disclosed in the patent, when the device is used in a high-load environment for a long time, there will be an obvious problem of heat accumulation, which will cause the device to fail due to excessive temperature. At the same time, the parasitic capacitance between the drain area and the gate will increase exponentially, especially in high-frequency switching operations, which will greatly increase the delay of device switching. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a SiC VDMOSFET structure with high heat dissipation and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiCVDMOSFET structure with high heat dissipation performance includes a plurality of mutually parallel MOS cells, wherein the MOS cells include a metal drain, a semiconductor epitaxial layer, a metal source, and a gate oxide layer covering the surface of the metal source, wherein an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer, and a P well layer are formed inside the semiconductor epitaxial layer by ion implantation; A source doping layer is provided on both the left and right sides of a single MOS cell, wherein the source doping layer is in ohmic contact with the metal source, and the source doping layer is one of gallium arsenide, gallium nitride or nickel-chromium alloy; The cross-sectional profile of the heavily doped P layer is in an arc shape, and the heavily doped P layer is in ohmic contact with the source doped layer; The N-well layer is in ohmic contact with the metal source and the source doping layer at the same time.

[0006] Furthermore, a single MOS cell is provided with side doping layers on both left and right sides, and the side doping layers are in ohmic contact with the metal drain electrode; The N substrate layer is in an arc shape near the side doping layer.

[0007] Furthermore, a middle doping layer is provided in the middle of a single MOS cell, and the middle doping layer is in ohmic contact with the metal drain electrode; The N substrate layer is in a trapezoidal shape near the middle doping layer.

[0008] Furthermore, a plurality of gate doping layers are disposed in the middle of a single MOS cell, and the distances between any two gate doping layers are the same.

[0009] Furthermore, the side doping layer, the middle doping layer and the gate doping layer are made of one of gallium arsenide, gallium nitride or nickel-chromium alloy.

[0010] A method for preparing a SiC VDMOSFET structure with high heat dissipation performance comprises the following steps: S1, selecting a doped semiconductor epitaxial layer, and etching grooves on the upper and lower surfaces of the semiconductor epitaxial layer by reactive ion etching; S2, filling the upper surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a source doping layer, and filling the lower surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a side doping layer, a middle doping layer and a gate doping layer; S3. Depositing metal on the surface of the semiconductor epitaxial layer to form a metal drain and a metal source, and testing the heat dissipation performance of the formed SiCVDMOSFET structure.

[0011] Furthermore, in step S3, the heat dissipation performance of the SiC VDMOSFET structure is determined according to the maximum junction temperature of the SiC VDMOSFET structure, the heat conduction resistance of the SiC VDMOSFET structure from the junction to the environment, and the change in switching loss of the SiC VDMOSFET structure when the standard temperature rises to 100°C, then: In the formula, represents the thermal performance coefficient of the tested SiC VDMOSFET structure, represents the maximum junction temperature of the SiC VDMOSFET structure, represents the thermal conduction resistance from the junction to the environment of the SiC VDMOSFET structure, It indicates the change in switching loss of SiC VDMOSFET structure when the temperature rises from standard to 100℃.

[0012] Furthermore, when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure can meet the use requirements; when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure cannot meet the use requirements.

[0013] Beneficial effects: 1. The present invention provides a source doping layer with a sinking design above the MOS cell, which allows the N-well layer to directly contact the metal source electrode, and also allows the N-well layer to indirectly contact the metal source electrode through the source doping layer, thereby reducing the ohmic resistance between the N-well layer and the metal source electrode, thereby reducing the heat generation at the contact position.

[0014] 2. The present invention uses a metal with better heat dissipation performance for the source doping layer, so that the source doping layer can improve heat dissipation by increasing the contact area with the semiconductor epitaxial layer and can also improve the heat dissipation effect through good metal heat dissipation.

[0015] 3. The present invention can quickly and conveniently determine the heat dissipation performance of the SiC VDMOSFET structure through the maximum junction temperature of the SiC VDMOSFET structure, the heat conduction resistance from the junction to the environment, and the change in switching loss when the standard temperature rises to 100°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a schematic diagram of the second embodiment of the present invention; Figure 3 It is a schematic diagram of Embodiment 3 of the present invention; Figure 4 It is a schematic diagram of Embodiment 4 of the present invention.

[0017] In the figure: 1. Metal drain; 2. Metal source; 3. Gate; 4. Gate oxide layer; 5. N substrate layer; 6. N drift layer; 7. N well layer; 8. Heavily doped P layer; 9. P well layer; 10. Source doping layer; 11. Side doping layer; 12. Middle doping layer; 13. Gate doping layer. DETAILED DESCRIPTION

[0018] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 1-4 As shown, the method for preparing a SiC VDMOSFET structure with high heat dissipation performance comprises the following steps: Step 1: Select a doped semiconductor epitaxial layer, and etch grooves on both the upper and lower surfaces of the semiconductor epitaxial layer by reactive ion etching; Step 2: Fill the upper surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a source doping layer 10, and fill the lower surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a side doping layer 11, a middle doping layer 12 and a gate doping layer 13; Step 3: depositing metal on the surface of the semiconductor epitaxial layer to form a metal drain 1 and a metal source 2, and testing the heat dissipation performance of the formed SiC VDMOSFET structure.

[0020] The heat dissipation performance of the SiCVDMOSFET structure is determined based on the maximum junction temperature of the SiC VDMOSFET structure, the thermal conduction resistance of the SiC VDMOSFET structure from the junction to the environment, and the change in switching loss when the SiC VDMOSFET structure rises from the standard temperature to 100°C. Then: In the formula, represents the thermal performance coefficient of the tested SiC VDMOSFET structure, represents the maximum junction temperature of the SiC VDMOSFET structure, represents the thermal conduction resistance from the junction to the environment of the SiC VDMOSFET structure, It indicates the change in switching loss of SiC VDMOSFET structure when the temperature rises from standard to 100℃.

[0021] when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure can meet the use requirements; when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure cannot meet the use requirements.

[0022] Among them, when it is necessary to detect the thermal performance coefficient of the sampled SiC VDMOSFET structure, it is necessary to collect the maximum junction temperature of the SiCVDMOSFET structure, the thermal conduction resistance from the junction to the environment, and the change in switching loss when the standard temperature rises to 100°C. Then, the maximum junction temperature of the SiC VDMOSFET structure is taken (℃). The thermal conduction resistance from the junction to the environment of the SiC VDMOSFET structure is (Unit: °C / W, thermal conduction resistance = (maximum junction temperature - ambient temperature) / power loss). The change in switching loss when the SiC VDMOSFET structure rises from the standard temperature to 100 °C is (Loss change = ambient temperature × (1 + empirically estimated percentage increase × (100°C - 20°C) / 10°C)). Then we have: From the above calculation, we can know that the heat dissipation performance coefficient of the sampled SiC VDMOSFET structure is , then it means that the heat dissipation performance of the tested SiC VDMOSFET structure can meet the use requirements.

[0023] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a SiC VDMOSFET structure with high heat dissipation is provided, including a plurality of mutually parallel MOS cells, the MOS cell including a metal drain 1, a semiconductor epitaxial layer, a metal source 2 and a gate oxide layer 4 covering the surface of the metal source 2, an N substrate layer 5, an N drift layer 6, an N well layer 7, a heavily doped P layer 8 and a P well layer 9 are formed inside the semiconductor epitaxial layer by ion implantation; a source doping layer 10 is provided on both sides of a single MOS cell, wherein the source doping layer 10 is in ohmic contact with the metal source 2, and the source doping layer 10 is one of gallium arsenide, gallium nitride or nickel-chromium alloy; the cross-sectional profile of the heavily doped P layer 8 is in an arc shape, and the heavily doped P layer 8 is in ohmic contact with the source doping layer 10; the N well layer 7 is in ohmic contact with both the metal source 2 and the source doping layer 10. A sinking source doping layer 10 is arranged above the MOS cell, which allows the N-well layer 7 to directly contact the metal source 2, and also allows the N-well layer 7 to indirectly contact the metal source 2 through the source doping layer 10, thereby reducing the ohmic resistance between the N-well layer 7 and the metal source 2, thus reducing the heat generation at the contact position. In addition, the source doping layer 10 uses a metal with better heat dissipation performance, so that the source doping layer 10 can improve heat dissipation by increasing the contact area with the semiconductor epitaxial layer, and can also improve the heat dissipation effect through good metal heat dissipation.

[0024] Example 2 like Figure 2 As shown, side doping layers 11 are provided on both sides of the interior of a single MOS cell, and the side doping layers 11 are in ohmic contact with the metal drain 1; the N substrate layer 5 is in an arc shape near the side doping layer 11. The material of the side doping layer 11 is one of gallium arsenide, gallium nitride or nickel-chromium alloy. The side doping layer 11 helps to reduce the contact resistance between the metal source 2 and the metal drain 1 and the semiconductor, and improve the current conduction capacity of the device. The side doping layer 11 enhances the contact area between the metal and the semiconductor, thereby reducing the resistance loss. And through the design of the side doping layer 11, the path for carriers to be injected from the metal source 2 or the metal drain 1 into the semiconductor can be optimized, thereby improving the switching performance of the device. In particular, by increasing the contact area of ​​the metal area, the side doping layer 11 helps to better dissipate heat and prevent the performance of the device from being degraded due to overheating.

[0025] Example 3 like Figure 3 As shown, a middle doping layer 12 is provided in the middle of a single MOS cell, and the middle doping layer 12 is in ohmic contact with the metal drain 1; the N substrate layer 5 is in a trapezoidal shape near the middle doping layer 12. The material of the middle doping layer 12 is one of gallium arsenide, gallium nitride or nickel-chromium alloy. The middle doping layer 12 is provided in the middle of the metal drain 1 to help improve the current distribution. By making the current flow in the metal drain 1 area more uniform and reducing the concentration of current density, the heat loss in the metal drain 1 area is reduced, thereby improving the reliability of the device. The middle doping layer 12 increases the surface area of ​​the metal, which helps to improve the heat dissipation effect, reduce the temperature rise, and reduce the negative impact of heat accumulation on the device performance, thereby improving the long-term stability of the MOSFET.

[0026] Example 4 like Figure 4 As shown, a plurality of gate doping layers 13 are provided in the middle of the interior of a single MOS cell, and the distance between two gate doping layers 13 is the same. The material of the gate doping layer 13 is one of gallium arsenide, gallium nitride or nickel-chromium alloy. By arranging the gate doping layers 13 distributed at intervals in the middle of the drain, the current can be effectively distributed more evenly in the metal drain 1 area, avoiding local hot spots with excessive current density, and reducing the performance degradation caused by local overheating in the metal drain 1 area. The gate doping layers 13 distributed at intervals improve the heat dissipation path by increasing the contact area, which helps to dissipate the heat in the metal drain 1 area, reduce the temperature rise of the device, improve the heat dissipation performance, and reduce the device failure caused by excessive temperature. In addition, the design of the gate doping layer 13 helps to reduce the parasitic capacitance between the metal drain 1 area and the gate 3, especially in high-frequency switching operations, which helps to increase the switching speed and reduce the switching delay.

[0027] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SiC VDMOSFET structure with high heat dissipation performance, comprising a plurality of MOS cells arranged in parallel, wherein the MOS cells comprise a metal drain (1), a semiconductor epitaxial layer, a metal source (2), and a gate oxide layer (4) covering the surface of the metal source (2), characterized in that: An N substrate layer (5), an N drift layer (6), an N well layer (7), a heavily doped P layer (8) and a P well layer (9) are formed inside the semiconductor epitaxial layer by ion implantation; A source doping layer (10) is provided on both the left and right sides of a single MOS cell, wherein the source doping layer (10) is in ohmic contact with the metal source (2), and the source doping layer (10) is one of gallium arsenide, gallium nitride or nickel-chromium alloy; The cross-sectional profile of the heavily doped P layer (8) is in an arc shape, and the heavily doped P layer (8) is in ohmic contact with the source doped layer (10); The N-well layer (7) is in ohmic contact with both the metal source electrode (2) and the source doping layer (10).

2. The SiC VDMOSFET structure with high heat dissipation performance according to claim 1, characterized in that: A side doping layer (11) is provided on both the left and right sides of the interior of a single MOS cell, and the side doping layer (11) is in ohmic contact with the metal drain (1); The N substrate layer (5) is in an arc shape at a position close to the side doping layer (11).

3. The SiC VDMOSFET structure with high heat dissipation performance according to claim 1, characterized in that: A medium doping layer (12) is provided in the middle of a single MOS cell, and the medium doping layer (12) is in ohmic contact with the metal drain (1); The N substrate layer (5) is in a trapezoidal shape at a position close to the medium doping layer (12).

4. The SiC VDMOSFET structure with high heat dissipation performance according to claim 1, characterized in that: A plurality of gate doping layers (13) are arranged in the middle of a single MOS cell, and the distance between any two gate doping layers (13) is the same.

5. The SiC VDMOSFET structure with high heat dissipation according to any one of claims 1 to 4, characterized in that: The side doping layer (11), the middle doping layer (12) and the gate doping layer (13) are made of one of gallium arsenide, gallium nitride or nickel-chromium alloy.

6. A method for preparing a SiC VDMOSFET structure with high heat dissipation, characterized in that: The method for preparing the SiCVDMOSFET structure with high heat dissipation is applied to the SiC VDMOSFET structure according to any one of claims 1 to 5, and the method for preparing the SiC VDMOSFET structure with high heat dissipation comprises the following steps: S1, selecting a doped semiconductor epitaxial layer, and etching grooves on the upper and lower surfaces of the semiconductor epitaxial layer by reactive ion etching; S2, filling the upper surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a source doping layer (10), and filling the lower surface groove of the semiconductor epitaxial layer with one of gallium arsenide, gallium nitride or nickel-chromium alloy to form a side doping layer (11), a middle doping layer (12) and a gate doping layer (13); S3, depositing metal on the surface of the semiconductor epitaxial layer to form a metal drain (1) and a metal source (2), and testing the heat dissipation performance of the formed SiCVDMOSFET structure.

7. The SiC VDMOSFET structure with high heat dissipation performance and the method for preparing the same according to claim 6, characterized in that: In step S3, the heat dissipation performance of the SiCVDMOSFET structure is determined according to the maximum junction temperature of the SiC VDMOSFET structure, the heat conduction resistance of the SiC VDMOSFET structure from the junction to the environment, and the change in switching loss of the SiC VDMOSFET structure when the temperature rises from the standard temperature to 100°C. Then: In the formula, represents the thermal performance coefficient of the tested SiC VDMOSFET structure, represents the maximum junction temperature of the SiC VDMOSFET structure, represents the thermal conduction resistance from the junction to the environment of the SiC VDMOSFET structure, It indicates the change in switching loss of SiC VDMOSFET structure when the temperature rises from standard to 100℃.

8. The SiC VDMOSFET structure with high heat dissipation performance and the method for preparing the same according to claim 7, characterized in that: when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure can meet the use requirements; when When , it means that the heat dissipation performance of the tested SiC VDMOSFET structure cannot meet the use requirements.

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