High-order QAM (Quadrature Amplitude Modulation) signal demodulation carrier synchronization design method based on secondary loop filtering

Abstract

The invention discloses a high-order QAM (Quadrature Amplitude Modulation) signal demodulation carrier synchronization design method based on secondary loop filtering, which relates to the field of signal processing, gives consideration to steady-state phase difference and capture bandwidth of carrier synchronization, covers various application scenes and provides good demodulation performance. According to the technical scheme, the method comprises the steps that a first loop is designed and mainly comprises a carrier compensator, a digital frequency discriminator, a numerical control oscillator, a first-stage digital loop filter and a frequency locking detector; the two-stage digital loop mainly comprises a carrier compensator, a digital phase discriminator, a numerical control oscillator, a two-stage digital loop filter and a phase locking detector. After the two stages of loops are connected in series, the first-stage loop carries out synchronous compensation on large frequency offset of signals, and the second-stage loop carries out synchronous compensation on small residual frequency offset and phase offset of the signals. The design is monitored through a locking detector, and carrier synchronization of high-order QAM signal demodulation is achieved.

Description

Technical Field

[0001] The invention relates to the field of signal processing, and in particular to a high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] Since the mid-20th century, communication technology has been developing day by day. Modern communication technology has overcome the limitations of time and space, making it possible for people to obtain and communicate information anytime and anywhere. Among them, digital communication has been widely used in today's communication systems due to its strong anti-interference ability, easy modulation, high confidentiality and easy combination with computers. The typical signal processing process of a digital communication receiving system includes: multiple access, frequency despreading, signal sampling, digital demodulation, channel decoding, decryption, and source decoding. The digital demodulator is the most basic and core part of the digital receiving system, which is equivalent to the "brain" of the entire receiving system. It processes the transmitted waveform that is degraded by the channel and restores it to a digital sequence. High-order quadrature amplitude modulation (QAM) is widely used in ultra-short wave communication and satellite communication with its high bandwidth utilization and good power utilization. In actual application scenarios, there are often certain degrees of time and frequency errors between the sending system and the receiving system. With the changes in the electromagnetic environment, the signal may also have changes in carrier frequency such as Doppler frequency shift during channel transmission. Therefore, when demodulating QAM signals, carrier synchronization is the key to the correct transmission of information. Its performance directly determines the quality of communication. The synchronization problem must be solved in almost all communication systems. Stable and accurate synchronization is crucial for high-order QAM signal demodulation.

[0004] Conventional carrier synchronization processing modules include: carrier compensator, digital frequency discriminator, digital loop filter, digital controlled oscillator and lock detector, etc. The carrier synchronization processing module has two basic working states: capture state and synchronization state. There are two main performance indicators for evaluating the performance of the capture process: one is the capture band of the digital loop, that is, the maximum inherent frequency difference that the carrier synchronization module can enter the synchronization state through the capture process. If the frequency difference of the input signal is greater than the inherent frequency difference of the synchronization module, the synchronization module cannot enter the synchronization state; the other is the capture time, which is the time interval between the carrier synchronization from the start time to the time of entering the synchronization state. The performance of the capture process mainly depends on the parameter setting of the digital loop filter, that is, the determination of the loop bandwidth. Generally speaking, the smaller the loop bandwidth, the lower the signal-to-noise ratio required when the carrier synchronization is locked, that is, the synchronization module is easier to lock under harsh conditions, and the smaller the steady-state phase difference after locking, the longer the capture time; the larger the loop bandwidth, the wider the capture bandwidth of the synchronization module, the faster the capture, but the corresponding noise resistance and stability will be worse. In practical applications, faced with increasingly complex and changeable electromagnetic environments, conventional carrier synchronization processing methods have been unable to meet the changing needs of users.

[0005] How to balance the steady-state phase difference and capture bandwidth is the key to ensuring the signal demodulation carrier synchronization performance. In conventional methods, the digital loop filter parameters determine the performance of demodulation carrier synchronization, but it is difficult to determine universal parameters that are suitable for various situations. The two-stage digital loop filter design does not try to find the balance point parameters that take into account the steady-state phase difference and capture bandwidth, but considers the two key performance indicators of steady-state phase difference and capture bandwidth separately by designing different loop parameters: the first-stage digital loop filter only considers the capture bandwidth, and initially locks the frequency within a certain range. At this time, the demodulation constellation diagram is allowed to still have residual small frequency deviation and phase deviation; the second-stage digital loop filter considers the steady-state phase difference, and uses a smaller loop bandwidth to track the residual frequency deviation and phase deviation, while obtaining better noise resistance. Summary of the invention

[0006] The purpose of the present invention is to provide a high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering to address the problems existing in the prior art, taking into account the steady-state phase difference and capture bandwidth of carrier synchronization, covering a variety of application scenarios, and providing good demodulation performance.

[0007] The technical solution of the present invention is as follows:

[0008] A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering, comprising:

[0009] Step S1: performing preliminary frequency offset capture of a high-order QAM complex signal with a large loop bandwidth, generating a carrier compensation signal, outputting a compensated high-order QAM complex signal, and performing lock detection on loop one;

[0010] Step S2: After the lock detection flag in step S1 is valid, the compensated high-order QAM complex signal is subjected to secondary synchronous tracking with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop 2;

[0011] Step S3: When the locking detection flags of loop 1 and loop 2 are both valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed.

[0012] Furthermore, the loop 1 includes: a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector;

[0013] The second loop includes: a carrier compensator, a digital phase detector, a digitally controlled oscillator, a secondary digital loop filter, and a phase lock detector.

[0014] Furthermore, the step S1 comprises:

[0015] Step S11: Perform digital frequency discrimination processing on the high-order QAM complex signal s1(n) through a digital frequency discriminator to obtain a frequency error ψ a(n) ;

[0016] Step S12: frequency error ψ a(n) It is sent to the first-stage digital loop filter and outputs the frequency error control word ω a(n) ; At the same time, the frequency lock detector starts to perform lock detection on the first-level digital loop filter;

[0017] Step S13: The frequency error control word ω a(n) Sent to the digital controlled oscillator to generate a first-level carrier compensation signal The high-order QAM complex signal s1(n) is then compensated by the carrier compensator, and the compensated high-order QAM complex signal s2(n) is output.

[0018] Furthermore, the step S2 comprises:

[0019] Step S21: Perform digital frequency discrimination processing on the compensated high-order QAM complex signal s2(n) through a digital frequency discriminator to obtain a phase error ψ b(n) ;

[0020] Step S22: The phase error ψ b(n) It is sent to the secondary digital loop filter and outputs the phase error control word ω b(n) ; At the same time, the phase lock detector starts to perform lock detection on the secondary digital loop filter;

[0021] Step S23: The phase error control word ωb(n) Sent to the digital controlled oscillator to generate a secondary carrier compensation signal The high-order QAM complex signal s2(n) is compensated by the carrier compensator, and a high-order QAM complex signal s3(n) is output after secondary compensation.

[0022] Furthermore, the frequency error control word ω a(n) It is expressed as:

[0023] ω a(n) =ω a(n-1) +C a1 (ψ a(n) -ψ a(n-1) )+C a2 ψ a(n)

[0024] Among them, C a1 , C a2 are the loop parameters of the first-stage digital loop filter, ω 1n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period.

[0025] Furthermore, the phase error control word ω b(n) It is expressed as:

[0026] ω b(n) =ω b(n-1) +C b1 (ψ b(n) -ψ b(n-1) )+C b2 ψ b(n)

[0027] Among them, C b1 , C b2 are the loop parameters of the second-stage digital loop filter, ω 2n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period.

[0028] Furthermore, the digital frequency discriminator adopts a polarity decision phase detection algorithm.

[0029] Furthermore, the input signal of the loop is an I and Q signal after down-conversion, resampling, matched filtering and bit synchronization.

[0030] Furthermore, the output signal of the loop is a carrier-locked output signal, that is, a constellation diagram of the modulated signal.

[0031] Furthermore, the modulation modes applicable to the loop are 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention optimizes the carrier synchronization in the demodulation of high-order QAM signals by designing a two-stage digital loop filter. The first-stage digital loop filter quickly captures the larger carrier frequency deviation of the signal and initially locks the frequency within a certain range. At this time, the demodulation constellation diagram is allowed to still have residual small frequency deviation and phase deviation; the second-stage digital loop filter considers the steady-state phase difference and uses a smaller loop bandwidth to track the residual frequency deviation and phase deviation, while obtaining better noise resistance, effectively taking into account the steady-state phase difference and capture bandwidth of carrier synchronization, and providing good demodulation performance.

[0034] 2. The present invention has the characteristics of large carrier synchronization capture range, high synchronization accuracy, strong anti-noise ability, and good adaptability and versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is the principle diagram of the secondary loop filter carrier synchronization processing;

[0036] Figure 2 This is the schematic diagram of the first-stage loop filter feedback processing;

[0037] Figure 3 The schematic diagram of the digital frequency discriminator for the first-stage loop filter feedback processing;

[0038] Figure 4 This is the schematic diagram of the secondary loop filter feedback processing. DETAILED DESCRIPTION

[0039] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0040] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0041] Embodiment 1

[0042] See also Figure 1 , a high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering, comprising:

[0043] Step S1: performing preliminary frequency offset capture of a high-order QAM complex signal with a large loop bandwidth, generating a carrier compensation signal, outputting a compensated high-order QAM complex signal, and performing lock detection on loop one;

[0044] Step S2: After the lock detection flag in step S1 is valid, the compensated high-order QAM complex signal is subjected to secondary synchronous tracking with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop 2;

[0045] Step S3: When the locking detection flags of loop 1 and loop 2 are both valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed.

[0046] In this embodiment, it should be noted that there are many design methods for the frequency lock detector, and its implementation structure can be selected as appropriate in actual development. In order to better adapt to engineering practice, the intermediate signals such as the error signal and the control word signal can also be appropriately smoothed. Figure 2 As shown, loop one includes: a carrier compensator, a digital frequency discriminator, a first-stage digital loop filter, a digitally controlled oscillator, and a frequency lock detector.

[0047] According to the signal characteristics, the input baseband high-order QAM complex signal expression is:

[0048]

[0049] Specifically, step S1 includes:

[0050] Step S11: Perform digital frequency discrimination processing on the high-order QAM complex signal s1(n) through a digital frequency discriminator to obtain a frequency error ψ a(n) ;

[0051] Step S12: frequency error ψ a(n) It is sent to the first-stage digital loop filter and outputs the frequency error control word ω a(n) At the same time, the frequency lock detector starts to lock the first-level digital loop filter, that is, when the frequency error ψ a(n)When entering the first-stage digital loop filter, the frequency lock detector starts to perform lock detection on the first-stage digital loop filter; it should be noted that the first-stage digital loop filter is an infinite impulse response filter, which can accumulate all previous frequency error signals to achieve the function of outputting a fixed control amount in a steady state; the frequency error control word ω output by the first-stage digital loop filter a(n) It is expressed as:

[0052] ω a(n) =ω a(n-1) +C a1 (ψ a(n) -ψ a(n-1) )+C a2 ψ a(n)

[0053] Among them, C a1 , C a2 are the loop parameters of the first-stage digital loop filter, ω 1n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period;

[0054] Step S13: The frequency error control word ω a(n) Sent to the digital controlled oscillator to generate a first-level carrier compensation signal And enter the carrier compensator to compensate the high-order QAM complex signal s1(n), and output the compensated high-order QAM complex signal s2(n), which is expressed as

[0055]

[0056] Figure 3 This is a schematic diagram of a digital discriminator in the feedback processing of a first-stage loop filter. It should be noted that there are a variety of design methods for digital discriminators, and their implementation structures can be selected as appropriate in actual development. In order to better adapt to engineering practice, the present invention adopts a polarity decision phase detection algorithm. Considering that the demodulated signal targeted by the present invention is a high-order QAM signal with multiple levels, the signal-to-noise ratio of the inner loop modulation symbol is low and the signal-to-noise ratio of the outer loop is high, so the power detection method is combined in the detection algorithm-only the symbols with high signal-to-noise ratio of the outer loop are used to calculate the phase error. When using the outer loop modulation symbol, polarity decision can be further used to replace the level-by-level decision, so as to further reduce the sensitivity of the phase detection output to the precise decision.

[0057] Assume q(n) is the input signal of the digital discriminator. The function of the power detector is to determine whether the power of the signal q(n) satisfies the condition |q(n)| 2 >τ 2 , τ is the set power threshold value, which is different in different modulation modes and determines the range of symbol points involved in frequency identification. That is, the power is greater than τ2 The input symbol is first polarity determined, and then the phase error is calculated. Assume that in the nth symbol interval, that is, t∈((n-1)T s ,nT s ], the input signal of the digital discriminator is:

[0058]

[0059] Among them, r n is the amplitude of the input signal q(n), θ n is the instantaneous phase of q(n). The output signal of the polarity decision device is:

[0060]

[0061] The ratio of the input signal to the polarity determiner output signal is:

[0062]

[0063] Considering that sin(x)≈x when x is very small, taking the imaginary part of the ratio of the input signal to the output signal of the polarity decision device yields:

[0064]

[0065] That is, by taking the imaginary part of the ratio signal, the approximate phase difference information Δθ can be obtained.

[0066] In summary, the phase error after polarity determination can be calculated according to the following formula:

[0067]

[0068] The input signal q(n) is expressed as a complex number:

[0069] q(n)=I(n)+j·Q(n)

[0070] The signal for polarity determination can be described as:

[0071] d(n)=A·{sgn[I(n)]+j·sgn[Q(n)]}

[0072] Substituting this into the phase error formula yields:

[0073]

[0074] As can be seen from the above formula, the extraction and calculation of the phase error does not require an actual multiplication unit, and the efficiency is very high. Power detection provides higher stability and reliability for phase detection of multi-level modulated signals.

[0075] See also Figure 4 In this embodiment, there are multiple design methods for the digital phase detector and the phase lock detector, and their implementation structures can be selected as appropriate in actual development. Figure 4 As shown, loop 2 includes: carrier compensator, digital phase detector, digital controlled oscillator, secondary digital loop filter, phase lock detector. Figure 2 After the frequency lock detector outputs the lock flag shown, Figure 2 The output s2(n) of is used as input and enters Figure 4 Loop two feedback processing is shown.

[0076] In this embodiment, specifically, step S2 includes:

[0077] Step S21: Perform digital frequency discrimination processing on the compensated high-order QAM complex signal s2(n) through a digital frequency discriminator to obtain a phase error ψ b(n) ;

[0078] Step S22: The phase error ψ b(n) It is sent to the secondary digital loop filter and outputs the phase error control word ω b(n) At the same time, the phase lock detector starts to lock the secondary digital loop filter, that is, when the phase error ψ b(n) When entering the secondary digital loop filter, the phase lock detector starts to perform lock detection on the secondary digital loop filter; the phase error control word ω b(n) It is expressed as:

[0079] ω b(n) =ω b(n-1) +C b1 (ψ b(n) -ψ b(n-1) )+C b2 ψ b(n)

[0080] Among them, C b1 , C b2 are the loop parameters of the second-stage digital loop filter, ω 2n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period;

[0081] Step S23: The phase error control word ω b(n) Sent to the digital controlled oscillator to generate a secondary carrier compensation signal And enter the carrier compensator to compensate the compensated high-order QAM complex signal s2(n), and output the secondary compensated high-order QAM complex signal s3(n), the expression is:

[0082]

[0083] When the secondary digital loop filter lock flag is valid, s3(n) is the high-order QAM signal after carrier synchronization is completed.

[0084] At this time, Δf3≈0 in the above formula, k=0,1,2,3.

[0085] In this embodiment, specifically, the input signal of the loop is an I and Q signal after down-conversion, resampling, matched filtering and bit synchronization.

[0086] In this embodiment, specifically, the output signal of the loop is a carrier-locked output signal, that is, a constellation diagram of the modulation signal.

[0087] In this embodiment, specifically, the modulation modes applicable to the loop are 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

[0088] In this embodiment, specifically, Figure 2 and Figure 4 The main structural differences are the digital frequency detector, phase detector and lock detector. However, the performance of the two loops mainly depends on the loop parameters of the digital loop filter.

[0089] Figure 1 This is an example of the schematic diagram of the carrier synchronization processing in the entire secondary loop filter, which describes the high-order QAM carrier recovery process of the second-order loop filter. The primary loop filter feedback performs preliminary frequency deviation capture with a large loop bandwidth, and the required transient time is longer, so it is also called a slow loop; the secondary loop filter feedback performs secondary synchronization tracking with a smaller loop bandwidth, and the transient time is shorter, so it is also called a fast loop. During the operation of the slow loop, the operation of the fast loop must be stopped, so a lock detector is used in the slow loop for control. After the slow loop is locked, it outputs a fixed phase deviation to compensate for the existing large fixed frequency deviation, while the remaining small frequency deviation and phase deviation are tracked by the fast loop. The phase error signals generated by the slow loop and the fast loop are accumulated and processed by the phase accumulator to generate a control word, which controls the digital controlled oscillator to generate the corresponding carrier signal.

[0090] The carrier signal generated by the slow loop and the input signal s1(n) enter the carrier compensator, and the output signal s2(n) after the first level compensation is used as the input signal of the fast loop. After being captured by the fast loop, the carrier signal generated and s2(n) enter the carrier compensator, and the output signal s3(n) is the high-order QAM signal after the carrier synchronization is completed.

[0091] The above-mentioned embodiments only express the specific implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the protection scope of the present application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the technical solution concept of the present application, and these all belong to the protection scope of the present application.

[0092] This background section is provided to generally present the context of the invention, and the work of the presently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither explicitly nor implicitly admitted to be prior art to the present invention.

Claims

1. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering, characterized in that: include: Step S1: performing preliminary frequency offset capture of a high-order QAM complex signal with a large loop bandwidth, generating a carrier compensation signal, outputting a compensated high-order QAM complex signal, and performing lock detection on loop one; Step S2: After the lock detection flag in step S1 is valid, the compensated high-order QAM complex signal is subjected to secondary synchronous tracking with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop 2; Step S3: When the locking detection flags of loop 1 and loop 2 are both valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed.

2. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 1, characterized in that: The loop 1 includes: a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector; The second loop includes: a carrier compensator, a digital phase detector, a digitally controlled oscillator, a secondary digital loop filter, and a phase lock detector.

3. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 2, characterized in that: The step S1 comprises: Step S11: Perform digital frequency discrimination processing on the high-order QAM complex signal s1(n) through a digital frequency discriminator to obtain a frequency error ψ a(n) ; Step S12: frequency error ψ a(n) It is sent to the first-stage digital loop filter and outputs the frequency error control word ω a(n) ; At the same time, the frequency lock detector starts to perform lock detection on the first-level digital loop filter; Step S13: The frequency error control word ω a(n) Sent to the digital controlled oscillator to generate a first-level carrier compensation signal The high-order QAM complex signal s1(n) is then compensated by the carrier compensator, and the compensated high-order QAM complex signal s2(n) is output.

4. The high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 3 is characterized in that: The step S2 comprises: Step S21: Perform digital frequency discrimination processing on the compensated high-order QAM complex signal s2(n) through a digital frequency discriminator to obtain a phase error ψ b(n) ; Step S22: The phase error ψ b(n) It is sent to the secondary digital loop filter and outputs the phase error control word ω b(n) ; At the same time, the phase lock detector starts to perform lock detection on the secondary digital loop filter; Step S23: The phase error control word ω b(n) Sent to the digital controlled oscillator to generate a secondary carrier compensation signal The high-order QAM complex signal s2(n) is compensated by the carrier compensator, and a high-order QAM complex signal s3(n) is output after secondary compensation.

5. The high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 4 is characterized in that: The frequency error control word ω a(n) It is expressed as: oh a(n) =ω a(n-1) +C a1 (ψ a(n) -ψ a(n-1) )+C a2 ψ a(n) Among them, C a1 , C a2 are the loop parameters of the first-stage digital loop filter, ω 1n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period.

6. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 5, characterized in that: The phase error control word ω b(n) It is expressed as: oh b(n) =ω b(n-1) +C b1 (ψ b(n) -ψ b(n-1) )+C b2 ψ b(n) Among them, C b1 , C b2 are the loop parameters of the second-stage digital loop filter, ω 2n is the loop bandwidth, ξ is the damping coefficient, and T is the sampling period.

7. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to claim 2, characterized in that: The digital frequency discriminator adopts a polarity decision phase detection algorithm.

8. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to any one of claims 1 to 7, characterized in that: The input signal of the loop is the I and Q signals after down-conversion, resampling, matched filtering and bit synchronization.

9. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to any one of claims 1 to 7, characterized in that: The output signal of the loop is a carrier-locked output signal, that is, a constellation diagram of the modulated signal.

10. A high-order QAM signal demodulation carrier synchronization design method based on secondary loop filtering according to any one of claims 1 to 7, characterized in that: The modulation modes applicable to the loop are 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

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