Phase-locked loop quantization noise calibration method and system, electronic equipment and storage medium

Abstract

The invention discloses a phase-locked loop quantization noise calibration method and system, electronic equipment and a storage medium. The method comprises the following steps: a phase frequency detector performs correlation processing on a feedback signal output by a modulator and a reference signal output by a phase discriminator to generate a gain coefficient; multiplying the gain coefficient by a feedback signal output by the modulator to output a first gain signal; subtracting the first gain signal from a reference signal output by the phase discriminator to output a second gain signal; the second gain signal is filtered by the digital loop filter to obtain a filtered signal and the filtered signal is output to the digital time converter; and the digital time converter processes the filtering signal to obtain a pulse signal suitable for being processed by the phase discriminator and outputs the pulse signal to the phase discriminator. The LMS algorithm is adopted, and on the basis of the complementary digital time converter calibration technology, quantization noise is eliminated through a low-energy-consumption circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit chips, and in particular to a phase-locked loop quantization noise calibration method, system, electronic equipment and storage medium. Background Art

[0002] Existing system-on-chip (SoC) contains many functions and requires many clock signals of different frequencies and performances. For example, multi-core processors, memory, I / O interfaces, power management, wireless transceivers and wired transceivers require their own clock chips to achieve optimal system performance. However, traditional analog phase-locked loops are large in area and have only one output signal, so it is difficult to meet the clock requirements of existing high-performance SoCs. Although digital fractional phase-locked loops can overcome problems such as area and power consumption, the compromise between the time-to-digital converter (TDC), the quantization noise of the fractional divider, and the phase noise of the digital controlled oscillator (DCO) is inevitable. At the same time, multiple clock signals require multiple phase-locked loops, resulting in large area and power consumption. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to provide a phase-locked loop quantization noise calibration method, system, electronic device and storage medium that can eliminate quantization noise with a lower energy consumption circuit.

[0004] Technical solution: In order to achieve the above-mentioned invention object, a phase-locked loop quantization noise calibration method of the present invention comprises the following steps:

[0005] The phase frequency detector correlates the feedback signal output by the modulator with the reference signal output by the phase detector to generate a gain coefficient;

[0006] The gain coefficient is multiplied by a feedback signal output by the modulator to output a first gain signal;

[0007] Subtracting the first gain signal from a reference signal output by the phase detector to output a second gain signal;

[0008] The second gain signal is filtered by a digital loop filter to obtain a filtered signal which is output to a digital-to-time converter;

[0009] The digital-to-time converter processes the filtered signal to obtain a pulse signal suitable for processing by the phase detector and outputs the pulse signal to the phase detector.

[0010] Furthermore, the method further comprises the following steps:

[0011] The multi-mode frequency divider obtains a time quantization error according to an input signal and a feedback signal output by the modulator;

[0012] The time quantization error is compensated by a first digital frequency synthesizer to obtain a first compensation signal;

[0013] The second digital frequency synthesizer receives the first compensation signal and the input signal for modulation to obtain a modulated signal;

[0014] The first digital-to-time converter performs an advance compensation signal on the received first compensation signal to output a second compensation signal to the second digital-to-time converter;

[0015] The second digital-to-time converter receives the second compensation signal to generate a delayed compensation signal, and obtains a third compensation signal which is output to the phase detector.

[0016] Furthermore, the related processing includes acquisition of input signals, phase comparison, generation of error signals and adjustment of control voltages.

[0017] Furthermore, the calculation formula of the gain coefficient is: q ×K G ×T DTCM +(1-e q )×K G ×T DTCC =T IN , when T DTCC =T DTCM , K G ×T DTCM =T IN , where K G is the gain coefficient, e q is the feedback signal of the modulator output, T IN is the time quantization error of the input signal, T DTCM is the time error of the second compensation signal, T DTCC is the third compensation signal time error.

[0018] A phase-locked loop quantization noise calibration system is applied to a phase-locked loop quantization noise calibration method, comprising a digital time converter, a phase detector, a modulator, a phase frequency detector and a digital loop filter.

[0019] The phase frequency detector is used to perform correlation processing on the feedback signal output by the modulator to generate a gain coefficient, the gain coefficient is multiplied by the feedback signal generated by the modulator to obtain a first gain signal, and the first gain signal is transmitted to the phase detector;

[0020] The phase detector is used to detect the phase difference between the input signal and the output signal of the phase-locked loop, and convert the phase difference into a corresponding error voltage signal, subtract the error voltage from the first gain signal to obtain a second gain signal, and transmit the second gain signal to the digital loop filter;

[0021] The digital loop filter is used to filter the second gain signal to obtain a filtered signal, and transmit the filtered signal to the digital-to-time converter;

[0022] The digital-to-time converter is used to convert the filtered signal into a pulse signal suitable for processing by the phase detector, and transmit the pulse signal to the phase detector.

[0023] Furthermore, the digital-to-time converter includes a first digital-to-time converter and a second digital-to-time converter, the first digital-to-time converter converts the filtered signal into a first pulse signal suitable for processing by the phase detector, and transmits the first pulse signal to the second digital-to-time converter, the second digital-to-time converter converts the first pulse signal into a second pulse signal, and transmits the second pulse signal to the phase detector.

[0024] Furthermore, the first digital-to-time converter and the second digital-to-time converter are complementary digital-to-time converters.

[0025] Furthermore, it also includes a multi-mode frequency divider, a first digital frequency synthesizer and a second digital frequency synthesizer,

[0026] The multi-mode frequency divider is used to obtain a time quantization error according to an input signal and a feedback signal output by the modulator, and output the time quantization error to the first digital frequency synthesizer;

[0027] The first digital frequency synthesizer is used to compensate the received time quantization error to obtain a first compensation signal, and output the first compensation signal to the digital-to-time converter and the second digital frequency synthesizer respectively;

[0028] The second digital frequency synthesizer is used to modulate the received first compensation signal and input signal to obtain a modulated signal and output it to the phase detector.

[0029] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the program, a phase-locked loop quantization noise calibration method is implemented.

[0030] A computer-readable storage medium stores a computer program, which implements a phase-locked loop quantization noise calibration method when executed by a processor.

[0031] Beneficial effect: Based on the complementary DTC calibration technology, the present invention proposes a quantization noise calibration technology, which reduces the compensation circuit of DTC when the digital control word is 0, and avoids the complex circuit design of FOD performance improvement technologies such as frequency spurious extraction and phase-locked loop filtering.

[0032] The present invention adopts the LMS algorithm, which is a full background calibration. Compared with the original foreground calibration + background calibration, it is insensitive to changes in process voltage temperature (PVT). The method using the LMS algorithm is simple and easy to implement, requires very small area and power consumption, and has obvious advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of a phase-locked loop quantization noise calibration method;

[0034] Figure 2 It is a block diagram of a frequency-division phase-locked loop quantization noise calibration system;

[0035] Figure 3 It is a schematic diagram of the physical structure of an electronic device. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present invention.

[0037] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, modules and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, modules, components and / or groups thereof. It should be understood that when we refer to a module as being "connected" or "coupled" to another module, it may be directly connected or coupled to the other modules, or there may be intermediate modules. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any modules and all combinations of one or more associated listed items.

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation method of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] The technical solution of the present application and how to solve the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0040] like Figure 1 FIG. 1 is a flow chart of a phase-locked loop quantization noise calibration method provided by an embodiment of the present invention, wherein the method comprises:

[0041] S1: The phase frequency detector performs correlation processing on the feedback signal output by the modulator and the reference signal output by the phase detector to generate a gain coefficient; wherein the correlation processing includes input signal acquisition, phase comparison, error signal generation and control voltage adjustment.

[0042] The calculation formula of the gain coefficient is e q ×K G ×T DTCM +(1-e q )×K G ×T DTCC =T IN , when T DTCC =T DTCM , K G ×T DTCM =T IN , where K G is the gain coefficient, e q is the feedback signal of the modulator output, T IN is the time quantization error of the input signal, T DTCM is the time error of the second compensation signal, T DTCC is the third compensation signal time error. Due to the influence of power supply voltage, temperature and process parameters, T DTCC =T DTCM The present embodiment is characterized in that the deviation is dynamically compensated by the LMS algorithm. The LMS algorithm is a background calibration, and there is no circuit pause for calibration, so it is different from the traditional foreground calibration method that requires a pause. The LMS algorithm can use a simple circuit to offset the influence of quantization noise, and the LMS algorithm is a very stable and reliable algorithm.

[0043] S2: multiplying the gain coefficient by the feedback signal output by the modulator to output a first gain signal;

[0044] S3: Subtracting the first gain signal from the reference signal output by the phase detector to output a second gain signal;

[0045] S4: the second gain signal is filtered by a digital loop filter to obtain a filtered signal which is output to a digital-to-time converter;

[0046] S5: The digital-to-time converter processes the filtered signal to obtain a pulse signal suitable for processing by the phase detector and outputs the pulse signal to the phase detector.

[0047] As an optional embodiment of the present invention, the method further comprises the following steps:

[0048] The multi-mode frequency divider obtains a time quantization error according to an input signal and a feedback signal output by the modulator;

[0049] The time quantization error is compensated by a first digital frequency synthesizer to obtain a first compensation signal;

[0050] The second digital frequency synthesizer receives the first compensation signal and the input signal for modulation to obtain a modulated signal;

[0051] The first digital-to-time converter performs an advance compensation signal on the received first compensation signal to output a second compensation signal to the second digital-to-time converter;

[0052] The second digital-to-time converter receives the second compensation signal to generate a delayed compensation signal, and obtains a third compensation signal which is output to the phase detector.

[0053] Because the multi-mode frequency divider is controlled by the modulator, there is a quantization error in the output frequency. By compensating the time quantization error, the error introduced by time quantization in the signal processing process can be reduced, thereby improving the accuracy of signal processing. Compensating for the time quantization error can make the system work more stably and reliably. In applications such as communication, radar, and navigation, the stability of the system is crucial, so this compensation mechanism can improve the performance of the entire system. By compensating for the time quantization error, the interference introduced by quantization noise in the signal processing process can be reduced, thereby expanding the dynamic range of the system. This is very important for applications that process complex signals or signals with high dynamic range. Using digital components such as digital frequency synthesizers and digital time converters for compensation can reduce the requirements for hardware, especially for systems with high precision and high stability. Digital components have higher flexibility and reusability than analog components, so they can reduce the complexity and cost of the system. Through digital components such as digital frequency synthesizers and digital time converters, the system can be flexibly configured and expanded according to specific application requirements. This makes the system more adaptable to different application scenarios and improves the reusability and maintainability of the system.

[0054] like Figure 2FIG. 1 is a structural diagram of a frequency-division phase-locked loop quantization noise calibration system provided by an embodiment of the present invention, which is applied to a phase-locked loop quantization noise calibration method. The system includes: DTC, BBPD1, DSM2, PFD3 and DLF4.

[0055] PFD3, used for performing correlation processing on the feedback signal output by DSM2 to generate a gain coefficient, multiplying the gain coefficient by the feedback signal generated by DSM2 to obtain a first gain signal, and transmitting the first gain signal to BBPD1;

[0056] BBPD1, used for detecting the phase difference between the input signal and the output signal of the phase-locked loop, converting the phase difference into a corresponding error voltage signal, subtracting the error voltage from the first gain signal to obtain a second gain signal, and transmitting the second gain signal to DLF4;

[0057] DLF4 is used to filter the second gain signal to obtain a filtered signal and transmit the filtered signal to DTC; DLF4 is used to filter the error signal to smooth the error control signal and prevent interference from high-frequency noise. In this process, DLF4 will calculate and process the error signal to obtain a suitable gain coefficient K G , in order to achieve compensation for time quantization error.

[0058] DTC is used to convert the filtered signal into a pulse signal suitable for processing by BBPD1 and transmit the pulse signal to BBPD1. DTC includes DTC M 5 and DTC C 6. DTC M 5 Convert the filtered signal into the first pulse signal suitable for BBPD1 processing, and transmit the first pulse signal to DTC C 6. DTC C 6 Convert the first pulse signal into a second pulse signal and transmit the second pulse signal to BBPD1. DTC M 5 with DTC C 6 is a complementary DTC. Using two complementary DTCs in a phase-locked loop circuit can improve the stability and accuracy of the system, reduce quantization errors and anti-interference capabilities, and achieve high-precision time measurement and other advantages. The two complementary DTCs can compensate each other for the timing signal to eliminate the deviation of the timing signal. Specifically, when one DTC generates an advanced compensation signal, the other DTC can generate a delayed compensation signal. The two compensate each other and ultimately achieve accurate compensation of the timing signal. This complementary method can improve the accuracy and stability of the compensation and reduce errors caused by changes in circuit parameters or environmental factors. In practical applications, the two complementary DTCs can be used in combination to achieve better compensation effects.

[0059] Also includes MMD7, DFF M 8 and DFF C 9, MMD7, used to obtain the time quantization error according to the input signal and the feedback signal output by DSM2, and output the time quantization error to DFF M 8; DFF M 8, used to compensate the received time quantization error to obtain a first compensation signal, and output the first compensation signal to DTC and DFF respectively C 9; DFF C 9, used to modulate the received first compensation signal and the input signal to obtain a modulated signal and output it to BBPD1.

[0060] In this embodiment: DTC: Digital-to-Time Converter, digital time converter; BBPD: Bang-Bang Phase Detector, phase detector; DSM: Delta Sigma Modulator, modulator; PFD: Phase Frequency Detector, phase frequency detector; DLF: Digital Loop Filter, digital loop filter; DTC M : Digital-to-Time Converter, in this embodiment, represents a first digital time converter; DTC C : Digital-to-Time Converter, this embodiment represents a second digital time converter; MMD: Multi-Modulus Divider, multi-mode frequency divider; DFF M : Digital Frequency Synthesizer, this embodiment represents a first digital frequency synthesizer; DFF C : Digital Frequency Synthesizer, this embodiment represents a second digital frequency synthesizer.

[0061] The present invention reduces the original three DTCs to two DTCs, thereby reducing the number, thereby reducing power consumption and area; the present invention can eliminate quantization noise with a simple circuit through the LMS algorithm, thereby further improving the overall noise performance of the circuit; the present invention is a full background calibration, which is insensitive to changes in process voltage temperature (PVT) compared to the original foreground calibration + background calibration; the method based on the LMS algorithm of this patent is simple and easy to implement, requires very small area and power consumption, and has obvious advantages.

[0062] These components are interconnected and work together to achieve the basic function of the phase-locked loop: tracking and locking the frequency and phase of the input signal. The multi-mode divider, the first digital frequency synthesizer, and the second digital frequency synthesizer work together to generate accurate and programmable frequency signals to meet different application requirements. The first DTC and the second DTC convert the processed signal into a pulse signal suitable for processing by BBPD1 and control the output frequency of the digital controlled oscillator. BBPD1 and DSM2 are used to achieve phase comparison and error voltage generation to adjust the frequency and phase of the voltage-controlled oscillator to achieve system stability and accuracy. Through the coordinated work of these components, the phase-locked loop can quickly and accurately track and lock the frequency and phase of the input signal, and generate an output signal with the same frequency and phase as the input signal.

[0063] like Figure 3 The physical structure diagram of an electronic device shown in the figure may include a processor 501, a communication interface 502, a memory 503 and a communication bus 504, wherein the processor, the communication interface and the memory communicate with each other via the communication bus. The processor may call the logic instructions in the memory to execute the phase-locked loop quantization noise calibration method.

[0064] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0065] On the other hand, an embodiment of the present invention further provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the phase-locked loop quantization noise calibration method provided by the above-mentioned method embodiments.

[0066] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the phase-locked loop quantization noise calibration method provided by the above embodiments.

[0067] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0068] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A phase-locked loop quantization noise calibration method, characterized in that: The following steps are involved: The phase frequency detector correlates the feedback signal output by the modulator with the reference signal output by the phase detector to generate a gain coefficient; The gain coefficient is multiplied by a feedback signal output by the modulator to output a first gain signal; Subtracting the first gain signal from a reference signal output by the phase detector to output a second gain signal; The second gain signal is filtered by a digital loop filter to obtain a filtered signal which is output to a digital-to-time converter; The digital-to-time converter processes the filtered signal to obtain a pulse signal suitable for processing by the phase detector and outputs the pulse signal to the phase detector.

2. The phase-locked loop quantization noise calibration method according to claim 1, characterized in that: The following steps are also included: The multi-mode frequency divider obtains a time quantization error according to an input signal and a feedback signal output by the modulator; The time quantization error is compensated by a first digital frequency synthesizer to obtain a first compensation signal; The second digital frequency synthesizer receives the first compensation signal and the input signal for modulation to obtain a modulated signal; The first digital-to-time converter performs an advance compensation signal on the received first compensation signal to output a second compensation signal to the second digital-to-time converter; The second digital-to-time converter receives the second compensation signal to generate a delayed compensation signal, and obtains a third compensation signal which is output to the phase detector.

3. The phase-locked loop quantization noise calibration method according to claim 1, characterized in that: The related processing includes the acquisition of input signals, phase comparison, generation of error signals and adjustment of control voltages.

4. The phase-locked loop quantization noise calibration method according to claim 1, characterized in that: The calculation formula of the gain coefficient is e q ×K G ×T DTCM +(1-e q )×K G ×T DTCC =T IN , when T DTCC =T DTCM , K G ×T DTCM =T IN , where K G is the gain coefficient, e q is the feedback signal of the modulator output, T IN is the time quantization error of the input signal, T DTCM is the time error of the second compensation signal, T DTCC is the third compensation signal time error.

5. A phase-locked loop quantization noise calibration system, characterized in that: The phase-locked loop quantization noise calibration method applied to any one of claims 1 to 4 comprises a digital time converter, a phase detector, a modulator, a phase frequency detector and a digital loop filter, The phase frequency detector is used to perform correlation processing on the feedback signal output by the modulator to generate a gain coefficient, the gain coefficient is multiplied by the feedback signal generated by the modulator to obtain a first gain signal, and the first gain signal is transmitted to the phase detector; The phase detector is used to detect the phase difference between the input signal and the output signal of the phase-locked loop, and convert the phase difference into a corresponding error voltage signal, subtract the error voltage from the first gain signal to obtain a second gain signal, and transmit the second gain signal to the digital loop filter; The digital loop filter is used to filter the second gain signal to obtain a filtered signal, and transmit the filtered signal to the digital-to-time converter; The digital-to-time converter is used to convert the filtered signal into a pulse signal suitable for processing by the phase detector, and transmit the pulse signal to the phase detector.

6. The phase-locked loop quantization noise calibration system according to claim 5, characterized in that: The digital-to-time converter includes a first digital-to-time converter and a second digital-to-time converter. The first digital-to-time converter converts the filtered signal into a first pulse signal suitable for processing by the phase detector, and transmits the first pulse signal to the second digital-to-time converter. The second digital-to-time converter converts the first pulse signal into a second pulse signal, and transmits the second pulse signal to the phase detector.

7. The phase-locked loop quantization noise calibration system according to claim 6, characterized in that: The first digital-to-time converter and the second digital-to-time converter are complementary digital-to-time converters.

8. The phase-locked loop quantization noise calibration system according to claim 7, characterized in that: It also includes a multi-mode frequency divider, a first digital frequency synthesizer and a second digital frequency synthesizer, The multi-mode frequency divider is used to obtain a time quantization error according to an input signal and a feedback signal output by the modulator, and output the time quantization error to the first digital frequency synthesizer; The first digital frequency synthesizer is used to compensate the received time quantization error to obtain a first compensation signal, and output the first compensation signal to the digital-to-time converter and the second digital frequency synthesizer respectively; The second digital frequency synthesizer is used to modulate the received first compensation signal and input signal to obtain a modulated signal and output it to the phase detector.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the phase-locked loop quantization noise calibration method as described in any one of claims 1 to 4 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the phase-locked loop quantization noise calibration method according to any one of claims 1 to 4 is implemented.

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