Method for manufacturing stacked transistor, stacked transistor, and semiconductor device

Abstract

The application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. The method comprises: etching a fin structure on a semiconductor substrate in one time, wherein the fin structure comprises a first part and a second part stacked along a first direction, and the first part is farther away from the semiconductor substrate than the second part; forming a first transistor based on the first part, wherein the first transistor comprises: a first gate structure formed by a first gate preparation process; removing the semiconductor substrate; and forming a second transistor stacked along the first direction with the first transistor based on the second part, wherein the second transistor comprises: a second gate structure formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in preparation steps; and a heat resistance of the first gate structure is greater than a heat resistance of the second gate structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular, to a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. BACKGROUND

[0002] At present, with the deepening of Moore's Law, it is a hot issue in the industry to continue to promote the miniaturization of transistors. Stacked transistors integrate two or more transistors in the vertical space to further improve the integration density of transistors, and become one of the important technologies to continue the miniaturization of integrated circuits.

[0003] In some schemes for preparing a stacked transistor, the active regions of two layers of homologous transistors are formed by etching, and the stacked transistors are fabricated on the front and back surfaces of a wafer by peeling. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, some preparation processes are not resistant to high temperature. Therefore, there is still a lot of room for improvement for the "self-aligned flip transistor" scheme. SUMMARY

[0004] The present application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device to form a gate structure that is more resistant to high temperature on the front surface of a wafer, so that on the one hand, the thermal budget of the back transistor can be improved, and the flexibility of the back transistor can be improved, and on the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing a stacked transistor can be ensured.

[0005] In a first aspect, an embodiment of the present application provides a preparation method of a stacked transistor, comprising: etching a fin structure on a semiconductor substrate at one time, wherein the fin structure comprises a first part and a second part stacked along a first direction, and the first part is farther away from the semiconductor substrate than the second part; based on the first part, forming a first transistor, wherein the first transistor comprises: a first gate structure, and the first gate structure is formed by a first gate preparation process; peeling and removing the semiconductor substrate; based on the second part, forming a second transistor stacked along the first direction with the first transistor, wherein the second transistor comprises: a second gate structure, and the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in preparation steps; and the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure.

[0006] In some embodiments, based on the first portion, forming the first transistor comprises: depositing a first gate dielectric material within the gate region of the stacked transistor to form a first gate dielectric layer covering the first portion; depositing a metal oxide material on the first gate dielectric layer to form a covering layer; depositing a first gate material on the covering layer to form a first gate electrode layer, wherein the first gate dielectric layer, the covering layer and the first gate electrode layer collectively constitute a first gate structure; the preparation steps of forming the first gate structure are included in a first gate preparation process; based on the first portion, forming a first source-drain structure within the source-drain region of the stacked transistor, wherein the first source-drain structure and the first gate structure collectively constitute the first transistor.

[0007] In some embodiments, when the first transistor is an N-type field effect transistor, the metal oxide material is lanthanum oxide; when the first transistor is a P-type field effect transistor, the metal oxide material is aluminum oxide.

[0008] In some embodiments, based on the second portion, forming the second transistor comprises: depositing a dummy gate material within the gate region of the stacked transistor to form a dummy gate structure; based on the second portion, forming a second source-drain structure within the source-drain region of the stacked transistor; removing the dummy gate structure and depositing a second gate dielectric material at the location where the dummy gate structure is removed to form a second gate dielectric layer; depositing a second gate material on the second gate dielectric layer to form a second gate electrode layer; wherein the second gate dielectric layer and the second gate electrode layer collectively constitute a second gate structure; the preparation steps of forming the second gate structure are included in a second gate preparation process; the second source-drain structure and the second gate structure collectively constitute the second transistor.

[0009] In some embodiments, when the first transistor is an N-type field effect transistor, after forming the second transistor based on the second portion, the method further comprises: bonding the second transistor to a carrier wafer; and stripping the second transistor after bonding.

[0010] In some embodiments, when the first transistor is a P-type field effect transistor, the first portion is formed of a silicon germanium material.

[0011] In some embodiments, the fin structure further comprises a third portion between the first portion and the second portion; after forming the dummy gate structure, the preparation method further comprises: removing the third portion and depositing an insulating material at the location where the third portion is removed to form an isolation layer, wherein the isolation layer is used to electrically isolate the first portion and the second portion.

[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, comprising: a first transistor; a second transistor, the first transistor and the second transistor are stacked along a first direction, a first active region of the first transistor is self-aligned with a second active region of the second transistor; the first transistor comprises a first gate structure, the second transistor comprises a second gate structure, the first gate structure and the second gate structure are oppositely arranged; the first gate structure is formed by a first gate preparation process; the first active region is formed based on a first part of a fin structure, and the second active region is formed based on a second part of the fin structure; the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in a preparation step; and a heat resistance of the first gate structure is greater than a heat resistance of the second gate structure.

[0013] In some embodiments, when the first transistor is a P-type field effect transistor, the first active region of the first transistor is formed of a silicon germanium material.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: the stacked transistor as described in the above embodiments.

[0015] In the embodiments of the present disclosure, by etching the fin structure on the semiconductor substrate at one time, and based on the first part and the second part of the fin structure, the first transistor and the second transistor are respectively prepared and formed on the front and back surfaces of the semiconductor substrate, the active structures of the upper and lower transistors in the stacked transistor can be self-aligned. Meanwhile, the first gate structure of the first transistor is prepared by the first preparation process, and the second gate structure of the second transistor is prepared by the second preparation process, so that the heat resistance of the first gate structure is greater than the heat resistance of the second gate structure. In this way, on the one hand, the thermal budget of the back transistor can be improved, and the flexibility of the back transistor can be improved, and on the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing the stacked transistor can be ensured.

[0016] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings herein are incorporated into the description and form part of the description, show embodiments consistent with the present application, and together with the description, serve to explain the principles of the present application.

[0018] Figure 1 An implementation flowchart of a preparation method of the stacked transistor according to an embodiment of the present application is shown;

[0019] Figure 2 A top view of the first stacked transistor according to an embodiment of the present application is shown;

[0020] Figures 3 to 34 FIG. 1 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application;

[0021] Figures 35 to 37 FIG. 2 is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application.

[0022] FIG. 10, stacked transistor; FIG. 11, first transistor; FIG. 12, second transistor; FIG. 111, first side wall; FIG. 112, first source-drain structure; FIG. 113, first interlayer dielectric layer; FIG. 114, first gate structure; FIG. 115, first source-drain metal; FIG. 116, first metal interconnection layer; FIG. 121, second dummy gate side wall; FIG. 122, second source-drain structure; FIG. 123, second interlayer dielectric layer; FIG. 124, second gate structure; FIG. 125, second source-drain metal; FIG. 126, second metal interconnection layer;

[0023] 20, semiconductor substrate; 21, third material layer; 22, first material layer; 23, second material layer; 24, first part; 25, second part; 26, third part; 27, shallow trench isolation structure; 28, front side oxide layer; 29, first gate dielectric layer; 30, cover layer; 31, first gate electrode layer; 32, first source-drain recess; 33, insulating layer; 34, carrier wafer; 35, back side oxide layer; 36, initial dummy gate structure; 37, dummy gate structure; 38, second side wall; 39, isolation layer; 40, source-drain isolation structure; 41, second source-drain recess; 42, second gate dielectric layer; 43, second gate electrode layer; 44, gate isolation structure. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the drawings. Descriptions of well-known functions and structures incorporated herein can be omitted to avoid obscuring the subject matter of the present application. The following description is presented in terms of exemplary embodiments, which are shown in the drawings. Those skilled in the art will recognize that alternative embodiments of the present application can be constructed without departing from the spirit and scope of the present application.

[0025] In the context of Moore's Law, it is a hot issue to continue to push the miniaturization of transistors. The stacked transistor can integrate two or more layers of transistors in the vertical space by stacking three-dimensional transistors, which helps to further improve the transistor integration density and circuit performance, and is considered as one of the important technologies to continue the miniaturization of integrated circuits.

[0026] In an embodiment, there are two schemes for the preparation process of the stacked transistor, the first one is a monolithic scheme, and the second one is a sequential scheme.

[0027] The first solution is to fabricate N field effect transistors (NFET) and P field effect transistors (PFET) on the same substrate without wafer bonding technology. This determines that the same layer transistors must be of the same type, that is, NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same plane space, and there is no alignment deviation. The advantage of this solution is better integration density. However, the following technical challenges exist in this solution: (1) complex process, a large amount of process technology development and optimization are required; (2) the polarity of each layer of transistors is fixed, and two layers of transistors must be used to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, and the design flexibility is poor.

[0028] The second solution is to bond a wafer on the top of the fabricated lower layer transistors, and to fabricate the upper layer transistors by using the bonded wafer, so as to vertically stack the two transistors. However, in the process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and the interconnection lines between the upper and lower layers of transistors. The advantage of this solution is that due to wafer bonding, the device structures, channel crystal directions and even channel materials of the upper and lower layers of transistors can be different to obtain better and more matched device performance. However, the following technical challenges exist in this solution: (1) preparation of high-quality top layer transistor active layer; (2) thinning and defect control of the top layer transistor bonding wafer; (3) alignment error between the upper and lower layers of transistors, and high precision requirement for photolithography.

[0029] The common technical difficulties faced by the above two solutions include: (1) thermal stability of the bottom layer device when fabricating the top layer device; (2) performance of the top layer device under low thermal budget; (3) metal interconnection between the top layer and the bottom layer transistors.

[0030] To solve the above technical problems, the disclosure embodiments propose a flip solution for realizing self-aligned stacked transistors, which forms active regions of upper and lower layer homologous transistors by etching, and realizes fabrication of stacked transistors on the front and back surfaces of a wafer by flipping, to overcome the disadvantages of the above two solutions. This can also be called a "self-aligned flip transistor" solution. However, in the "self-aligned flip transistor" solution, part of the preparation process has a problem of not being resistant to high temperature. Therefore, there is still a large room for improvement for the "self-aligned flip transistor" solution.

[0031] To solve the above technical problems, the embodiment of the present application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device, so as to form a gate structure with higher temperature resistance on the front surface of the wafer, so that on the one hand, the thermal budget of the back transistor can be improved, and the flexibility of the back transistor can be improved, and on the other hand, the failure rate of the front transistor can be reduced, and the success rate of preparing the stacked transistor can be ensured.

[0032] Meanwhile, when the first transistor in the stacked transistor is an NFET, a layer of lanthanum oxide covering layer is deposited on the channel corresponding to the NFET, which can increase the negative electric atoms, thereby effectively reducing the threshold voltage of the NFET. When the first transistor in the stacked transistor is a PFET, a channel is prepared by using a silicon germanium material, so as to increase the carrier mobility and reduce the threshold voltage of the PFET, and further improve the electrical performance of the PFET.

[0033] Further, in order to compensate the temperature influence, the back interconnection structure in the stacked transistor can use high-temperature-resistant metal materials such as ruthenium (Ru) or tungsten (W), so that the front transistor prepared first in the stacked transistor can withstand higher temperature.

[0034] In a first aspect, the embodiment of the present application provides a preparation method of a stacked transistor. Figure 1 For the implementation flowchart of the preparation method of the stacked transistor according to the embodiment of the present application, see Figure 1 As shown in the figure, the preparation method of the stacked transistor can include:

[0035] Step S101: etching once to form a fin structure on a semiconductor substrate, wherein the fin structure includes a first part and a second part stacked along a first direction, and the first part is farther away from the semiconductor substrate than the second part;

[0036] Step S102: forming a first transistor based on the first part, wherein the first transistor includes: a first gate structure, and the first gate structure is formed by a first gate preparation process;

[0037] Step S103: developing and removing the semiconductor substrate;

[0038] Step S104: forming a second transistor stacked along the first direction with the first transistor based on the second part, wherein the second transistor includes: a second gate structure, and the second gate structure is formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in preparation steps; and the heat resistance of the first gate structure is greater than that of the second gate structure.

[0039] It is understood that both the first gate fabrication process and the second gate fabrication process include multiple aspects such as fabrication steps, fabrication flow, and structural materials. In the embodiments of this application, the first gate fabrication process and the second gate fabrication process differ at least in the fabrication steps, thereby enabling the acquisition of gate structures with different heat resistances.

[0040] In some embodiments, the first gate fabrication process and the second gate fabrication process differ in at least the number of fabrication steps. In one embodiment, the first gate fabrication process may have more steps than the second gate fabrication process, thereby realizing more material layers in the first gate structure and improving the heat resistance of the first gate structure.

[0041] In some embodiments, the first gate fabrication process and the second gate fabrication process may differ not only in the fabrication steps, but also in the execution order of the fabrication steps (i.e., the fabrication process) and / or in the materials used to perform the fabrication steps (i.e., the structural material).

[0042] It is understandable that different execution sequences of fabrication steps or different materials used in the steps can lead to different gate structures, thereby obtaining gate structures with different heat resistances. In the embodiments of this application, the heat resistance of the first gate structure is controlled to be relatively high. After the semiconductor substrate is flipped, a higher temperature can be used to fabricate the reverse transistor. On the one hand, this can improve the thermal budget of the reverse transistor and enhance its flexibility; on the other hand, it can reduce the failure rate of the front transistor and ensure the success rate of fabricating stacked transistors.

[0043] It should be noted that the first direction in the embodiments of this application can be a direction perpendicular to the semiconductor substrate, or it can be understood as the height direction of the fin structure. The second direction can be perpendicular to the first direction. The second direction can be understood as the length direction of the fin structure. The second direction is, for example, the length direction of the gate structure. The third direction can be perpendicular to the first and second directions. The third direction can be understood as the extension direction of the fin structure. The third direction is, for example, the width direction of the gate structure.

[0044] The following will combine Figure 1 The preparation method described herein is illustrated by way of example.

[0045] In step S101, a fin-like structure is formed by etching on the semiconductor substrate in one step.

[0046] The fin-shaped structure includes a first portion and a second portion stacked along a first direction, and the first portion is farther away from the semiconductor substrate than the second portion. The first portion of the fin-shaped structure can be used to form an active region of a front-side transistor (i.e., a first transistor) in the stacked transistor; and the second portion stacked along the first direction with the first portion is used to form an active region of a back-side transistor (i.e., a second transistor) in the stacked transistor.

[0047] In some embodiments, step S101 can include performing a material layer deposition, epitaxial growth, photolithography, or the like on the semiconductor substrate to form the fin-shaped structure on the semiconductor substrate at one time. The fin-shaped structure includes a first portion and a second portion, and the second portion is closer to the semiconductor substrate than the first portion.

[0048] In some embodiments, according to the fin-shaped structure, a fin field effect transistor can be formed.

[0049] In some embodiments, when the fin-shaped structure (including the first portion and the second portion) is etched at one time, a larger etching depth can be used. For example, the height of the fin-shaped structure obtained by etching can be greater than 100 nm. It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiments of the present application do not limit this.

[0050] In some embodiments, the etching process mentioned in the embodiments of the present application can include any one of dry etching, wet etching, reactive ion etching, and chemical oxide removal process, and the embodiments of the present application do not limit this. In an embodiment, the etching to form the fin-shaped structure can use a photolithography process. In an embodiment, the steps of the photolithography process can include depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, and the like.

[0051] In some embodiments, the first transistor and the second transistor are both fin field effect transistors.

[0052] In some embodiments, step S101 can include forming a first material layer and a second material layer stacked along a first direction on the semiconductor substrate, and then etching the first material layer and the second material layer from top to bottom in sequence to obtain the first portion and the second portion, respectively. Here, the first material layer after etching can form the first portion; and the second material layer after etching can form the second portion.

[0053] In some embodiments, step S101 can include electrically isolating the first portion and the second portion. It can be understood that the first portion and the second portion can be electrically isolated in various ways such as forming an isolation layer, forming an insulating layer, ion implantation, and the like. The embodiments of the present application do not limit this.

[0054] In some embodiments, the step S101 can include: providing a wafer; etching the wafer to form an initial fin structure with a preset depth; removing the initial fin structure in the regions on both sides of the stacked transistors in the third direction by a fin cutting process to form the fin structure. Ion implantation is performed on the middle part of the fin structure to electrically isolate the first part and the second part. Here, the regions on both sides of the stacked transistors in the third direction refer to the regions on both sides of the stacked transistors in the cross-sectional view in the C-C' direction.

[0055] It can be understood that the initial fin structure in the regions on both sides of the stacked transistors can be removed by the fin cutting process, so that the fin structures of the plurality of standard transistor units are disconnected with each other, and the isolation between the adjacent transistor units is completed. For example, the ions of the ion implantation include P-type ions, N-type ions or oxygen ions. The P-type ions include one or more of boron ions, gallium ions and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0056] In some embodiments, the step S101 can include: forming a first material layer, a third material layer and a second material layer stacked along a first direction on a semiconductor substrate, and then etching the first material layer, the third material layer and the second material layer from top to bottom in sequence to obtain the first part, the third part and the second part, respectively. The third part is located between the first part and the second part. The etched first material layer can form the first part; the etched second material layer can form the second part; and the etched third material layer can form the third part.

[0057] In an embodiment, the third part is used to electrically isolate the first part and the second part. In an embodiment, the third part can be formed of an oxide material. In an embodiment, the third part can be formed of a dielectric material.

[0058] In some embodiments, the material of the material layer forming the first part, the second part and the third part can be selected according to actual needs. In an embodiment, when the first transistor is a P-type field effect transistor, the material forming the first part can be a silicon germanium material.

[0059] In some embodiments, after the fin structure is obtained, an insulating material can be deposited on the semiconductor substrate to obtain a shallow trench isolation structure. Here, the shallow trench isolation structure can wrap the second part, and the first part can be exposed outside the shallow trench isolation structure.

[0060] The oxide forming the shallow trench isolation structure 24 can be a silicon-based oxide (SiOx, x is the number of oxygen atoms), such as silicon dioxide (SiO2) and the like.

[0061] In step S102, based on the first portion, a first transistor of the stacked transistor is formed.

[0062] It can be understood that the first transistor in the stacked transistor can be formed based on the exposed first portion by using a semiconductor manufacturing process. The first transistor includes a first dummy gate sidewall, a first source-drain structure, a first interlayer dielectric layer, a first gate structure, and a first source-drain metal. The first gate structure can be formed by using a first gate manufacturing process.

[0063] In some embodiments, step S102 can include: depositing a first gate dielectric material in a gate region of the stacked transistor to form a first gate dielectric layer covering the first portion; depositing a metal oxide material on the first gate dielectric layer to form a covering layer; and depositing a first gate material on the covering layer to form a first gate electrode layer, wherein the first gate dielectric layer, the covering layer, and the first gate electrode layer together constitute the first gate structure; the manufacturing steps of the first gate structure are included in the first gate manufacturing process; and based on the first portion, a first source-drain structure is formed in a source-drain region of the stacked transistor.

[0064] It can be understood that the first gate manufacturing process can include the steps of forming the first gate dielectric layer, forming the covering layer, and forming the first gate electrode layer. Through the above steps, the first gate structure with greater heat resistance can be obtained. It can be understood that the first gate structure can be directly formed by the first gate manufacturing process without forming a dummy gate structure, and thus the use of a metal gate to replace the dummy gate structure can reduce the process complexity.

[0065] It can be understood that the covering layer is located between the first gate dielectric layer and the first gate electrode layer, and the covering layer can solve the Fermi level pinning phenomenon and adjust the threshold voltage of the transistor.

[0066] In some embodiments, the metal oxide material forming the covering layer can be selected according to actual needs, for example, hafnium oxide, aluminum oxide, titanium oxide, etc., which are not limited in the embodiments of the present application. In an embodiment, when the first transistor is an N-type field effect transistor, the metal oxide forming the covering layer can be lanthanum oxide. The lanthanum oxide material contains more negative atoms, thereby being able to reduce the threshold voltage (Vt) of the N-type field effect transistor. In an embodiment, when the first transistor is a P-type field effect transistor, the metal oxide forming the covering layer can be aluminum oxide. The aluminum oxide material contains more positive atoms, thereby being able to reduce the threshold voltage (Vt) of the P-type field effect transistor.

[0067] In some embodiments, the first gate dielectric material can be a high dielectric constant (K) material. In some embodiments, the first gate material can be a polysilicon or a metal material. Here, for an N-type field effect transistor, the metal material can be tantalum nitride, tantalum, etc.; for a P-type field effect transistor, the metal material can be titanium nitride, tungsten, cobalt, etc.

[0068] In some embodiments, step 102 can include forming a first gate isolation structure within the gate isolation region. It can be appreciated that after the first gate structure is formed, a gate cut-off process can be employed to remove the first gate structure on both sides of the stacked transistor in the second direction, and deposit an insulating material at the location where the first gate structure is removed, to form the first gate isolation structure. The first gate isolation structure is used to electrically isolate the gate structures of two adjacent first transistors.

[0069] In some embodiments, step S104 can include forming a first gate dielectric layer across the first portion based on the exposed first portion, and sequentially depositing a cap layer and a first gate electrode layer on the first gate dielectric layer to form the first gate structure. After the first gate structure is formed, a sidewall material can also be deposited to form a first sidewall. Here, the sidewall material can be a silicon oxide, silicon nitride, etc. The first sidewall is used to protect the covered structure.

[0070] In some embodiments, after the first gate structure is formed, a semiconductor preparation standard process can be employed to form a first source / drain structure. Then, step S102 can include forming a first source / drain structure of the first transistor based on the first portion. In some embodiments, the first portion within the source / drain region of the stacked transistor can be etched to form a first source / drain recess; and a first source / drain structure can be epitaxially grown within the first source / drain recess. After the first source / drain structure is formed, an insulating material can be deposited on the first source / drain structure to form a first interlayer dielectric layer. In an embodiment, a fin recess process can be employed to form the first source / drain recess on the first portion. In an embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the first source / drain recess by selective epitaxial growth to fill the first source / drain recess, and then a first source / drain structure can be formed on the strained material by a heavy doping process.

[0071] In some embodiments, after the first gate structure is formed, the first interlayer dielectric layer can be etched to expose the first source / drain structure, and a metal material can be deposited on the first source / drain structure to form a first source / drain metal.

[0072] In an embodiment, after the first gate structure and the first source-drain metal are formed, a first metal interconnection layer can be formed on the first gate structure and the first source-drain metal by using standard post-processes of semiconductor manufacturing (such as interconnection medium deposition, metal line formation, and lead pad formation).

[0073] In an embodiment, the metal lines in the first metal interconnection layer can be made of high-temperature-resistant metal materials such as ruthenium (Ru) or tungsten (W), so as to improve the high-temperature resistance of the first transistor.

[0074] It should be noted that, for the sake of convenience, the first source-drain structure mentioned in the embodiments of the present application is a short form, and specifically refers to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, and the like are similar to the first source-drain recess, and "source-drain" is a short form of "source and / or drain".

[0075] In step S103, the semiconductor substrate is inverted and removed.

[0076] It can be understood that, after the first transistor is obtained, the first transistor can be inverted so that the first transistor manufactured is located at the bottom, and the second part for manufacturing the second transistor can be located at the upper part, so as to facilitate subsequent manufacturing of the second transistor.

[0077] In some embodiments, after the post-process of the first transistor is completed, the first transistor can be bonded with a carrier wafer. For example, after the first metal interconnection layer is deposited with an insulating material (such as silicon oxide), an insulating layer can be formed, and the insulating layer can be bonded with the carrier wafer and inverted so that the first transistor is located at the lower layer of the stacked transistor after inversion.

[0078] In the embodiments of the present disclosure, the carrier wafer after bonding can provide physical support for the inverted first transistor after inversion, effectively preventing the first transistor from being broken by external force during the manufacturing of the second transistor.

[0079] In an embodiment, after inversion, the semiconductor substrate can be removed by using a polishing process or a chemical mechanical planarization process, so as to expose the second part.

[0080] In step S104, based on the second part, a second transistor of the stacked transistor is formed.

[0081] It can be understood that after the first transistor is formed, the second transistor in the stacked transistor can be formed based on the exposed second part by using a semiconductor manufacturing process. The second transistor includes a second dummy gate sidewall, a second source-drain structure, a second interlayer dielectric layer, a second gate structure, and a second source-drain metal. The second gate structure can be formed by using a second gate manufacturing process. The second gate manufacturing process is different from the first gate manufacturing process.

[0082] In some embodiments, step S104 can include: depositing a dummy gate material in a gate region of the stacked transistor to form a dummy gate structure; forming a second source-drain structure in a source-drain region of the stacked transistor based on the second part; removing the dummy gate structure and depositing a second gate dielectric material at a position where the dummy gate structure is removed to form a second gate dielectric layer; depositing a second gate material on the second gate dielectric layer to form a second gate electrode layer; wherein the second gate dielectric layer and the second gate electrode layer together constitute the second gate structure; and the manufacturing steps of forming the second gate structure are included in the second gate manufacturing process.

[0083] It can be understood that the second gate manufacturing process can include the steps of forming the dummy gate structure, removing the dummy gate structure, forming the second gate dielectric layer, and forming the second gate electrode layer. Through the above steps, the second gate structure can be obtained. The heat resistance of the second gate structure is less than that of the first gate structure, but the second gate structure has the advantages of reducing power consumption and leakage, improving carrier mobility, and the like, which are superior to the first gate structure. It can be understood that the second gate structure is formed by the second gate manufacturing process, which requires forming the dummy gate structure first and then forming the second gate structure.

[0084] In some embodiments, the second gate dielectric material can be a high dielectric constant (K) material. In some embodiments, the material forming the second gate dielectric layer can be the same as or different from the material forming the first gate dielectric layer. In some embodiments, the second gate material can be a metal oxide material. In an example, the second gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the second transistor. The second gate electrode layer can be composed of multiple layers of electrode materials, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In an example, the second gate dielectric layer can include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0085] In some embodiments, step S104 can include: thinning the shallow trench isolation structure to expose a second portion wrapped by the shallow trench isolation structure; forming a dummy gate structure across the second portion and a second dummy gate spacer covering sidewalls of the dummy gate structure; after the first source / drain structure is prepared, removing the dummy gate structure using a gate replacement process and depositing a second gate structure at locations where the dummy gate structure is removed. Here, the second dummy gate spacer can be formed based on a spacer material.

[0086] In some embodiments, step 104 can include: forming a second gate isolation structure within the gate isolation region. It can be understood that after the second gate structure is formed, a gate cut-off process can be used to remove the second gate structure located on both sides of the stacked transistor in the second direction and deposit an insulating material at locations where the second gate structure is removed to form the second gate isolation structure. The first gate isolation structure and the second gate isolation structure are arranged in a stack along the first direction. The second gate isolation structure is used to electrically isolate gate structures of two adjacent second transistors.

[0087] In some embodiments, when the first gate isolation structure is not formed in the stacked transistor, step 104 can include: forming a third gate isolation structure within the gate isolation region. It can be understood that after the second gate structure is formed, a gate cut-off process can be used to remove the second gate structure and the first gate structure located on both sides of the stacked transistor in the second direction and deposit an insulating material at locations where the second gate structure and the first gate structure are removed to form the third gate isolation structure. The third gate isolation structure is used to electrically isolate gate structures of two adjacent stacked transistors.

[0088] In some embodiments, when the fin structure further includes a third portion located between the first portion and the second portion, before the dummy gate structure is formed, step S104 can include: removing the third portion and depositing an insulating material at locations where the third portion is removed to form an isolation layer. It can be understood that the isolation layer is used to electrically isolate the first portion and the second portion.

[0089] In some embodiments, after the second gate structure is formed, a semiconductor manufacturing standard process can be used to form the second source / drain structure. Then, step S104 can include forming the second source / drain structure of the second transistor based on the second portion. In some embodiments, the second portion within the source / drain region of the stacked transistor can be etched to form a second source / drain recess, and a second source / drain structure can be epitaxially grown in the second source / drain recess. After the second source / drain structure is formed, an insulating material can be deposited on the second source / drain structure to form a second interlayer dielectric layer. In an embodiment, a fin-type structure deep etching process can be used to form the second source / drain recess on the second portion. In an embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the second source / drain recess by selective epitaxial growth to fill the second source / drain recess, and then a second source / drain structure can be formed on the strained material by a heavy doping process.

[0090] In some embodiments, after the second gate structure is formed, the second interlayer dielectric layer can be etched to expose the second source / drain structure, and a metal material can be deposited on the second source / drain structure to form a second source / drain metal.

[0091] In an embodiment, after the second gate structure and the second source / drain metal are formed, a second metal interconnection layer can be formed on the second gate structure and the second source / drain metal by using a semiconductor manufacturing standard back-end process (such as interconnection line interlayer dielectric deposition, metal line formation, lead pad formation, etc.).

[0092] In some embodiments, when the first transistor is an N-type field effect transistor, the first metal interconnection layer can not be formed in step S102, and thus after step S104, the second transistor can be flipped, and the first metal interconnection layer can be formed on the first source / drain structure and the first gate structure.

[0093] It can be understood that when the first transistor is an N-type field effect transistor and the second transistor is a P-type field effect transistor, the first transistor can be placed at the upper layer and the second transistor can be placed at the lower layer to improve the performance of the stacked transistor in use, considering the stress effect in the stacked transistor. Accordingly, in some embodiments, when the first transistor is an N-type field effect transistor and the first metal interconnection layer is formed in step S102, the second transistor is a P-type field effect transistor, and the second metal interconnection layer is formed in step S104. At this time, the first transistor and the second transistor can also be flipped so that the first transistor is located at the upper layer and the second transistor is located at the lower layer.

[0094] In some embodiments, when the first transistor is an N-type field-effect transistor, a first metal interconnect layer can be formed in step S102, and a second metal interconnect layer can be formed in step S104. Therefore, after step S104, the method further includes: bonding the second transistor to a carrier wafer; and flipping the bonded second transistor.

[0095] Understandably, in order to improve the performance of stacked transistors during use, N-type field-effect transistors can be placed on the upper layer of the stacked transistors and the second transistor can be placed on the lower layer of the stacked transistors by bonding carrier wafers and flipping.

[0096] This completes the fabrication process of the first stacked transistor.

[0097] In this embodiment, by etching a fin-like structure onto a semiconductor substrate in a single step, and fabricating a first transistor and a second transistor on the front and back sides of the semiconductor substrate respectively based on the first and second portions of the fin-like structure, the active structures of the upper and lower transistor layers in the stacked transistor can be self-aligned. Simultaneously, a first gate structure for the first transistor is fabricated using a first fabrication process, and a second gate structure for the second transistor is fabricated using a second fabrication process, resulting in a higher heat resistance for the first gate structure than for the second gate structure. This improves the thermal budget of the reverse transistor, enhancing its flexibility, while also reducing the failure rate of the front transistor, ensuring a higher success rate in fabricating the stacked transistor.

[0098] The following is a specific example illustrating the fabrication method of the stacked transistors in the embodiments of this application.

[0099] Figure 2 This is a top view illustrating a first type of stacked transistor according to an embodiment of this application. See also... Figure 2 As shown, the top view only shows the fin structure, gate structure, and source / drain structure of the stacked transistors. Figures 3 to 34 This is a schematic diagram illustrating the fabrication process of a first type of stacked transistor according to an embodiment of this application. For ease of understanding, Figures 3 to 34 (a) in the middle shows along Figure 2 A cross-sectional view along the direction of the dashed line AA'. Figures 3 to 34 (b) shows along Figure 2 A cross-sectional view along the direction of the dashed line BB'. Figures 3 to 34 (c) in the middle shows the direction along Figure 2 A cross-sectional view along the direction of the dashed line CC'.

[0100] In this embodiment, it is assumed that the first transistor is a P-type field-effect transistor and the second transistor is an N-type field-effect transistor. The following will combine... Figures 1 to 34A possible implementation of the stacked transistor provided in this embodiment is described.

[0101] In the first step, referring to Figure 3 As shown in the figure, a third material layer 21 and a first material layer 22 are respectively formed on a semiconductor substrate 20 (formed of silicon material) by epitaxy. The first material layer 22 is formed of silicon germanium material, and the third material layer 21 is formed of silicon germanium material. The germanium atom content percentage of the silicon germanium in the first material layer 22 and the silicon germanium in the third material layer 21 is different. The first material layer 22 can be prepared to form a channel (PFET channel) of the first transistor 11, and the third material layer 21 can be prepared to form an isolation layer between the first transistor 11 and the second transistor 12. Meanwhile, a part of the semiconductor substrate 20 close to the third material layer 21 can be understood as a second material layer 23, and the second material layer 23 can be prepared to form a channel (NFET channel) of the second transistor 12.

[0102] In the second step, referring to Figure 4 As shown in the figure, the first material layer 22, the third material layer 21 and the second material layer 23 are etched in sequence to form an initial fin structure. The initial fin structure located on both sides of the semiconductor substrate 20 in the third direction is removed to obtain a fin structure.

[0103] It can be understood that the location on both sides of the semiconductor substrate 20 in the third direction refers to the location on both sides in the C-C' direction. The fin structure includes a first part 24, a second part 25 and a third part 26, and the third part 26 is located between the first part 24 and the second part 25. The first part 24 is formed of the first material layer 22, the second part 25 is formed of the second material layer 23, and the third part 26 is formed of the third material layer 21.

[0104] In the third step, referring to Figure 5 As shown in the figure, an insulating material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 27 covering the fin structure, and a chemical-mechanical planarization (CMP) process is performed on the shallow trench isolation structure 27 to ensure that the shallow trench isolation structure 27 in any area has the same height. It can be understood that the height of the shallow trench isolation structure 27 in the first direction after the chemical-mechanical planarization process is slightly higher than that of the fin structure.

[0105] In the fourth step, referring to Figure 6 As shown in the figure, an etching process is used to etch the shallow trench isolation structure 27 until the first part of the fin structure is exposed. Here, the etched shallow trench isolation structure 27 can expose the first part 24, and wrap the third part 26 and the second part 25.

[0106] In the fifth step, referring to Figure 7As shown, an isotropic deposition process is used to deposit oxide material on the shallow trench isolation structure 27 to form a front oxide layer 28. Here, the front oxide layer 28 is used to protect the fin structure and improve the reliability and performance of the device. Understandably, the front oxide layer 28 can cover the upper surface of the shallow trench isolation structure 27, the upper surface of the fin structure, and the sidewalls of the fin structure.

[0107] Step 6, see Figure 8 As shown, an isotropic deposition process is used to deposit a first gate dielectric material on the front oxide layer 28 to form a first gate dielectric layer 29. It is understood that when the first transistor 11 is a P-type field-effect transistor, the first gate dielectric material can be materials such as hafnium dioxide, zirconium dioxide, silicon nitride, lanthanum trioxide, and titanium nitride.

[0108] Step 7, see Figure 9 As shown, an isotropic deposition process is used to deposit a metal oxide material on the first gate dielectric layer 29 to form the capping layer 30 of the P-type field-effect transistor. Here, the metal oxide material can be aluminum oxide.

[0109] Step 8, see Figure 10 As shown, an isotropic deposition process is used to deposit a first gate material on the capping layer 30 to form a first gate electrode layer 31, and the first gate electrode layer 31 is subjected to chemical mechanical planarization. It is understood that when the first transistor 11 is a P-type field-effect transistor, the first gate material can be polysilicon, titanium nitride, tantalum nitride, or other materials.

[0110] Step 9, see Figure 11 As shown, the first gate dielectric layer 29, capping layer 30, and first gate electrode layer 31 in the front source / drain region are removed by photolithography to form a first gate structure 114 in the front gate region. Here, the photolithographically removed first gate dielectric layer 29, capping layer 30, and first gate electrode layer 31 together constitute the first gate structure 114. The height of the first gate structure 114 in the first direction is greater than the height of the fin structure in the first direction. Figure 11 In the CC' cross-sectional view, the first gate structure 114 is arranged at intervals along the third direction.

[0111] Step 10, see Figure 12 As shown, an isotropic deposition process is used to deposit sidewall material (such as silicon nitride) in the gate region and source / drain region of the front-side transistor to form an initial dummy gate sidewall that completely covers the first gate structure 114 and the first portion 24. Then, an anisotropic etching process is used to etch the initial dummy gate sidewall to form the first sidewall 111. Here, the first sidewall 111 can cover the sidewalls of the first gate structure 114 and the first portion 24.

[0112] Eleventh step, refer to Figure 13 As shown, a portion of the first portion 24 of the fin structure and the corresponding first side wall 111 are removed by a deep etching process to form the first source / drain recess 32.

[0113] Twelfth step, refer to Figure 14 As shown, when the first transistor 11 is a P-type field effect transistor, a germanium-silicon epitaxial layer can be formed in the first source / drain recess 32 by epitaxial growth, and then a first source / drain structure 112 can be formed based on the germanium-silicon epitaxial layer by a heavy doping process.

[0114] Thirteenth step, refer to Figure 15 As shown, after the first source / drain structure 112 is formed, an insulating material is deposited on the first source / drain structure 112 to form a first interlayer dielectric layer 113, and a chemical mechanical planarization process is used to process the first interlayer dielectric layer 113 to make the height of the first transistor 11 uniform. The insulating material can be silicon nitride, silicon oxide, or the like.

[0115] Fourteenth step, refer to Figure 16 As shown, the first interlayer dielectric layer 113 is etched to expose the first source / drain structure 112, and a metal material is deposited on the first source / drain structure 112 to form a first source / drain metal 115.

[0116] Fifteenth step, refer to Figure 17 As shown, a standard back-end-of-line process of semiconductor manufacturing (such as interconnection dielectric deposition, metal line formation, and lead pad formation) is used to form a first metal interconnection layer 116 on the first gate structure 114 and the first source / drain metal 115. In an embodiment, the metal lines in the first metal interconnection layer 116 can be made of a high-temperature-resistant metal material such as ruthenium (Ru) or tungsten (W), thereby improving the high-temperature resistance of the first transistor.

[0117] Sixteenth step, refer to Figure 18 As shown, the semiconductor substrate 20 is developed to make the first transistor 11 located at the lower layer. An insulating material is deposited on the top of the first metal interconnection layer 116 to form an insulating layer 33, and the insulating layer 33 is bonded to a wafer carrier 34. The bonded first transistor 11 is flipped to make the first transistor 11 located at the lower layer.

[0118] Seventeenth step, refer to Figure 19 As shown, an etching process is used to remove the semiconductor substrate 20 until the shallow trench isolation structure 27 is exposed, and the upper surface of the second portion 25 can also be exposed.

[0119] Eighteenth step, refer to Figure 20As shown, an etching process is performed to thin the shallow trench isolation structure 27 so that the second portion 25 is exposed outside the thinned shallow trench isolation structure 27. The thinned shallow trench isolation structure 27 can wrap the third portion 26. The thinned shallow trench isolation structure 27 has a certain thickness in the first direction, which can be used to electrically isolate the first transistor 11 and the second transistor 12.

[0120] Nineteenth step, see Figure 21 As shown, an isotropic deposition process is performed to deposit an oxide material on the shallow trench isolation structure 27 to form a backside oxide layer 35. The backside oxide layer 35 can have the same function as the frontside oxide layer 28, which will not be repeated here. The oxide material used to form the frontside oxide layer 28 can be the same as or different from the oxide material used to form the backside oxide layer 35.

[0121] Twentieth step, see Figure 22 As shown, an isotropic deposition process is performed to deposit a dummy gate material (polysilicon) on the backside oxide layer 35 to form an initial dummy gate structure 36, and a chemical mechanical planarization process is performed on the initial dummy gate structure 36.

[0122] Twenty-first step, see Figure 23 As shown, a photolithography process is performed to remove the initial dummy gate structure 36 in the backside source-drain region to form a dummy gate structure 37 in the backside gate region. The height of the dummy gate structure 37 in the first direction is greater than the height of the fin structure in the first direction. As shown in the C-C' cross-sectional view in Figure 11 In an embodiment, a fin cutting process can be performed to remove a portion of the dummy gate structure 37, which is located at the edge portion in the third direction.

[0123] Twenty-second step, see Figure 24 As shown, an etching process is performed to remove the backside oxide layer 35 and the shallow trench isolation structure 27 in the backside source-drain region. Here, the shallow trench isolation structure 27 can be removed to expose the third portion 26.

[0124] Twenty-third step, see Figure 25 As shown, an isotropic etching process is performed to remove the third portion 26 between the first portion 24 and the second portion 25 in the backside source-drain region and the gate region. As shown in the A-A' cross-sectional view in Figure 25 The third portion 26 between the dummy gate structure and the first gate structure 114 is removed; the B-B' cross-sectional view shows that the third portion 26 above the first source-drain structure 112 is removed; and the C-C' cross-sectional view shows that the third portion 26 between the first portion 24 and the second portion 25 is removed.

[0125] Twenty-fourth step, see Figure 26As shown, an isotropic deposition process is used to deposit sidewall material to simultaneously form the second pseudo-gate sidewall 121 of the second pseudo-gate structure 37, the second sidewall 38 of the second portion 25, and the isolation layer 39 between the first portion 24 and the second portion 25. Here, the isolation layer 39 is used for electrical isolation between the first portion 24 and the second portion 25. The sidewall material can be an insulating material. The second pseudo-gate sidewall 121 covers the sidewall of the pseudo-gate structure 37. The second sidewall 38 covers the sidewall of the second portion 25.

[0126] Step 25, see Figure 27 As shown, insulating material is deposited and etched back in the reverse source / drain region to form a source / drain isolation structure 40 between the first transistor 11 and the second transistor 12. Here, the source / drain isolation structure 40 is used for electrical isolation between the first transistor 11 and the second transistor 12.

[0127] Step 26, see Figure 28 As shown, a portion of the second part 25 of the fin structure and the corresponding second sidewall 38 are removed by a fin structure deep etching process to form a second source drain groove 41.

[0128] Step 27, see Figure 29 As shown, when the second transistor 12 is an N-type field-effect transistor, a strain material such as silicon germanium or silicon carbide can be selectively epitaxially grown in the second source-drain groove 41 to fill the second source-drain groove 41, and then a second source-drain structure 122 is formed on the strain material by a heavy doping process.

[0129] Step 28, see Figure 30 As shown, after forming the second source-drain structure 122, an insulating material is deposited on the second source-drain structure 122 to form the second interlayer dielectric layer 123, and the second interlayer dielectric layer 123 is processed by a chemical mechanical planarization process to make the height of the second transistor 12 uniform.

[0130] Step 29, see Figure 31 As shown, the dummy gate structure 37 is removed by etching, and a second gate dielectric material is deposited at the location where the dummy gate structure 37 is removed to form a second gate dielectric layer 42; a second gate material is deposited on the second gate dielectric layer 42 to form a second gate electrode layer 43. The second gate dielectric layer 42 and the second gate electrode layer 43 together constitute the second gate structure 124. Here, the second gate dielectric layer 42 can cover the upper surface of the second portion 25, the upper surface of the shallow trench isolation structure 27, the sidewalls of the second portion 25, and the sidewalls of the second dummy gate sidewall 121. The second gate dielectric layer 42 can completely isolate the second gate electrode layer 43 from other structures.

[0131] Step 30, see Figure 32As shown, the gate cut-off process is adopted to remove the second gate structure 124, the first gate structure 114 and the structure between the second gate structure 124 and the first gate structure 114 on both sides of the stacked transistor in the second direction to form a gate isolation trench, and deposit an insulating material in the gate isolation trench to form a gate isolation structure 44.

[0132] Thirty-first, referring to Figure 33 As shown, the second interlayer dielectric layer 123 is etched to expose the second source-drain structure 122, and a metal material is deposited on the second source-drain structure 122 to form a second source-drain metal 125.

[0133] Thirty-second, referring to Figure 34 As shown, a standard back-end-of-line process of semiconductor preparation (such as interconnection line interlayer dielectric deposition, metal line formation, and lead pad formation) is adopted to form a second metal interconnection layer 126 on the second gate structure 124 and the second source-drain metal 125.

[0134] In the embodiment of the present application, the first transistor is a P-type field effect transistor, and the first transistor can use a silicon germanium channel to increase the carrier mobility in the P-type fin field effect transistor, reduce the threshold voltage, and improve the electrical performance of the P-type fin field effect transistor. At the same time, the first transistor has a high-temperature-resistant first gate structure 114, which helps to ensure that the first transistor is not damaged in the process of preparing the second transistor.

[0135] Figures 35 to 37 For the second preparation process of the stacked transistor shown in the embodiment of the present application, for the convenience of understanding, Figures 35 to 37 (a) in FIG. 4 shows a cross-sectional view along the direction of the dashed line A-A' in FIG. 4, Figure 2 (b) in FIG. 4 shows a cross-sectional view along the direction of the dashed line B-B' in FIG. 4, Figures 35 to 37 (b) in FIG. 4 shows a cross-sectional view along the direction of the dashed line B-B' in FIG. 4, Figure 2 (c) in FIG. 4 shows a cross-sectional view along the direction of the dashed line C-C' in FIG. 4. Figures 35 to 37 Figure 2 In the embodiment, it is assumed that the first transistor is an N-type field effect transistor and the second transistor is a P-type field effect transistor. The following will be described in combination with ,

[0136] A possible implementation of the stacked transistor provided in the embodiment will be described. Figures 1 to 2 Figures 35 to 37 First step, referring to

[0137] First step, referring to Figure 35 ​As shown, the third material layer 21 and the first material layer 22 are respectively formed on the semiconductor substrate 20 (formed of silicon material) by epitaxy. The first material layer 22 is formed of silicon material, and the third material layer 21 is formed of silicon germanium material. The first material layer 22 can be prepared to form a channel (NFET channel) of the first transistor 11, and the third material layer 21 can be prepared to form an isolation layer between the first transistor 11 and the second transistor 12. Meanwhile, a part of the semiconductor substrate 20 close to the third material layer 21 can be understood as the second material layer 23, and the second material layer 23 can be prepared to form a channel (PFET channel) of the second transistor 12.

[0138] The second step to the thirty-second step are described in detail in the first aspect. Figure 36 As shown, the same preparation process as the second step to the thirty-second step in the embodiment corresponding to the first transistor 11 being a P-type field effect transistor and the second transistor being an N-type field effect transistor is adopted to obtain the stacked transistor 10.

[0139] It should be noted that the first transistor is an N-type field effect transistor, and the second transistor is a P-type field effect transistor, and the channels of the first transistor and the second transistor are both prepared from silicon material. The covering layer 30 corresponding to the first transistor is an N-type field effect transistor covering layer 30, and here, the metal oxide material forming the N-type field effect transistor covering layer 30 can be lanthanum oxide. The covering layer 30 formed of lanthanum oxide can reduce the threshold voltage of the NFET.

[0140] The thirty-third step is described in detail in the first aspect. Figure 37 As shown, an insulating material is deposited on top of the first metal interconnection layer 116 to form an insulating layer 33, and the insulating layer 33 is bonded with a carrier wafer 34. The second transistor 12 after bonding is flipped to be located at the lower layer.

[0141] In the embodiment of the present application, the first transistor is an N-type field effect transistor, and the covering layer in the first transistor can be prepared from lanthanum oxide material, which can increase negative electric atoms, thereby effectively reducing the threshold voltage of the NFET. Meanwhile, the first transistor has a high-temperature-resistant first gate structure 114, which helps to ensure that the first transistor is not damaged in the process of preparing the second transistor. Finally, after the preparation of the second transistor is completed, the first transistor being an N-type field effect transistor is flipped to the upper layer of the stacked transistor, thereby helping to improve the performance of the stacked transistor.

[0142] In a second aspect, a stacked transistor is provided in the embodiment of the present application, which can be prepared by the method in one or more embodiments. Figures 1 to 34 The method is described in detail in the first aspect. Figure 34 As shown, the stacked transistor comprises:

[0143] The first transistor 11 and the second transistor 12 are arranged in a stack along a first direction, and a first active region of the first transistor 11 is self-aligned with a second active region of the second transistor 12. The first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure 124. The first gate structure 114 and the second gate structure 124 are arranged oppositely.

[0144] The first gate structure 114 is formed by a first gate preparation process, and the second gate structure 124 is formed by a second gate preparation process. The first gate preparation process and the second gate preparation process are different at least in a preparation step. The first gate structure 114 has a higher heat resistance than the second gate structure 124.

[0145] It can be understood that the preparation processes of the first transistor 11 and the second transistor 12 can refer to the descriptions in one or more of the above embodiments, and will not be described herein for the sake of brevity.

[0146] It can be understood that the first transistor 11 and the second transistor 12 are self-aligned. The self-alignment can mean that a first channel in the first transistor 11 and a second channel in the second transistor 12 are aligned vertically, a first source-drain structure 112 in the first transistor 11 and a second source-drain structure 122 in the second transistor 12 are aligned vertically, and a first gate structure 114 in the first transistor 11 and a second gate structure 124 in the second transistor 12 are aligned vertically. Here, the first channel, the first source-drain structure 112, and the first gate structure 114 are all formed based on the first part 24 of the fin structure.

[0147] In this embodiment, the first gate structure 114 and the second gate structure 124 are prepared by different preparation processes, so that the first gate structure 114 has a higher heat resistance than the second gate structure 124. In this way, the first gate structure 114 has a higher tolerance to a large number of high-temperature processes in subsequent processes, and the failure rate of the front device is reduced.

[0148] In some embodiments, when the first transistor 11 is a P-type field effect transistor, the first active region of the first transistor 11 is formed of a silicon germanium material. It can be understood that when the first transistor 11 is a P-type field effect transistor, the first part 24 of the fin structure can be formed of a silicon germanium material, so that the first active region of the first transistor 11 is formed of a silicon germanium material. For a P-type field effect transistor, a channel prepared and formed of a silicon germanium material can reduce the threshold voltage of the P-type field effect transistor, and further improve the electrical performance of the upper and lower transistors of the stacked transistors.

[0149] It can be understood that, in the embodiments of the present application, by using the first gate preparation process for the first transistor 11 and the second gate preparation process for the second transistor 12, a high-heat-budget-tolerant stacked transistor implementation scheme is realized.

[0150] In some embodiments, the stacked transistor can be detected by means of a transmission electron microscope (TEM) section, and a structure as shown in FIG. 6A can be obtained. Figure 34 As can be seen from FIG. 6A, the topography of the gate dielectric layer inside the gate structure in the front and back transistors (i.e., the first transistor 11 and the second transistor 12) is different: the first gate structure 114 in the first transistor 11 is prepared before the first source-drain structure 112, and the corresponding gate dielectric layer only exists at the bottom of the gate electrode layer material; the second gate structure 124 in the second transistor 12 is prepared after the second source-drain structure 122, and the corresponding gate dielectric layer wraps the sidewall and bottom of the gate electrode layer, thereby improving the overall performance and overall circuit energy efficiency of the stacked transistor. Figure 34 It should be noted that the stacked transistor has self-alignment, which on the one hand solves the long-standing problems of process complexity and alignment difficulty existing in the existing mainstream technical solutions of the stacked transistor, and realizes the industrialization of the transistor stacking technology. On the other hand, through the self-aligned "back-to-back" fin structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through the interconnection of the stacked transistor, greatly releasing the metal wiring resources.

[0151] Finally, the scheme of realizing the upper and lower transistors through flip-chip is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs), without the need for special process development for specific device architectures, and has strong flexibility and strong extendability from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicality and wide development prospects.

[0152] In a third aspect, the embodiments of the present application provide a semiconductor device, comprising: the stacked transistor according to the above-mentioned embodiments. The specific limitations of the stacked transistor can be referred to the structure shown in FIG. 6A, which will not be repeated here.

[0153] Figure 34 In a fourth aspect, the embodiments of the present application provide an electronic device, comprising: a circuit board and a semiconductor device according to the above-mentioned embodiments, the semiconductor device being arranged on the circuit board. The semiconductor device comprises the stacked transistor described above. The specific limitations of the stacked transistor can be referred to the structure shown in FIG. 6A, which will not be repeated here.

[0154] In a fourth aspect, the embodiments of the present application provide an electronic device, comprising: a circuit board and a semiconductor device according to the above-mentioned embodiments, the semiconductor device being arranged on the circuit board. The semiconductor device comprises the stacked transistor described above. The specific limitations of the stacked transistor can be referred to the structure shown in FIG. 6A, which will not be repeated here. Figure 34 ​​

[0155] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the application. In the present application, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, different embodiments or examples described in the present application and the features of different embodiments or examples can be combined by those skilled in the art without contradiction.

[0156] The above is only the preferred embodiment of the present application, and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating stacked transistors, characterized in that, The method includes: A fin-like structure is formed by etching on a semiconductor substrate in one step, wherein the fin-like structure includes a first portion and a second portion stacked along a first direction, the first portion being farther away from the semiconductor substrate than the second portion; Based on the first part, a first transistor is formed, wherein the first transistor includes: a first gate structure, the first gate structure being formed by a first gate fabrication process; The semiconductor substrate is then poured and removed. Based on the second part, a second transistor is formed stacked with the first transistor along a first direction, wherein the second transistor includes: a second gate structure, the second gate structure being formed by a second gate fabrication process; the second gate fabrication process and the first gate fabrication process differ in at least one fabrication step; the heat resistance of the first gate structure is greater than that of the second gate structure.

2. The preparation method according to claim 1, characterized in that, The formation of the first transistor based on the first portion includes: A first gate dielectric material is deposited in the gate region of the stacked transistor to form a first gate dielectric layer covering the first portion; A metal oxide material is deposited on the first gate dielectric layer to form a capping layer; A first gate material is deposited on the capping layer to form a first gate electrode layer, wherein the first gate dielectric layer, the capping layer, and the first gate electrode layer together constitute the first gate structure; the fabrication step of forming the first gate structure is included in the first gate fabrication process; Within the source-drain region of the stacked transistor, a first source-drain structure is formed based on the first portion, wherein the first source-drain structure and the first gate structure together constitute the first transistor.

3. The preparation method according to claim 2, characterized in that, When the first transistor is an N-type field-effect transistor, the metal oxide material is lanthanum oxide; When the first transistor is a P-type field-effect transistor, the metal oxide material is aluminum oxide.

4. The preparation method according to claim 2, characterized in that, The formation of the second transistor based on the second part includes: A dummy gate material is deposited in the gate region of the stacked transistors to form a dummy gate structure; A second source-drain structure is formed based on the second portion within the source-drain region of the stacked transistors; The dummy gate structure is removed, and a second gate dielectric material is deposited at the location where the dummy gate structure is removed to form a second gate dielectric layer; A second gate material is deposited on the second gate dielectric layer to form a second gate electrode layer; The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure; the fabrication step of forming the second gate structure is included in the second gate fabrication process; the second source / drain structure and the second gate structure together constitute the second transistor.

5. The preparation method according to claim 4, characterized in that, When the first transistor is an N-type field-effect transistor, after forming the second transistor based on the second part, the method further includes: The second transistor is bonded to the carrier wafer; The bonded second transistor is then flipped.

6. The preparation method according to claim 4, characterized in that, When the first transistor is a P-type field-effect transistor, the first portion is formed of silicon-germanium material.

7. The preparation method according to claim 4, characterized in that, The fin-like structure further includes a third portion located between the first portion and the second portion; After forming the pseudo-gate structure, the fabrication method further includes: The third portion is removed, and an insulating material is deposited at the location where the third portion is removed to form an insulating layer, wherein the insulating layer is used to electrically isolate the first portion and the second portion.

8. A stacked transistor, fabricated using the fabrication method according to any one of claims 1 to 7, characterized in that, include: First transistor; The second transistor is stacked along a first direction, and the first active region of the first transistor and the second active region of the second transistor are self-aligned; the first transistor includes a first gate structure, the second transistor includes a second gate structure, and the first gate structure and the second gate structure are disposed opposite to each other; the first active region is formed based on a first portion of the fin structure, and the second active region is formed based on a second portion of the fin structure. The first gate structure is formed by a first gate fabrication process; the second gate structure is formed by a second gate fabrication process; the second gate fabrication process and the first gate fabrication process differ in at least one fabrication step; the heat resistance of the first gate structure is greater than that of the second gate structure.

9. The stacked transistor according to claim 8, characterized in that, When the first transistor is a P-type field-effect transistor, the first active region of the first transistor is formed of silicon-germanium material.

10. A semiconductor device, characterized in that, include: The stacked transistor as described in claim 8 or 9.

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