Two-dimensional material multi-port reconfigurable device structure and preparation method thereof

Abstract

The invention relates to the technical field of nano electronic devices, in particular to a two-dimensional material multi-port reconfigurable device structure and a preparation method thereof. The static grid electrodes are used for regulating and controlling the conduction type of a nanometer two-dimensional material channel, the nanometer electrodes are directly connected with an active region, a plurality of nanometer electrodes are directly connected with a central two-dimensional material, and meanwhile side grid electrodes are not connected with the central two-dimensional material. By applying different gate voltages, the carrier type, density and transport mechanism of the central two-dimensional material can be regulated and controlled, and free switching among an n-type state, a p-type state or an undoped state is realized. The device structure provided by the invention is provided with a plurality of nano-sized side gate electrodes and an electrode connected with a channel, and by utilizing the electric tunability of a two-dimensional material, the advantages of relatively strong gate control capability, relatively high device integration degree, reconfigurable function and the like can be obtained.

Description

Technical Field

[0001] The present application relates to the technical field of nanoelectronic devices, and in particular to a two-dimensional material multi-port reconfigurable device structure and a preparation method thereof. Background Art

[0002] In the past few decades, in order to meet the growing demand for chip computing power, integrated circuit technology has continued to develop in accordance with Moore's Law. However, the way to improve chip computing power by miniaturizing the characteristic size of transistors to increase chip integration is becoming more and more challenging. Because the characteristic size of transistors is close to the physical limit, effects such as short channels and quantum tunneling lead to increased tunneling and leakage currents, affecting the performance of transistors. Therefore, in the post-Moore era, in order to continue to improve chip performance, it is necessary to introduce new materials, new device structures, and new computing architectures to break through the limitations of traditional technologies.

[0003] Recently, a technology that can achieve dynamic reconfiguration during device operation has been proposed. It is characterized by being able to realize multiple functions on a single device, which to some extent overcomes the problem of single function of traditional metal oxide semiconductor field effect transistors (MOSFETs), and is expected to realize more complex systems with fewer devices. By changing the electrical input of the reconfigurable device, the type of channel carriers can be flexibly switched to p-type or n-type in the same device to realize the behavior of unipolar p-type or unipolar n-type transistors. In contrast, the channel carrier type of transistors made by traditional CMOS technology has been fixed to unipolar p-type or n-type during the ion implantation process. In addition, reconfigurable devices can also realize specific circuit functions composed of multiple CMOS transistors. For example, traditional logic gate circuits usually require a combination of several CMOS transistors, while reconfigurable devices can flexibly realize multiple logic functions such as AND gates, OR gates, and NOT gates on a single device. In addition, more complex circuit functions, such as adders and subtractors, can also be completed by a single reconfigurable device. This integration of functions reduces the number of transistors while improving the flexibility and overall performance of the circuit.

[0004] Reconfigurable devices have been explored and realized in materials such as silicon nanowires, memristors, and carbon nanotubes. For reconfigurable silicon nanowire devices, the nanowire manufacturing process is complex and the functions are limited. Reconfigurable memristors are non-volatile two-terminal devices that can only be reconfigured through the input and output terminals, without a separate control terminal for reconfiguration, which limits the flexibility of function switching. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a two-dimensional material multi-port reconfigurable device structure and preparation method with stronger gate control capability in view of the problem that current reconfigurable devices have insufficient channel electric field control capability and limited functions.

[0006] In order to solve the above technical problems, the present invention provides a two-dimensional material multi-port reconfigurable device, the device structure has multiple electrostatic gates for regulating the conductivity type of the two-dimensional material channel and electrodes directly connected to the active area, wherein the top view of the device is as shown Figure 2 As shown, the channel electrode layer 3 is directly connected to the two-dimensional material layer 5, and the side gate electrode layer 4, as a side gate electrode, is not connected to the two-dimensional material layer 5, and is used to regulate the carrier type, density and transport mechanism of the two-dimensional material layer 5 to achieve free switching between n-type, p-type or undoped states.

[0007] In one embodiment, Figure 1 As shown in the cross-sectional view of the device, the device includes from bottom to top at least a substrate layer 1, an insulating layer 2, a channel electrode layer 3, a side gate electrode layer 4, and a two-dimensional material layer 5. The channel electrode layer 3 and the side gate electrode layer 4 are used to connect to a probe station or to achieve electrical connection through wire bonding.

[0008] Preferably, the substrate layer 1 material includes doped silicon, indium tin oxide, silicon carbide, and serves as a back gate electrode to control the channel as a whole. The insulating layer 2 material includes silicon oxide, aluminum oxide, boron nitride, silicon nitride, and mica.

[0009] In one embodiment, the channel electrode layer 3 and the side gate electrode layer 4 are made of several nanoelectrodes by electron beam lithography, the nanoelectrodes of the channel electrode layer 3 are directly connected to the channel of the two-dimensional material layer 5, and the nanoelectrodes of the side gate electrode layer 4 are used as side gate electrodes to regulate the channel of the two-dimensional material layer 5. The materials of the channel electrode layer 3 and the side gate electrode layer 4 include Ti, Cr, Au, and Pd.

[0010] Preferably, the shape of the two-dimensional material layer 5 includes nano-rings and nano-circles. The material of the two-dimensional material layer 5 includes graphene, transition metal sulfides, and transition metal selenides.

[0011] In one embodiment, any two electrodes connected to the active area in the device are selected as input electrodes, another different electrode is selected as the output electrode, and the other electrodes are selected as control electrodes to affect the output characteristics. By measuring the voltage-current data between the input-output electrode and the control-output electrode, and then setting the loss function according to the target function, the appropriate voltage parameters of the control electrode are found through gradient descent or evolutionary algorithm, and the found parameters are verified in the device to realize the logic operation function or arithmetic operation function. For example, multiple logic operation functions such as AND gates, OR gates, and NOT gates can be realized on a single device. In addition, more complex arithmetic operation functions, such as adders and subtractors, can also be completed by a single device.

[0012] In order to further solve the technical problem to be solved by the present invention, the present invention provides a method for preparing a two-dimensional material multi-port reconfigurable device, wherein the two-dimensional material multi-port reconfigurable device has the structure as described above, and the preparation method comprises: Step 1, making metal alignment marks and nano-electrodes on the substrate / insulating layer material; Step 2, based on the preparation of the nano-electrode, preparing a micron-scale electrode connected to the nano-electrode; Step 3, transferring or growing the two-dimensional material on the substrate on which the electrode has been fabricated; Step 4, patterning the two-dimensional material on the sample surface at the micrometer level; Step 5, performing nanoscale patterning of the two-dimensional material on the sample surface; Step 6: anneal the sample to remove surface contamination of the two-dimensional material and complete the fabrication of the two-dimensional material multi-port reconfigurable device.

[0013] Preferably, the two-dimensional material transfer method in step 3 includes: PMMA wet assisted transfer method, PDMS assisted transfer method, electrochemical bubbling transfer method or thermal release tape transfer method. The growth method of two-dimensional materials includes: molecular beam epitaxy deposition method, atomic layer deposition method, chemical vapor deposition method and metal organic chemical vapor deposition method.

[0014] In order to further solve the technical problem to be solved by the present invention, the present invention provides another method for preparing a two-dimensional material multi-port reconfigurable device, wherein the two-dimensional material multi-port reconfigurable device has the above structure, and the preparation method comprises: Step 1: Making metal alignment marks on a substrate having a two-dimensional material.

[0015] Step 2: Use metal alignment marks to overlay and produce micrometer-scale electrodes.

[0016] Step 3: Perform micron-scale patterning of the two-dimensional material on the sample surface.

[0017] Step 4: Perform nanoscale patterning of the two-dimensional material on the sample surface.

[0018] Step 5: Make nanoelectrodes to connect the two-dimensional material channel and the microelectrode.

[0019] Step 6: anneal the sample to remove surface contamination of the two-dimensional material and complete the fabrication of the two-dimensional material multi-port reconfigurable device.

[0020] The two-dimensional material channel is located below or above the metal electrode.

[0021] Through the two-dimensional material multi-port reconfigurable device structure and preparation method described above, the device structure proposed in the present invention has multiple nano-sized side gate electrodes and electrodes connected to the channel, which utilizes the electrical tunability of the two-dimensional material to obtain advantages such as strong gate control capability, high device integration, and reconfigurable function. The device structure proposed in the present invention has a wide range of application scenarios, is compatible with most two-dimensional material manufacturing processes, and can be used to construct two-dimensional material heterojunction devices. According to the characteristics of the channel material, the device can also be used as a reconfigurable sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features of the present invention will be further described below in conjunction with the accompanying drawings and detailed description thereof. It should be understood that these drawings only illustrate several exemplary embodiments according to the present invention and therefore should not be regarded as limiting the scope of protection of the present invention. Unless otherwise specified, the drawings are not necessarily to scale and similar reference numerals represent similar components.

[0023] Figure 1 This is a cross-sectional view of a two-dimensional material multi-port reconfigurable device according to the present invention; Figure 2 This is a top view of the two-dimensional material multi-port reconfigurable device of the present invention; Figure 3 A graphene multi-port reconfigurable device layout having multiple side gate electrodes and connected to a channel electrode in the present invention; Figure 4 The process flow chart of preparing multi-port reconfigurable devices made of two-dimensional materials by method one is shown; Figure 5 The process flow chart of preparing multi-port reconfigurable devices made of two-dimensional materials by method 2 is shown; Figure 6 A schematic diagram of the device of the present invention using a side gate electrode to control a pn junction of a two-dimensional material; In the accompanying drawings: 1—substrate layer; 2—insulating layer; 3—channel electrode layer; 4—side gate electrode layer; 5—two-dimensional material layer. DETAILED DESCRIPTION

[0024] The following detailed description refers to the drawings which form a part of this specification. The exemplary embodiments mentioned in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. It will be appreciated by those skilled in the art that many other embodiments may be adopted and that various changes may be made to the described embodiments without departing from the spirit and scope of protection of the present invention. It should be understood that the various aspects of the present invention described and illustrated herein may be arranged, replaced, combined, separated and designed in many different configurations, all of which are included in the present invention.

[0025] Embodiment 1: The technical scheme and purpose of the present invention will be further described below in conjunction with the accompanying drawings.

[0026] The reconfigurability of the device of the present invention is achieved by controlling the gate electrostatic doping of the bipolar two-dimensional material active region channel, and different functions can be achieved by applying different gate voltage combinations. Taking the realization of the most basic p-type or n-type transistor as an example, by applying a negative or positive voltage on the side gate, according to the working principle of the flat capacitor, the corresponding p-type carriers or n-type carriers will be induced in the bipolar two-dimensional material channel, and the p-type doping or n-type doping of the channel will be realized to form a p-type transistor or n-type transistor. Unlike traditional PMOS transistors or NMOS transistors, the doping is reversible and can be freely switched between n-type, p-type or undoped states; while the doping condition of the channel of traditional PMOS transistors (NMOS transistors) cannot be changed once it is determined by the ion implantation process.

[0027] Furthermore, to realize the pn junction function in the two-dimensional material multi-port device, we can select the separated side gates to apply opposite biases (negative polarity voltage and positive polarity voltage), and use the local control of the channel by the side gates to cause p-type and n-type doping in the adjacent channel regions to form a pn junction, such as Figure 6 As shown. When source-drain voltages of different polarities are applied, the conductivity of the pn-type (or np-type) channel will exhibit opposite behaviors. In particular, the positions of the p-type region and the n-type region of the conventional pn junction diode are fixed, while the device of the present invention can be switched between pn-type and np-type diodes by changing the polarity of the side gate voltage.

[0028] Furthermore, the device of the present invention can also be combined with a neural network to realize basic Boolean logic gate functions and more complex classification tasks. To realize basic Boolean logic gate functions, such as AND, NOT, OR and other Boolean logic functions, any two electrodes connected to the active area in the device can be selected as input electrodes, another different electrode can be used as an output electrode, and other electrodes can be used as control electrodes to affect the output characteristics. By measuring the voltage-current data between the input-output electrode and the control-output electrode, a neural network is used to model it, and then a loss function is set according to the target function, and the appropriate voltage parameters of the control electrode are found through gradient descent or evolutionary algorithms. Finally, the parameters found are verified in the device to realize the logic operation function. Therefore, according to the functions that the device needs to realize, on the basis of defining the input, output, and control electrodes, sufficient data is collected and modeled using DNN to realize more complex arithmetic operations, such as adders, subtractors, etc.

[0029] Embodiment 2: This embodiment illustrates a multi-port reconfigurable device made of graphene material and a process flow for making the same.

[0030] The device layout of this embodiment is as follows Figure 3 As shown. The central ring represents the annular graphene channel. The eight nanoelectrodes are used as side gate electrodes and do not contact the graphene channel to control the channel doping. The eight nanoelectrodes are connected to the graphene channel to achieve multi-port input and output. Furthermore, the front line width of the nanoelectrode is 20 nm, the nano side gate electrode is 50 nm away from the edge of the graphene channel, and the nanoelectrode connected to the channel overlaps the graphene channel by 50 nm. The graphene layer is patterned by electron beam lithography into a nano ring with a diameter of 580 nm and a ring width of 70 nm.

[0031] The device consists of highly doped substrate silicon (p-type or n-type), silicon dioxide layer (300 nm thick), metal electrode layer, and graphene layer from bottom to top.

[0032] Figure 4 This is a schematic diagram of the process flow of manufacturing the embodiment device using method one, showing the process flow of manufacturing the graphene multi-port reconfigurable device.

[0033] The preparation process of the graphene multi-port reconfigurable device in this embodiment includes the following steps: (1) First, the nano-electrodes and alignment mark layers are patterned on the silicon / silicon oxide substrate by electron beam lithography. In order to obtain a smaller line width and good electrode morphology, we need to use PMMA electron beam photoresist with a thickness of less than 100 nm and high-voltage, high-resolution electron beam exposure equipment. Then, metal Ti (10 nm) / Au (40 nm) is evaporated using electron beam evaporation or thermal evaporation equipment and peeled off to make nano-electrodes and alignment marks.

[0034] (2) After the nano-electrode is fabricated, a laser direct writing device is used to overlay and fabricate a micro-electrode layer connected to the nano-electrode to achieve electrical connection. In this step, a magnetron sputtering device is used to deposit metal Ti (10 nm) / Au (60 nm), and then peeled off to complete the fabrication of the micro-electrode. (3) After the electrode is fabricated, the graphene is transferred to the silicon / silicon oxide substrate on which the electrode has been fabricated using the PMMA wet-assisted graphene transfer method. The specific transfer steps are further described below: a) The copper substrate with single-layer graphene was cut into 1 cm*1 cm squares, and then electron beam photoresist PMMA A4 was spin-coated on the sample surface to support the graphene during the transfer process.

[0035] b) After the electron beam photoresist on the sample surface is naturally dried, the side that is not spin-coated with the electron beam photoresist is turned upward, and reactive ion etching (RIE) is used to remove the graphene on this side to avoid affecting the transfer quality.

[0036] c) Transfer the sandwich structure of copper foil / graphene / electron beam photoresist obtained in the previous step into a copper etching solution with the side coated with photoresist facing up, so that the sample floats on the surface of the solution. Preferably, a copper etching solution of ammonium persulfate (APS) with a mass fraction of 10% is used.

[0037] d) After the copper foil under the graphene is completely etched, the graphene / electron beam photoresist film is transferred to clean water using a glass slide and washed three times to remove the copper etching solution.

[0038] e) Finally, the graphene / electron beam photoresist is transferred to the surface of the substrate with the metal electrode. After standing to dry and baking, the sample is placed in an acetone solution to remove the electron beam photoresist PMMA, thus completing the transfer of the graphene.

[0039] (4) After the graphene transfer is completed, the graphene area is patterned at the micrometer scale using laser direct writing, and then the exposed graphene is removed using reactive ion etching (RIE) equipment.

[0040] (5) Finally, the graphene nanochannels are patterned using electron beam lithography equipment, and the preparation of the graphene multi-port reconfigurable device is completed after etching, degumming, and annealing.

[0041] Embodiment 3: The difference between this embodiment and the second embodiment is that the channel material is replaced with molybdenum disulfide to manufacture the multi-port reconfigurable device and the device is manufactured by the process of method 2.

[0042] The device layout is consistent with that of Example 2, and the preparation process is mainly described below.

[0043] The device consists of highly doped substrate silicon (p-type or n-type), silicon dioxide layer (300 nm thick), molybdenum disulfide layer, and metal electrode layer from bottom to top.

[0044] The process flow of device manufacturing in this embodiment is as follows: Figure 5 As shown, a schematic diagram of the process flow of manufacturing a molybdenum disulfide multi-port reconfigurable device using method two is shown.

[0045] The preparation process of the molybdenum disulfide multi-port reconfigurable device in this embodiment includes the following steps: (1) First, an alignment mark layer is patterned on a silicon / silicon oxide / molybdenum disulfide substrate by electron beam lithography. Using electron beam lithography to make alignment marks is conducive to achieving a smaller overlay error. Then, metal Ti (10 nm) / Au (60 nm) is evaporated using electron beam evaporation or thermal evaporation equipment and peeled off to make alignment marks. The thickness of the alignment mark is required to be more than 70 nm.

[0046] (2) Use laser direct writing equipment to overlay and make a micron electrode layer connected to the nanoelectrode to achieve electrical connection of the device. This step uses electron beam evaporation, thermal evaporation or magnetron sputtering equipment to deposit metal Ti (10 nm) / Au (60 nm), and then peel it off. (3) Use a laser direct writing device to perform micrometer-scale patterning on MoS2. After photolithography and development, use a reactive ion etching device (RIE) to etch away excess MoS2.

[0047] (4) Electron beam lithography equipment is used to perform nanoscale patterning of MoS2. After photolithography and development, reactive ion etching equipment is used to remove the exposed MoS2.

[0048] (5) Finally, electron beam lithography equipment is used to make nanoelectrodes connecting the MoS2 channel and the micro-electrode. In order to reduce the defects of MoS2 during the coating process, electron beam evaporation or thermal evaporation coating equipment is used in this step to evaporate Ti (10 nm) / Au (60 nm) at a low rate of about 0.2 Å / s. After peeling and annealing, the preparation of the MoS2 multi-port reconfigurable device is completed.

[0049] Embodiment 4: The present embodiment is different from the above embodiment in that the channel material can be replaced with other bipolar two-dimensional materials, such as black phosphorus (BP), molybdenum ditelluride (MOTe2), WS2, etc., and the material transfer or growth method includes: PMMA wet assisted transfer method, PDMS assisted transfer method, thermal release tape transfer method, roll-to-roll transfer method and electrochemical bubbling transfer method; the growth method includes: molecular beam epitaxy (MBE), atomic layer deposition (PLD), liquid phase epitaxy (LPE), physical vapor substrate method (PVD), chemical vapor deposition (CVD) and metal organic chemical vapor deposition (MOCVD) and other methods. In addition, the present invention can also be integrated with CMOS circuits in a complementary manner, using the multifunctionality and reconfigurability of the device to serve as a multifunctional module in future CMOS integrated circuits, thereby improving the area efficiency, response speed and computing performance of integrated circuits.

[0050] In the description of the present invention, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0052] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0054] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0055] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A two-dimensional material multi-port reconfigurable device, characterized in that: The device has several nanoelectrodes, some of which are directly connected to the two-dimensional material channel, while other nanoelectrodes are not connected to the two-dimensional material and serve as side gate electrodes to regulate the two-dimensional material channel. By applying different gate voltages, the carrier type and density of the central two-dimensional material can be controlled to achieve free switching between n-type, p-type or undoped states.

2. The device according to claim 1, characterized in that The device includes a substrate layer, an insulating layer, a metal electrode layer, and a two-dimensional material layer from bottom to top. The metal electrode layer is used to connect a probe station or to achieve electrical connection through wire bonding.

3. The device according to claim 2, characterized in that The substrate layer materials include doped silicon, indium tin oxide, and silicon carbide, which serve as back gate electrodes to regulate the overall channel. The insulating layer materials include silicon oxide, aluminum oxide, boron nitride, silicon nitride, and mica.

4. The device according to claim 2, characterized in that The metal electrode layer uses electron beam lithography to produce several nanoelectrodes, some of which are directly connected to the two-dimensional material channel, and the other nanoelectrodes serve as side gate electrodes to regulate the two-dimensional material channel.

5. The device according to claim 4, characterized in that The metal electrode layer materials include Ti, Cr, Au, and Pd.

6. The device according to claim 1, characterized in that The shapes of the two-dimensional material layers include nanorings and nanocircles, and the two-dimensional materials include graphene, transition metal sulfides, and transition metal selenides.

7. A method for regulating a two-dimensional material multi-port reconfigurable device, characterized in that: The two-dimensional material multi-port reconfigurable device is the device according to claim 1, and the control method comprises: Any two electrodes connected to the active area in the device are selected as input electrodes, another different electrode is selected as the output electrode, and the other electrodes are selected as control electrodes to affect the output characteristics. By measuring the voltage-current data between the input-output electrodes and the control-output electrodes, and then setting the loss function according to the target function, the appropriate voltage parameters of the control electrode are found through gradient descent or evolutionary algorithm, and the found parameters are verified in the device to realize logical operation function or arithmetic operation function.

8. A method for preparing a two-dimensional material multi-port reconfigurable device, characterized in that: The two-dimensional material multi-port reconfigurable device is the device according to claim 1, and the preparation method comprises: Step 1, making metal alignment marks and nano-electrodes on the substrate / insulating layer material; Step 2, based on the preparation of the nano-electrode, preparing a micron-scale electrode connected to the nano-electrode; Step 3, transferring or growing the two-dimensional material on the substrate on which the electrode has been fabricated; Step 4, patterning the two-dimensional material on the sample surface at the micrometer level; Step 5, performing nanoscale patterning of the two-dimensional material on the sample surface; Step 6: anneal the sample to remove surface contamination of the two-dimensional material and complete the fabrication of the two-dimensional material multi-port reconfigurable device.

9. The method for preparing a two-dimensional material multi-port reconfigurable device according to claim 8, characterized in that: Two-dimensional material transfer includes: PMMA wet-assisted transfer method, PDMS-assisted transfer method, electrochemical bubbling transfer method or thermal release tape transfer method; two-dimensional material growth includes: molecular beam epitaxial deposition method, atomic layer deposition method, chemical vapor deposition method and metal organic chemical vapor deposition method.

10. A method for preparing a two-dimensional material multi-port reconfigurable device, characterized in that: The two-dimensional material multi-port reconfigurable device is the device according to claim 1, and the preparation method comprises: Step 1, making a metal alignment mark on a substrate having a two-dimensional material; Step 2, using metal alignment marks to overlay and produce micrometer-scale electrodes; Step 3, patterning the two-dimensional material on the sample surface at the micrometer level; Step 4, performing nanoscale patterning of the two-dimensional material on the sample surface; Step 5, making nano-electrodes to connect the two-dimensional material channel and the micro-electrode; Step 6, annealing the sample to remove surface contamination of the two-dimensional material, and completing the fabrication of the two-dimensional material multi-port reconfigurable device; The two-dimensional material channel is located below or above the metal electrode.

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