Semiconductor device and mounting substrate

Abstract

A flip chip size packaged semiconductor device (1) is provided with: a semiconductor layer (40); a vertical MOS transistor (10) formed in the semiconductor layer (40); a protective film (35); a first wiring electrode (12) connected to a source electrode (13) of the vertical MOS transistor (10); and a second wiring electrode (52) connected to a gate electrode (19) of the vertical MOS transistor (10), a first outer peripheral structure (101) protruding upward of the semiconductor device (1) is formed by sequentially stacking the source electrode (13), the protective film (35), and the first wiring electrode (12) at an outer peripheral portion of the first wiring electrode (12) in a plan view of the semiconductor layer (40), and a second outer peripheral structure (102) protruding upward of the semiconductor device (1) is formed by sequentially stacking the gate electrode (19), the protective film (35), and the second wiring electrode (52) at an outer peripheral portion of the second wiring electrode (52) in the plan view of the semiconductor layer (40).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a mounting substrate on which the semiconductor device is mounted. BACKGROUND

[0002] Conventionally, a semiconductor device is known (for example, refer to Patent Document 1).

[0003] PRIOR ART DOCUMENT

[0004] PATENT DOCUMENT

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-169579 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In recent years, in order to achieve space saving of a mounting substrate on which a semiconductor device is mounted, a mounting method in which the semiconductor device is buried inside the mounting substrate has been proposed.

[0008] Therefore, an object of the present application is to provide a semiconductor device and the like having a configuration suitable for a mounting method in which the semiconductor device is mounted by being buried in a mounting substrate.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] A semiconductor device of one embodiment of the present application is a chip-size packaged semiconductor device including a semiconductor layer; a vertical MOS transistor formed in the semiconductor layer; a protective film which is a protective film covering an upper surface of the vertical MOS transistor, has a first opening portion in which a source electrode of the vertical MOS transistor is exposed to an outside of the protective film, and a second opening portion in which a gate electrode of the vertical MOS transistor is exposed to the outside of the protective film; a first wiring electrode connected to the source electrode, which is mainly made of copper and covers the exposed portion of the source electrode to the outside of the protective film in the first opening portion without a gap; and a second wiring electrode connected to the gate electrode, which is mainly made of copper and covers the exposed portion of the gate electrode to the outside of the protective film in the second opening portion without a gap. In a plan view of the semiconductor layer, the semiconductor device has a rectangular shape, an entire length of an outer periphery of the first opening portion is enclosed by the protective film, an entire length of an outer periphery of the second opening portion is enclosed by the protective film, a first outer periphery structure in which the source electrode, the protective film, and the first wiring electrode are stacked in this order is formed in a portion of an outer periphery of the first wiring electrode in the plan view of the semiconductor layer, an uppermost layer of the first outer periphery structure is the first wiring electrode, a second outer periphery structure in which the gate electrode, the protective film, and the second wiring electrode are stacked in this order is formed in a portion of an outer periphery of the second wiring electrode in the plan view of the semiconductor layer, an uppermost layer of the second outer periphery structure is the second wiring electrode, a first wiring electrode exposed portion which is an upper surface of the first wiring electrode is exposed to the outside of the semiconductor device, a second wiring electrode exposed portion which is an upper surface of the second wiring electrode is exposed to the outside of the semiconductor device, the first outer periphery structure protrudes upward from an upper surface of a portion of the first wiring electrode exposed portion which is not included in the first outer periphery structure, the second outer periphery structure protrudes upward from an upper surface of a portion of the second wiring electrode exposed portion which is not included in the second outer periphery structure, an uppermost position of the semiconductor device is present in the first outer periphery structure or / and the second outer periphery structure, an area of the first wiring electrode exposed portion is larger than an area of the first opening portion in the plan view of the semiconductor layer, an area of the second wiring electrode exposed portion is larger than an area of the second opening portion in the plan view of the semiconductor layer, the semiconductor device further includes a metal layer formed in contact with a lower surface of the semiconductor layer, a thickness of the metal layer is larger than a maximum thickness of the first wiring electrode, and the first wiring electrode has a wall surface which is a reverse tapered shape toward an outer side of the first wiring electrode in a cross-sectional view of the semiconductor layer in a portion of an outer periphery of the semiconductor layer, and the wall surface is not in contact with the protective film.

[0011] A semiconductor device of one embodiment of the present application is a chip-size packaged semiconductor device including a semiconductor layer; a vertical MOS transistor formed in the semiconductor layer; a protective film which is a protective film covering an upper surface of the vertical MOS transistor, has a first opening portion in which a source electrode of the vertical MOS transistor is exposed to an outside of the protective film, and a second opening portion in which a gate electrode of the vertical MOS transistor is exposed to the outside of the protective film; a first wiring electrode connected to the source electrode, which is mainly made of copper and covers the exposed portion of the source electrode to the outside of the protective film in the first opening portion without a gap; and a second wiring electrode connected to the gate electrode, which is mainly made of copper and covers the exposed portion of the gate electrode to the outside of the protective film in the second opening portion without a gap. In a plan view of the semiconductor layer, the semiconductor device has a rectangular shape, a total length of an outer periphery of the first opening portion is enclosed by the protective film, a total length of an outer periphery of the second opening portion is enclosed by the protective film, the protective film has a multilayer structure including a plurality of protective film layers including a first protective film layer and a second protective film layer positioned above the first protective film layer, in a peripheral portion of the first wiring electrode in the plan view of the semiconductor layer, a first peripheral structure in which the source electrode, the first protective film layer, the first wiring electrode, and the second protective film layer are sequentially stacked is formed, an uppermost layer of the first peripheral structure is the second protective film layer, in a peripheral portion of the second wiring electrode in the plan view of the semiconductor layer, a second peripheral structure in which the gate electrode, the first protective film layer, the second wiring electrode, and the second protective film layer are sequentially stacked is formed, an uppermost layer of the second peripheral structure is the second protective film layer, a first wiring electrode exposed portion which is a portion of an upper surface of the first wiring electrode not included in the first peripheral structure is exposed to the outside of the semiconductor device, a second wiring electrode exposed portion which is a portion of an upper surface of the second wiring electrode not included in the second peripheral structure is exposed to the outside of the semiconductor device, the first peripheral structure protrudes upward from an upper surface of the first wiring electrode exposed portion, the second peripheral structure protrudes upward from an upper surface of the second wiring electrode exposed portion, an uppermost position of the semiconductor device is in the first peripheral structure or / and the second peripheral structure, if a thickness of the first wiring electrode in the first peripheral structure is a first thickness and a thickness of the second protective film layer in the first peripheral structure is a second thickness, the second thickness is equal to or smaller than the first thickness, and in a peripheral portion in the plan view of the semiconductor layer, the first wiring electrode has a wall surface which is an inverted tapered shape toward an outer side of the first wiring electrode in a cross-sectional view of the semiconductor layer.

[0012] The mounting substrate of one embodiment of the present application is a mounting substrate in which a first wiring layer, an interlayer insulating layer, and a second wiring layer are sequentially stacked, and includes the semiconductor device described above mounted in a face-up manner in the interlayer insulating layer, a first wiring formed in the second wiring layer, and one or more first connection wirings connecting the first wiring and the upper surface of the first wiring electrode and extending in a direction orthogonal to the mounting substrate, the one or more first connection wirings being connected to the upper surface of the first wiring electrode at a portion of the upper surface of the first wiring electrode which does not overlap with the first outer peripheral structure in a plan view of the semiconductor layer.

[0013] Effects of Invention

[0014] The semiconductor device and the like according to one embodiment of the present application provide a semiconductor device and the like having a structure suitable for mounting by a mounting method in which the semiconductor device is buried in a mounting substrate. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 FIG. 1 is a plan view of one example of a structure of a semiconductor device according to Embodiment 1.

[0016] Figure 2 FIG. 2 is a cross-sectional view of one example of a structure of the semiconductor device according to Embodiment 1.

[0017] Figure 3 FIG. 3 is a cross-sectional view of one example of a structure of the semiconductor device according to Embodiment 1.

[0018] Figure 4 FIG. 4 is a photograph of a portion of the upper surface of the semiconductor device according to Embodiment 1 taken from an oblique upper side.

[0019] Figure 5 FIG. 5 is an enlarged cross-sectional view of a structure of the first outer peripheral structure according to Embodiment 1.

[0020] Figure 6 FIG. 6 is a graph showing the relationship between the resistance of the semiconductor device according to Embodiment 1 and the shape and Si thickness of the semiconductor device according to Embodiment 1.

[0021] Figure 7 FIG. 7 is a cross-sectional view of the semiconductor device according to Embodiment 1 and the first outer peripheral structure schematically showing one example of a case where the semiconductor device according to Embodiment 1 is deformed due to a heat treatment step.

[0022] Figure 8 FIG. 8 is a plan view of one example of a structure of the semiconductor device according to Embodiment 1.

[0023] Figure 9 FIG. 9 is a cross-sectional view of one example of a structure of the semiconductor device according to Embodiment 1.

[0024] Figure 10 is a plan view showing one example of the configuration of the semiconductor device of Embodiment 1.

[0025] Figure 11 is a cross-sectional view showing one example of the configuration of the semiconductor device of Embodiment 1.

[0026] Figure 12 is a plan view showing one example of the configuration of the semiconductor device of Embodiment 1.

[0027] Figure 13 is a plan view showing one example of the configuration of the semiconductor device of Embodiment 2.

[0028] Figure 14 is a cross-sectional view showing one example of the configuration of the semiconductor device of Embodiment 2.

[0029] Figure 15 is an enlarged cross-sectional view showing the configuration of the first outer peripheral configuration of Embodiment 2.

[0030] Figure 16 is a plan view showing one example of the configuration of the mounting substrate of Embodiment 3.

[0031] Figure 17 is a cross-sectional view showing one example of the configuration of the mounting substrate of Embodiment 3.

[0032] Figure 18 is an enlarged plan view showing one example of the configuration of the mounting substrate of Embodiment 3. DETAILED DESCRIPTION

[0033] (Process of obtaining one embodiment of the present application)

[0034] The inventors have developed a semiconductor device including a vertical MOS transistor.

[0035] On the other hand, in recent years, space saving of a mounting substrate on which a semiconductor device is mounted has been required.

[0036] In response to this requirement, the inventors have considered that if a semiconductor device can be mounted by being buried in the inside of a mounting substrate, space saving of the mounting substrate can be achieved.

[0037] Accordingly, the inventors have developed a semiconductor device including a vertical MOS transistor that is resin-sealed in a mounting substrate and mounted in an upward-facing manner, based on this idea.

[0038] The inventors have found, through this development, that there is a semiconductor device having a structure suitable for a mounting method in which the semiconductor device is mounted in a mounting substrate.

[0039] That is, the inventors have arrived at the insight that by providing a protrusion on the upper surface of the semiconductor device that protrudes into the resin that encloses the semiconductor device, the protrusion functions as an anchor that fixes the position of the semiconductor device within the resin, as a result of which it is possible to achieve suppression of resin peeling in the mounting board and stabilization of the position of the semiconductor device inside the mounting board.

[0040] Further, the inventors have found that in the case where a protrusion is present on the upper surface of the semiconductor device, the upper surface of the resin that is cured after enclosing the semiconductor device also forms a protrusion that reflects the protrusion on the upper surface of the semiconductor device. Also, the inventors have arrived at the insight that by using the protrusion formed on the upper surface of the resin as a guide line when machining the mounting board, it is possible to machine the mounting board with higher precision compared to the case where the protrusion is not present.

[0041] Accordingly, the inventors and others have further repeated experiments and research based on these insights, as a result of which the inventors and others have conceived of the semiconductor device and the like of the present invention described below.

[0042] A semiconductor device of one embodiment of the present application is a flip chip scale package type semiconductor device which can be mounted face up, and includes a semiconductor layer, a vertical MOS (Metal Oxide Semiconductor) transistor formed in the semiconductor layer, a protective film which covers an upper surface of the vertical MOS transistor and has a first opening portion through which a source electrode of the vertical MOS transistor is exposed to the outside of the protective film and a second opening portion through which a gate electrode of the vertical MOS transistor is exposed to the outside of the protective film, a first wiring electrode connected to the source electrode, which is mainly composed of copper and covers the exposed portion of the source electrode to the outside of the protective film in the first opening portion without a gap, a second wiring electrode connected to the gate electrode, which is mainly composed of copper and covers the exposed portion of the gate electrode to the outside of the protective film in the second opening portion without a gap, wherein the semiconductor device is rectangular in a plan view of the semiconductor layer, a first outer peripheral structure in which the source electrode, the protective film, and the first wiring electrode are stacked in this order is formed at an outer peripheral portion of the semiconductor layer in the plan view of the semiconductor layer, the uppermost layer of the first outer peripheral structure is the first wiring electrode, a second outer peripheral structure in which the gate electrode, the protective film, and the second wiring electrode are stacked in this order is formed at an outer peripheral portion of the semiconductor layer in the plan view of the semiconductor layer, the uppermost layer of the second outer peripheral structure is the second wiring electrode, a first wiring electrode exposed portion which is an upper surface of the first wiring electrode is exposed to the outside of the semiconductor device, a second wiring electrode exposed portion which is an upper surface of the second wiring electrode is exposed to the outside of the semiconductor device, the first outer peripheral structure protrudes upward from an upper surface of a portion of the first wiring electrode exposed portion which is not included in the first outer peripheral structure, the second outer peripheral structure protrudes upward from an upper surface of a portion of the second wiring electrode exposed portion which is not included in the second outer peripheral structure, an uppermost position of the semiconductor device is present in the first outer peripheral structure or / and the second outer peripheral structure, an area of the first wiring electrode exposed portion is larger than an area of the first opening portion in the plan view of the semiconductor layer, an area of the second wiring electrode exposed portion is larger than an area of the second opening portion in the plan view of the semiconductor layer, an area of the semiconductor layer in the plan view of the semiconductor layer is denoted as S [mm 2 ], and a thickness from a lower surface of the semiconductor layer to an upper surface of the protective film is denoted as h [mm], the following relation is satisfied: h / S > 0.025.

[0043] According to the semiconductor device of the above structure, in the case where the semiconductor device is resin-sealed in a mounting substrate and mounted in a face-up manner, the first outer peripheral structure and the second outer peripheral structure are recessed in the resin on the upper surface of the semiconductor device.

[0044] Therefore, the first outer peripheral structure and the second outer peripheral structure recessed in the resin function as an anchor for fixing the position of the semiconductor device in the resin, and as a result, resin peeling in the mounting substrate is suppressed, and the position of the semiconductor device inside the mounting substrate is stabilized.

[0045] Further, on the upper surface of the resin cured after the semiconductor device is enclosed, a protrusion reflecting the first outer peripheral structure and the second outer peripheral structure is formed.

[0046] Therefore, in the case where the resin is processed to form a hole reaching the first wiring electrode exposure portion from the upper surface of the resin, by using the protrusion corresponding to the first outer peripheral structure formed on the upper surface of the resin as a guide line, the hole is processed inside the protrusion, and as compared with the case where the protrusion is not present, the hole reaching the first wiring electrode exposure portion from the upper surface of the resin can be processed with higher precision.

[0047] Further, similarly, in the case where the resin is processed to form a hole reaching the second wiring electrode exposure portion from the upper surface of the resin, by using the protrusion corresponding to the second outer peripheral structure formed on the upper surface of the resin as a guide line, the hole is processed inside the protrusion, and as compared with the case where the protrusion is not present, the hole reaching the second wiring electrode exposure portion from the upper surface of the resin can be processed with higher precision.

[0048] Thus, according to the semiconductor device of the above structure, a semiconductor device having a structure suitable for a mounting method of being buried and mounted in a mounting substrate is provided.

[0049] Further, it can also be that a metal layer formed in contact with the lower surface of the semiconductor layer is further provided, the thickness of the metal layer is thicker than the maximum thickness of the first wiring electrode, the outer peripheral portion of the first wiring electrode in the plan view of the semiconductor layer has a wall surface becoming an inverted conical shape toward the outside of the first wiring electrode in the sectional view of the semiconductor layer, and the wall surface is not in contact with the protective film.

[0050] Further, it can also be that the portion of the protective film around the first opening portion in the plan view of the semiconductor layer has a conical shape region becoming a conical shape toward the first opening portion in the sectional view, and the wall surface is located inside the conical shape region in the plan view of the semiconductor layer.

[0051] A semiconductor device of one embodiment of the present application is a flip chip scale package type semiconductor device which can be mounted face up, and includes a semiconductor layer, a vertical MOS (Metal Oxide Semiconductor) transistor formed in the semiconductor layer, a protective film which covers an upper surface of the vertical MOS transistor and has a first opening portion through which a source electrode of the vertical MOS transistor is exposed to the outside of the protective film and a second opening portion through which a gate electrode of the vertical MOS transistor is exposed to the outside of the protective film, a first wiring electrode connected to the source electrode and made of copper and covering the exposed portion of the source electrode to the outside of the protective film in the first opening portion without a gap, and a second wiring electrode connected to the gate electrode and made of copper and covering the exposed portion of the gate electrode to the outside of the protective film in the second opening portion without a gap. In a plan view of the semiconductor layer, the semiconductor device has a rectangular shape, the protective film has a multilayer structure including a plurality of protective film layers including a first protective film layer and a second protective film layer positioned above the first protective film layer, in a peripheral portion of the first wiring electrode in the plan view of the semiconductor layer, a first peripheral structure in which the source electrode, the first protective film layer, the first wiring electrode, and the second protective film layer are stacked in this order is formed, the uppermost layer of the first peripheral structure is the second protective film layer, in a peripheral portion of the second wiring electrode in the plan view of the semiconductor layer, a second peripheral structure in which the gate electrode, the first protective film layer, the second wiring electrode, and the second protective film layer are stacked in this order is formed, the uppermost layer of the second peripheral structure is the second protective film layer, a first wiring electrode exposed portion which is a portion of the upper surface of the first wiring electrode and is not included in the first peripheral structure is exposed to the outside of the semiconductor device, a second wiring electrode exposed portion which is a portion of the upper surface of the second wiring electrode and is not included in the second peripheral structure is exposed to the outside of the semiconductor device, the first peripheral structure protrudes upward from the upper surface of the first wiring electrode exposed portion, the second peripheral structure protrudes upward from the upper surface of the second wiring electrode exposed portion, the uppermost position of the semiconductor device is in the first peripheral structure or / and the second peripheral structure, if a thickness of the first wiring electrode in the first peripheral structure is a first thickness and a thickness of the second protective film layer in the first peripheral structure is a second thickness, the second thickness is greater than half the first thickness and is equal to or smaller than the first thickness, in the plan view of the semiconductor layer, an area of the first wiring electrode exposed portion is greater than an area of the first opening portion, and in the plan view of the semiconductor layer, an area of the second wiring electrode exposed portion is greater than an area of the second opening portion.

[0052] According to the semiconductor device described above, in a case where the semiconductor device is resin-sealed in a mounting substrate and mounted in a face-up manner, the first outer peripheral structure and the second outer peripheral structure are recessed in the resin on the upper surface of the semiconductor device.

[0053] Therefore, the first outer peripheral structure and the second outer peripheral structure recessed in the resin function as an anchor for fixing the position of the semiconductor device in the resin, and as a result, resin peeling in the mounting substrate is suppressed, and the position of the semiconductor device inside the mounting substrate is stabilized.

[0054] In addition, on the upper surface of the resin cured after the semiconductor device is enclosed, protrusions reflecting the first outer peripheral structure and the second outer peripheral structure are formed.

[0055] Therefore, in a case where the resin is processed to form a hole reaching the first wiring electrode exposure portion from the upper surface of the resin, by using the protrusion corresponding to the first outer peripheral structure formed on the upper surface of the resin as a guide line, the hole is processed inside the protrusion, and as compared with a case where the protrusion is not present, the hole reaching the first wiring electrode exposure portion from the upper surface of the resin can be processed with higher precision.

[0056] Further, similarly, in a case where the resin is processed to form a hole reaching the second wiring electrode exposure portion from the upper surface of the resin, by using the protrusion corresponding to the second outer peripheral structure formed on the upper surface of the resin as a guide line, the hole is processed inside the protrusion, and as compared with a case where the protrusion is not present, the hole reaching the second wiring electrode exposure portion from the upper surface of the resin can be processed with higher precision.

[0057] Thus, according to the semiconductor device described above, a semiconductor device having a configuration suitable for a mounting method in which the semiconductor device is mounted by being buried in a mounting substrate is provided.

[0058] In addition, it can also be that a minimum width of a portion of the second protective film layer that overlaps the first wiring electrode in a plan view of the semiconductor layer is greater than a thickness of a portion of the second protective film layer that does not overlap the first wiring electrode or the second wiring electrode in the plan view of the semiconductor layer, and a minimum width of a portion of the second protective film layer that overlaps the second wiring electrode in the plan view of the semiconductor layer is greater than a thickness of a portion of the second protective film layer that does not overlap the first wiring electrode or the second wiring electrode in the plan view of the semiconductor layer.

[0059] In addition, it can be that a height of the first outer peripheral structure from a top surface of the first wiring electrode exposed portion is 50% or more of a thickness of the first wiring electrode at the first opening portion, and a height of the second outer peripheral structure from a top surface of the second wiring electrode exposed portion is 50% or more of a thickness of the second wiring electrode at the second opening portion.

[0060] In addition, it can be that a first occupancy ratio, which is an occupancy ratio of an area of the first opening portion in a plan view of the semiconductor layer with respect to an area of the source electrode in the plan view of the semiconductor layer, is 0.5 or more and less than 1.0, in a case where the area of the source electrode in the plan view of the semiconductor layer is set to M1 and the area of the first opening portion in the plan view of the semiconductor layer is set to S1.

[0061] In addition, it can be that the first occupancy ratio is 0.9 or more and less than 1.0, and a second occupancy ratio, which is an occupancy ratio of an area of the first wiring electrode exposed portion in the plan view of the semiconductor layer with respect to the area of the source electrode in the plan view of the semiconductor layer, is 0.9 or more and 1.1 or less, in a case where the area of the first wiring electrode exposed portion in the plan view of the semiconductor layer is set to P1.

[0062] In addition, it can be that a third occupancy ratio, which is an occupancy ratio of an area of the second wiring electrode exposed portion in the plan view of the semiconductor layer with respect to an area of the second opening portion in the plan view of the semiconductor layer, is 1.27 or more, in a case where the area of the second opening portion in the plan view of the semiconductor layer is set to S2 and the area of the second wiring electrode exposed portion in the plan view of the semiconductor layer is set to P2.

[0063] In addition, it can be that, in the plan view of the semiconductor layer, shapes of the first wiring electrode and the second wiring electrode are linearly symmetrical with a central line as a symmetrical axis, the central line bisecting the semiconductor device in area.

[0064] The mounting substrate of one embodiment of the present application is a mounting substrate in which a first wiring layer, an interlayer insulating layer, and a second wiring layer are sequentially stacked, and includes the semiconductor device described above mounted in the interlayer insulating layer with the top surface facing upward, a first wiring formed in the second wiring layer, and one or more first connection wirings connecting the first wiring and the top surface of the first wiring electrode and extending in a direction orthogonal to the mounting substrate, the one or more first connection wirings being connected to the top surface of the first wiring electrode at a portion of the top surface of the first wiring electrode which does not overlap with the first outer peripheral structure in a plan view of the semiconductor layer.

[0065] According to the mounting substrate described above, the first outer peripheral structure and the second outer peripheral structure are recessed into the material forming the interlayer insulating layer on the top surface of the semiconductor device.

[0066] Thus, the first outer peripheral structure and the second outer peripheral structure recessed into the material forming the interlayer insulating layer function as an anchor for fixing the position of the semiconductor device in the interlayer insulating layer, and as a result, peeling of the interlayer insulating layer in the mounting substrate and stabilization of the position of the semiconductor device in the mounting substrate are achieved.

[0067] In addition, in the case where the material forming the interlayer insulating layer is resin, for example, a protrusion reflecting the first outer peripheral structure and the second outer peripheral structure is formed on the top surface of the resin cured after the semiconductor device is enclosed, i.e., the top surface of the interlayer insulating layer.

[0068] Thus, in the case where the interlayer insulating layer is processed to form a hole reaching the first wiring electrode exposure portion from the top surface of the interlayer insulating layer, the protrusion corresponding to the first outer peripheral structure formed on the top surface of the interlayer insulating layer is used as a guide line, and the hole is formed inside the protrusion, whereby the hole reaching the first wiring electrode exposure portion from the top surface of the interlayer insulating layer can be formed with higher precision than in the case where the protrusion is not present.

[0069] Further, similarly, in the case where the interlayer insulating layer is processed to form a hole reaching the second wiring electrode exposure portion from the top surface of the interlayer insulating layer, the protrusion corresponding to the second outer peripheral structure formed on the top surface of the interlayer insulating layer is used as a guide line, and the hole is formed inside the protrusion, whereby the hole reaching the second wiring electrode exposure portion from the top surface of the interlayer insulating layer can be formed with higher precision than in the case where the protrusion is not present.

[0070] Thus, according to the mounting substrate described above, a mounting substrate in which a semiconductor device having a structure suitable for a mounting method in which the semiconductor device is buried in the mounting substrate is mounted is provided.

[0071] In addition, the mounting substrate can further include a second wiring formed in the second wiring layer, and a second connection wiring connecting the second wiring and an upper surface of the second wiring electrode and extending in a direction orthogonal to the mounting substrate, the second connection wiring being connected to the upper surface of the second wiring electrode at a portion of the upper surface of the second wiring electrode that does not overlap the second outer peripheral structure in a plan view of the semiconductor layer, the cross section of each of the one or more first connection wirings in a direction orthogonal to the direction in which the one or more first connection wirings extend and the cross section of the second connection wiring in a direction orthogonal to the direction in which the second connection wiring extends being circular, and the cross section of at least one of the one or more first connection wirings being larger than the cross section of the second connection wiring.

[0072] A mounting substrate of one embodiment of the present application is a mounting substrate in which a first wiring layer, an interlayer insulating layer, and a second wiring layer are sequentially stacked, and includes a semiconductor device mounted in the interlayer insulating layer in a face-up manner, the semiconductor device having a semiconductor layer and including a first wiring electrode on an upper surface, a first wiring formed in the second wiring layer, and one or more first connection wirings connecting the first wiring and the upper surface of the first wiring electrode and extending in a direction orthogonal to the mounting substrate, the semiconductor device including a first outer peripheral structure at an outer peripheral portion of the first wiring electrode in a plan view of the semiconductor layer, the first outer peripheral structure protruding upward from a portion of the upper surface of the first wiring electrode that does not overlap the first outer peripheral structure in the plan view of the semiconductor layer, the uppermost position of the semiconductor device being present in the first outer peripheral structure, the first wiring electrode being exposed to the outside of the semiconductor device at least at the portion of the upper surface of the first wiring electrode that does not overlap the first outer peripheral structure in the plan view of the semiconductor layer, and the one or more first connection wirings being connected to the upper surface of the first wiring electrode at the portion of the upper surface of the first wiring electrode that does not overlap the first outer peripheral structure in the plan view of the semiconductor layer.

[0073] According to the mounting substrate described above, the first outer peripheral structure is recessed into the material forming the interlayer insulating layer at the upper surface of the semiconductor device.

[0074] Thus, the first outer peripheral structure recessed into the material forming the interlayer insulating layer functions as an anchor that fixes the position of the semiconductor device in the interlayer insulating layer, and as a result, peeling of the interlayer insulating layer in the mounting substrate and stabilization of the position of the semiconductor device inside the mounting substrate are achieved.

[0075] In addition, in a case where a material forming the interlayer insulating layer is, for example, a resin, a protrusion reflecting the first outer peripheral configuration is formed on an upper surface of the resin cured after the semiconductor device is enclosed, that is, an upper surface of the interlayer insulating layer.

[0076] Therefore, in a case where a hole reaching the first wiring electrode exposure portion from the upper surface of the interlayer insulating layer is processed, the protrusion corresponding to the first outer peripheral configuration formed on the upper surface of the interlayer insulating layer is used as a guide line, and processing of the hole reaching the first wiring electrode exposure portion from the upper surface of the interlayer insulating layer is performed inside the protrusion, whereby the processing of the hole reaching the first wiring electrode exposure portion from the upper surface of the interlayer insulating layer can be performed with higher accuracy than in a case where the protrusion is not present.

[0077] Thus, according to the mounting substrate of the above-described structure, a mounting substrate on which a semiconductor device having a configuration suitable for a mounting method of being buried in the mounting substrate is mounted is provided.

[0078] In addition, the one or more first connection wirings can be a plurality of.

[0079] In addition, a height from the lowest position in the upper surface of the first wiring electrode to the uppermost position of the semiconductor device can be 15% or more of the length of the one or more first connection wirings in a direction orthogonal to the mounting substrate.

[0080] In addition, the first wiring electrode can be a plurality of, the one or more first connection wirings can be a plurality of corresponding to the plurality of first wiring electrodes in pairs, respectively, the plurality of first connection wirings can be connected to the first wiring electrode by one of the plurality of first wiring electrodes corresponding to the first connection wiring in pairs, respectively, and the cross sections of the plurality of first connection wirings each in a direction orthogonal to the direction in which the plurality of first connection wirings each extend can be equal to each other.

[0081] In addition, in a plan view of the mounting substrate, the mounting substrate can have a shape having a long side direction, the semiconductor device can have a shape having a long side direction, and the long side direction of the mounting substrate and the long side direction of the semiconductor device can be orthogonal to each other.

[0082] In addition, the mounting substrate can further include an electronic component disposed at a position higher than the interlayer insulating layer, in a plan view of the mounting substrate, the electronic component can have a shape having a long side direction, the semiconductor device can have a shape having a long side direction, at least a portion of the electronic component can overlap the semiconductor device, and the long side direction of the electronic component and the long side direction of the semiconductor device can be orthogonal to each other.

[0083] A specific example of a semiconductor device according to one embodiment of the present application will be described below with reference to the drawings. The embodiments shown in the drawings are merely examples of the present application. Therefore, the numerical values, shapes, constituent elements, arrangement and connection modes of the constituent elements, and steps (procedures) and the order of the steps shown in the following embodiments are merely examples, and are not intended to limit the present application. In addition, the drawings are schematic, and the illustration is not necessarily strict. In the drawings, the same reference numerals are assigned to substantially the same structures, and repeated description is omitted or simplified.

[0084] (Embodiment 1)

[0085] Hereinafter, the semiconductor device according to Embodiment 1 will be described. The semiconductor device is a chip size package type semiconductor device capable of face-up mounting, and has a configuration suitable for mounting by a mounting method of burying a mounting substrate.

[0086] Structure

[0087] Hereinafter, the configuration of the semiconductor device according to Embodiment 1 will be described. The semiconductor device according to Embodiment 1 is a chip size package (CSP) type semiconductor device in which N (N is an integer of 1 or more) vertical type MOS (Metal Oxide Semiconductor) transistors are formed. The N vertical type MOS transistors are so-called trench type MOSFETs (Field Effect Transistors).

[0088] In the present application, N is described as being 2, but N is not necessarily limited to 2, and N can be 1 or 3 or more.

[0089] Figure 1 is a plan view showing one example of the configuration of the semiconductor device 1 according to Embodiment 1. As shown in Figure 1 , the semiconductor device 1 is rectangular in the plan view of the semiconductor device 1 (i.e., in the plan view of the semiconductor layer 40 described later).

[0090] Figure 2 , Figure 3 is a sectional view showing one example of the configuration of the semiconductor device 1. Figure 2 represents a cross section of I-I of Figure 1 , Figure 3 represents a cross section of II-II of Figure 1 .

[0091] As shown in Figures 1-3As shown, the semiconductor device 1 includes the metal layer 30, the semiconductor layer 40, the oxide film 34, the protective film 35, the first vertical MOS transistor 10 formed in the semiconductor layer 40, the second vertical MOS transistor 20 formed in the semiconductor layer 40, the first source electrode 13 functioning as a source electrode of the first vertical MOS transistor 10, the first gate electrode 19 functioning as a gate electrode of the first vertical MOS transistor 10, the second source electrode 23 functioning as a source electrode of the second vertical MOS transistor 20, the second gate electrode 29 functioning as a gate electrode of the second vertical MOS transistor 20, the first wiring electrode 12 connected to the first source electrode 13, the second wiring electrode 52 connected to the first gate electrode 19, the third wiring electrode 22 connected to the second source electrode 23, and the fourth wiring electrode 54 connected to the second gate electrode 29.

[0092] In the present application, the semiconductor device 1 is described as including the metal layer 30, but the semiconductor device 1 is not necessarily limited to the structure including the metal layer 30.

[0093] In addition, in Figure 1 , the first source electrode 13, the first gate electrode 19, the second source electrode 23, the second gate electrode 29, the first opening portion 61 described later, the second opening portion 62 described later, the third opening portion 63 described later, and the fourth opening portion 64 described later are illustrated as being visually recognizable by the broken lines, but in fact, these constituent elements cannot be visually recognized directly from the outside of the semiconductor device 1.

[0094] The semiconductor layer 40 is configured by laminating the semiconductor substrate 32 and the low-concentration impurity layer 33.

[0095] Here, if the area of the semiconductor layer 40 in a plan view of the semiconductor layer 40 is assumed to be S [mm 2 ], and the thickness from the lower surface of the semiconductor layer 40 to the upper surface of the protective film 35 is assumed to be h [mm], then the relationship h / S >= 0.025 is satisfied.

[0096] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 and is composed of silicon containing impurities of the first conductivity type.

[0097] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains impurities of the first conductivity type having a lower concentration than the impurities of the first conductivity type of the semiconductor substrate 32. The low-concentration impurity layer 33 may, for example, be formed on the semiconductor substrate 32 by epitaxial growth.

[0098] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33.

[0099] The protective film 35 is a protective film that covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, and has a first opening portion 61 that exposes the first source electrode 13 to the outside of the protective film 35, a second opening portion 62 that exposes the first gate electrode 19 to the outside of the protective film 35, a third opening portion 63 that exposes the second source electrode 23 to the outside of the protective film 35, and a fourth opening portion 64 that exposes the second gate electrode 29 to the outside of the protective film 35.

[0100] Here, the fact that the protective film 35 covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20 means that the protective film 35 is formed on substantially the entire surface of the semiconductor device 1 except for the opening portions in a plan view of the semiconductor layer 40. Here, the substantially entire surface of the semiconductor device 1 means the entire surface of the semiconductor device 1 in a region of the wafer that is ensured as a margin when the semiconductor device 1 is cut from the wafer, except for a peripheral region that is slightly left on the four sides of the semiconductor device 1 after cutting. Therefore, in this peripheral region, the oxide film 34 is exposed on the upper surface of the semiconductor device 1 except as described above.

[0101] In addition, the opening portion of the protective film 35 according to the present application means a shape in which the entire length of the outer periphery of the opening portion is enclosed by the protective film 35 in a plan view of the semiconductor layer 40. Therefore, in a plan view of the semiconductor layer 40, a shape in which a part of the outer periphery overlaps with the peripheral region in which the oxide film 34 is exposed on the upper surface of the semiconductor device 1 except as described above does not correspond to the opening portion of the protective film 35 according to the present application.

[0102] In the present application, the protective film 35 is described as having one first opening portion 61 as an opening portion that exposes the first source electrode 13 to the outside of the protective film 35, but the protective film 35 can have a plurality of opening portions as opening portions that expose the first source electrode 13 to the outside of the protective film 35.

[0103] Similarly, in the present application, the protective film 35 is described as having one second opening portion 62 as an opening portion that exposes the first gate electrode 19 to the outside of the protective film 35, but the protective film 35 can have a plurality of opening portions as opening portions that expose the first gate electrode 19 to the outside of the protective film 35.

[0104] In the present application, the protective film 35 is described as having one third opening portion 63 as an opening portion that exposes the second source electrode 23 to the outside of the protective film 35, but the protective film 35 can have a plurality of opening portions as opening portions that expose the second source electrode 23 to the outside of the protective film 35.

[0105] Similarly, in the present application, the protective film 35 is described as having one fourth opening portion 64 as an opening portion through which the second gate electrode 29 is exposed to the outside of the protective film 35, but the protective film 35 can have a plurality of opening portions as opening portions through which the second gate electrode 29 is exposed to the outside of the protective film 35.

[0106] Further, the protective film 35 can be a single layer structure or a multi-layer structure in which a plurality of layers are stacked. In the present application, the protective film 35 is described as having a multi-layer structure (here, a two-layer structure) in which a first protective film layer 35A and a second protective film layer 35B positioned above the first protective film layer 35A are stacked.

[0107] As one example without limitation, the first protective film layer 35A can also be composed of silicon nitride, for example, with a film thickness of 0.3 μm.

[0108] As one example without limitation, the second protective film layer 35B can also be composed of polyimide, for example, with a film thickness of 8 μm.

[0109] The metal layer 30, which is formed in contact with the lower surface of the semiconductor substrate 32, can be composed of silver, copper, nickel, or an alloy thereof, or can be composed of a metal material having a high conductivity capable of functioning as an electrode. Further, in the metal layer 30, a small amount of an element other than a metal that is mixed as an impurity in the manufacturing process of the metal material can also be contained.

[0110] In the region of the low-concentration impurity layer 33 in which the first vertical MOS transistor 10 is formed, a first body region 18 containing an impurity of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14 containing an impurity of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed.

[0111] The first source electrode 13 is connected to the first source region 14 and the first body region 18 through the opening of the oxide film 34.

[0112] As one example without limitation, the first source electrode 13 can also be composed of a metal material containing any one or more of aluminum, copper, gold, and silver.

[0113] The first wiring electrode 12 is connected to the first source electrode 13 and covers the exposed portion of the first source electrode 13 to the outside of the protective film 35 in the first opening portion 61 without a gap. Thereby, the first source electrode 13 is prevented from being corroded by a substance outside the semiconductor device 1.

[0114] The first wiring electrode 12 is formed by plating with copper as the main component, as one example without limitation. The first wiring electrode 12 has a thickness of, for example, 10 μm.

[0115] Further, in a case where the protective film 35 has one or more opening portions in addition to the first opening portion 61, through which the first source electrode 13 is exposed to the outside of the protective film 35, the semiconductor device 1 has, with respect to each of these one or more opening portions, a wiring electrode similar to the first wiring electrode 12.

[0116] The first gate electrode 19 is electrically connected to the first gate conductor 15.

[0117] As an example not limited thereto, the first gate electrode 19 can be composed of a metal material including one or more of aluminum, copper, gold, and silver.

[0118] The second wiring electrode 52 is connected to the first gate electrode 19 and covers, without a gap, the exposed portion of the first gate electrode 19 to the outside of the protective film 35 in the second opening portion 62. Thus, the first gate electrode 19 is prevented from being corroded by a substance outside the semiconductor device 1.

[0119] The second wiring electrode 52 is composed mainly of copper and is formed, as an example not limited thereto, by plating. The second wiring electrode 52 has, for example, a thickness of 10 μm.

[0120] Further, in a case where the protective film 35 has one or more opening portions in addition to the second opening portion 62, through which the first gate electrode 19 is exposed to the outside of the protective film 35, the semiconductor device 1 has, with respect to each of these one or more opening portions, a wiring electrode similar to the second wiring electrode 52.

[0121] In the region of the low-concentration impurity layer 33 in which the second vertical MOS transistor 20 is formed, a second body region 28 including an impurity of a second conductivity type different from the first conductivity type is formed. In the second body region 28, a second source region 24 including an impurity of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0122] The second source electrode 23 is connected to the second source region 24 and the second body region 28 through the opening of the oxide film 34.

[0123] As an example not limited thereto, the second source electrode 23 can be composed of a metal material including one or more of aluminum, copper, gold, and silver.

[0124] The third wiring electrode 22 is connected to the second source electrode 23 and covers, without a gap, the exposed portion of the second source electrode 23 to the outside of the protective film 35 in the third opening portion 63. Thus, the second source electrode 23 is prevented from being corroded by a substance outside the semiconductor device 1.

[0125] The third wiring electrode 22 is composed mainly of copper and is formed, as an example not limited thereto, by plating. The third wiring electrode 22 has, for example, a thickness of 10 μm.

[0126] Further, in a case where the protective film 35 has one or more opening portions that expose the second source electrode 23 to the outside of the protective film 35 in addition to the third opening portion 63, the semiconductor device 1 has the same wiring electrode as the third wiring electrode 22 with respect to each of these one or more opening portions.

[0127] The second gate electrode 29 is electrically connected to the second gate conductor 25.

[0128] As an example not limited thereto, the second gate electrode 29 can also be composed of a metal material including one or more of aluminum, copper, gold, and silver.

[0129] The fourth wiring electrode 54 is connected to the second gate electrode 29 and covers, without a gap, the exposed portion of the second gate electrode 29 to the outside of the protective film 35 in the fourth opening portion 64. Thereby, the second gate electrode 29 is suppressed from being corroded by a substance outside the semiconductor device 1.

[0130] The fourth wiring electrode 54 is formed by plating with copper as a main component, as an example not limited thereto. The fourth wiring electrode 54 has a thickness of, for example, 10 μm.

[0131] Further, in a case where the protective film 35 has one or more opening portions that expose the second gate electrode 29 to the outside of the protective film 35 in addition to the fourth opening portion 64, the semiconductor device 1 has the same wiring electrode as the fourth wiring electrode 54 with respect to each of these one or more opening portions.

[0132] Here, the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54 are thinner than the thickness of the metal layer 30. That is, the thickness of the metal layer 30 is thicker than the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54.

[0133] In the semiconductor device 1, for example, the first conductive type can be set to N type, the second conductive type can be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be N-type semiconductors, and the first body region 18 and the second body region 28 can be P-type semiconductors.

[0134] In the semiconductor device 1, for example, the first conductive type can be set to P type, the second conductive type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be P-type semiconductors, and the first body region 18 and the second body region 28 can be N-type semiconductors.

[0135] In this invention, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described as so-called N-channel transistors, wherein the first conductivity type is N-type and the second conductivity type is P-type.

[0136] In addition, in this invention, the first vertical MOS transistor 10 is the same as the second vertical MOS transistor 20, the first source electrode 13 is the same as the second source electrode 23, the first gate electrode 19 is the same as the second gate electrode 29, the first wiring electrode 12 is the same as the third wiring electrode 22, and the second wiring electrode 52 is the same as the fourth wiring electrode 54.

[0137] Therefore, the following description will focus on the first vertical MOS transistor 10 and the second vertical MOS transistor 20, using them as representatives. The description will focus on the first source electrode 13 and the second source electrode 23, using them as representatives. The description will focus on the first gate electrode 19 and the second gate electrode 29, using them as representatives. The description will focus on the first wiring electrode 12 and the third wiring electrode 22, using them as representatives. The description will focus on the second wiring electrode 52 and the fourth wiring electrode 54, using them as representatives.

[0138] like Figure 2 , Figure 3 As shown, the upper surface of the first wiring electrode 12 is exposed outside the semiconductor device 1, and the upper surface of the second wiring electrode 52 is exposed outside the semiconductor device 1.

[0139] In this invention, the portion of the upper surface of the first wiring electrode 12 that is exposed outside the semiconductor device 1 (semiconductor device 1A described later in Embodiment 2) is defined as the first wiring electrode exposed portion 71, and the portion of the upper surface of the second wiring electrode 52 that is exposed outside the semiconductor device 1 (semiconductor device 1A described later in Embodiment 2) is defined as the second wiring electrode exposed portion 72.

[0140] Therefore, in Embodiment 1, the first exposed wiring electrode 71 is the upper surface of the first wiring electrode 12, and the second exposed wiring electrode 72 is the upper surface of the second wiring electrode 52.

[0141] That is, in Embodiment 1, the first wiring electrode exposed portion 71, which is the upper surface of the first wiring electrode 12, is exposed to the outside of the semiconductor device 1, and the second wiring electrode exposed portion 72, which is the upper surface of the second wiring electrode 52, is exposed to the outside of the semiconductor device 1.

[0142] Here, as Figures 1-3As shown, in the plan view of the semiconductor layer 40, the area of the first wiring electrode exposed portion 71 is larger than the area of the first opening portion 61, and the area of the second wiring electrode exposed portion 72 is larger than the area of the second opening portion 62.

[0143] In addition, as Figure 2 , Figure 3 shown, in the outer peripheral portion of the semiconductor layer 40 in the plan view of the first wiring electrode 12, a first outer peripheral structure 101 in which the first source electrode 13, the protective film 35, and the first wiring electrode 12 are sequentially stacked is formed, and in the outer peripheral portion of the semiconductor layer 40 in the plan view of the second wiring electrode 52, a second outer peripheral structure 102 in which the first gate electrode 19, the protective film 35, and the second wiring electrode 52 are sequentially stacked is formed.

[0144] Here, the uppermost layer of the first outer peripheral structure 101 is the first wiring electrode 12, and the uppermost layer of the second outer peripheral structure 102 is the second wiring electrode 52.

[0145] As Figure 2 , Figure 3 shown, the first outer peripheral structure 101 protrudes upward from the upper surface of the portion of the first wiring electrode exposed portion 71 that is not included in the first outer peripheral structure 101, the second outer peripheral structure 102 protrudes upward from the upper surface of the portion of the second wiring electrode exposed portion 72 that is not included in the second outer peripheral structure 102, and the uppermost position of the semiconductor device 1 is present in the first outer peripheral structure 101 and / or the second outer peripheral structure 102.

[0146] Figure 4 is a captured image obtained by capturing a portion near the second wiring electrode 52 in the upper surface of the semiconductor device 1 from an oblique upper side of the semiconductor device 1.

[0147] As Figure 4 can be seen, in the outer peripheral portion of the semiconductor layer 40 in the plan view of the second wiring electrode 52, the second outer peripheral structure 102 that protrudes upward from the upper surface of the portion that is not included in the second outer peripheral structure 102 is formed.

[0148] Figure 5 is an enlarged cross-sectional view showing the structure of the first outer peripheral structure 101.

[0149] In the present application, the second outer peripheral structure 102 is described as being the same as when the first source electrode 13 is replaced with the first gate electrode 19 with respect to the first outer peripheral structure 101.

[0150] Therefore, hereinafter, the first outer peripheral structure 101 and the second outer peripheral structure 102 will be described using Figure 5 .

[0151] As Figure 5As shown, the outer peripheral portion of the first wiring electrode 12 in the plan view of the semiconductor layer 40 has a first wall 201. The first wall 201 is in the shape of an inverted cone facing the outside of the first wiring electrode 12 in the cross-sectional view of the semiconductor layer 40 and does not contact the protective film 35.

[0152] In addition, such as Figure 5 As shown, the portion of the protective film 35 around the first opening 61 in the plan view of the semiconductor layer 40 has a first cone-shaped region 202 that is cone-shaped toward the first opening 61 in the cross-sectional view of the semiconductor layer 40.

[0153] Here, as Figure 5 As shown, in the plan view of semiconductor layer 40, the first wall 201 is located inside the first cone-shaped region 202.

[0154] Similarly, the second wiring electrode 52 has a second wall on the outer periphery of the semiconductor layer 40 in the plan view. The second wall is in the shape of an inverted cone facing the outside of the second wiring electrode 52 in the cross-sectional view of the semiconductor layer 40 and does not contact the protective film 35.

[0155] Similarly, the portion of the protective film 35 surrounding the second opening 62 in the plan view of the semiconductor layer 40 has a second cone-shaped region that is cone-shaped toward the second opening 62 in the cross-sectional view of the semiconductor layer 40.

[0156] Similarly, in the plan view of semiconductor layer 40, the second wall is located inside the second cone-shaped region.

[0157] <Inspection>

[0158] When the semiconductor device 1 with the above structure is sealed in resin within a mounting substrate and mounted facing upwards, the first peripheral structure 101 and the second peripheral structure 102 are embedded in the resin on the upper surface of the semiconductor device 1.

[0159] Therefore, the first peripheral structure 101 and the second peripheral structure 102 embedded in the resin serve to anchor the position of the semiconductor device 1 within the resin, resulting in the suppression of resin peeling from the mounting substrate and the stabilization of the position of the semiconductor device 1 inside the mounting substrate.

[0160] In addition, protrusions reflecting the first peripheral structure 101 and the second peripheral structure 102 are formed on the upper surface of the resin that has been cured after being encapsulated in the semiconductor device 1.

[0161] Therefore, in a case where the resin is processed to form a hole reaching the first wiring electrode exposure portion 71 from the upper surface of the resin, the protrusion formed on the upper surface of the resin corresponding to the first outer peripheral structure 101 is used as a guide line, and the resin is processed to form a hole inside the protrusion, whereby the processing to form a hole reaching the first wiring electrode exposure portion 71 from the upper surface of the resin can be performed with higher accuracy than in a case where the protrusion is not present.

[0162] Also, similarly, in a case where the resin is processed to form a hole reaching the second wiring electrode exposure portion 72 from the upper surface of the resin, the protrusion formed on the upper surface of the resin corresponding to the second outer peripheral structure 102 is used as a guide line, and the resin is processed to form a hole inside the protrusion, whereby the processing to form a hole reaching the second wiring electrode exposure portion 72 from the upper surface of the resin can be performed with higher accuracy than in a case where the protrusion is not present.

[0163] Thus, according to the semiconductor device 1 having the above-described structure, a semiconductor device having a structure suitable for a mounting method in which the semiconductor device is buried in a mounting substrate is provided.

[0164] As described above, in the plan view of the semiconductor layer 40, the area of the first wiring electrode exposure portion 71 is larger than the area of the first opening portion 61, and the area of the second wiring electrode exposure portion 72 is larger than the area of the second opening portion 62.

[0165] Thus, in the plan view of the semiconductor layer 40, compared to a case where the area of the first wiring electrode exposure portion 71 is not larger than the area of the first opening portion 61 and the area of the second wiring electrode exposure portion 72 is not larger than the area of the second opening portion 62, the degree of freedom of the processing to form a hole reaching the first wiring electrode exposure portion 71 from the upper surface of the resin and the processing to form a hole reaching the second wiring electrode exposure portion 72 from the upper surface of the resin can be improved.

[0166] In a case where the semiconductor device 1 is mounted by being buried in a mounting substrate, the semiconductor device 1 is sometimes subjected to stress and impact from the mounting substrate. If the thickness from the lower surface of the semiconductor layer 40 to the upper surface of the protective film 35 (hereinafter, also referred to as "Si thickness") is too small with respect to the area of the semiconductor device 1 in the plan view of the semiconductor layer 40 (hereinafter, also referred to as "chip area"), the semiconductor device 1 cannot have sufficient resistance to stress and impact from such mounting substrates.

[0167] The inventors conducted experiments and research on the relationship between the stress and impact resistance of the semiconductor device 1 against the mounting substrate and the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 and the Si thickness. As a result, the inventors obtained the following insight: in the case where the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is 2 [mm] x 2 [mm], if the Si thickness is 0.1 mm or more, the semiconductor device 1 can obtain sufficient stress and impact resistance against the mounting substrate.

[0168] Based on this insight, the inventors further conducted experiments and research repeatedly and obtained the following insight: in the case where the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is less than 2 [mm] x 2 [mm], even if the Si thickness h [mm] is made thinner in proportion to the chip area S [mm 2 ], the semiconductor device 1 can obtain sufficient stress and impact resistance against the mounting substrate; and in the case where the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is more than 2 [mm] x 2 [mm], if the Si thickness h [mm] is made thicker in proportion to the chip area S [mm 2 ], the semiconductor device 1 can obtain sufficient stress and impact resistance against the mounting substrate.

[0169] Figure 6 is a diagram showing the relationship between the stress and impact resistance of the semiconductor device 1 against the mounting substrate and the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 and the Si thickness, which the inventors obtained through experiments and research.

[0170] As Figure 6 shown, if the chip area is set to S [mm 2 ] and the Si thickness is set to h [mm], then in the range where the relationship h / S ≧ 0.025 holds, the semiconductor device 1 can obtain sufficient stress and impact resistance against the mounting substrate.

[0171] Figure 7 is a cross-sectional view of the semiconductor device 1 and the first outer peripheral structure 101 schematically showing an example of the case where the semiconductor device 1 is deformed due to a heat treatment process at the time of resin sealing in the case where the semiconductor device 1 is resin-sealed and mounted face-up in the mounting substrate.

[0172] As described above, the semiconductor device 1 has the metal layer 30 thicker than the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54 on the back surface side. In general, the metal (for example, silver, copper, nickel, or an alloy thereof) that constitutes the metal layer 30 has a larger thermal expansion rate than the impurity-containing semiconductor (for example, silicon doped with an impurity) that constitutes the semiconductor layer 40.

[0173] Therefore, as shown in (b) of FIG. 10, when the semiconductor device 1 is resin-sealed in the mounting substrate, the temperature of the semiconductor device 1 also rises at the time of heat treatment for curing the resin, and thus warping that protrudes the back surface of the semiconductor device 1 occurs. As a result, as shown in (a) and (b) of FIG. 10, the inclination of the first wall surface 201 that becomes an inverted taper shape of the first outer periphery structure 101 at the time of heat treatment changes toward the upper side of the semiconductor device 1 compared to before the heat treatment. Figure 7 Figure 7 Therefore, as shown in (b) of FIG. 10, when the semiconductor device 1 is resin-sealed in the mounting substrate, the temperature of the semiconductor device 1 also rises at the time of heat treatment for curing the resin, and thus warping that protrudes the back surface of the semiconductor device 1 occurs. As a result, as shown in (a) and (b) of FIG. 10, the inclination of the first wall surface 201 that becomes an inverted taper shape of the first outer periphery structure 101 at the time of heat treatment changes toward the upper side of the semiconductor device 1 compared to before the heat treatment.

[0174] After that, if the heat treatment ends and the temperature of the resin and the semiconductor device 1 is cooled (if it returns to normal temperature), as shown in (c) of FIG. 10, the warping that protrudes the back surface of the semiconductor device 1 is relaxed. As a result, as shown in (a) and (c) of FIG. 10, the inclination of the first wall surface 201 that becomes an inverted taper shape of the first outer periphery structure 101 after the cooling changes toward the lower side of the semiconductor device 1 compared to at the time of the heat treatment. Figure 7 Figure 7

[0175] Thus, the inclination of the first wall surface 201 that becomes an inverted taper shape of the first outer periphery structure 101 changes from the upper side of the semiconductor device 1 toward the lower side as the warping of the semiconductor device 1 is relaxed during the process in which the heat treatment ends and the temperature of the resin and the semiconductor device 1 is cooled. By this change, the first outer periphery structure 101 sinks more firmly into the resin compared to a structure that does not have the first wall surface 201 that becomes an inverted taper shape.

[0176] Therefore, according to the semiconductor device 1 of the above-described structure, the first outer periphery structure 101 has the first wall surface 201 that becomes an inverted taper shape, thereby functioning as an anchor that more firmly fixes the position of the semiconductor device 1 in the resin compared to a structure that does not have the first wall surface 201, as a result, further suppression of resin peeling in the mounting substrate and further stabilization of the position of the semiconductor device 1 inside the mounting substrate are achieved.

[0177] ​​​Further, based on the same reason, according to the semiconductor device 1 of the above structure, the second outer peripheral structure 102 functions as an anchor that more firmly fixes the position of the semiconductor device 1 in the resin by having the second wall surface that becomes an inverted taper shape, compared to a structure that does not have the second wall surface, as a result, further suppression of resin peeling in the mounting substrate and further stabilization of the position of the semiconductor device 1 inside the mounting substrate are achieved.

[0178] Further, as described above, in the plan view of the semiconductor layer 40, the first wall surface 201 is located inside the first taper shape region 202.

[0179] Thus, according to the semiconductor device 1 of the above structure, the first outer peripheral structure 101 more firmly sinks into the resin compared to a structure in which the first wall surface 201 is not located inside the first taper shape region 202.

[0180] Thus, according to the semiconductor device 1 of the above structure, the first outer peripheral structure 101 functions as an anchor that more firmly fixes the position of the semiconductor device 1 in the resin by having the first wall surface 201 located inside the first taper shape region 202 in the plan view of the semiconductor layer 40, compared to a structure in which the first wall surface 201 is not located inside the first taper shape region 202 in the plan view of the semiconductor layer 40, as a result, further suppression of resin peeling in the mounting substrate and further stabilization of the position of the semiconductor device 1 inside the mounting substrate are achieved.

[0181] Further, based on the same reason, according to the semiconductor device 1 of the above structure, the second outer peripheral structure 102 functions as an anchor that more firmly fixes the position of the semiconductor device 1 in the resin by having the second wall surface located inside the second taper shape region in the plan view of the semiconductor layer 40, compared to a structure in which the second wall surface is not located inside the second taper shape region in the plan view of the semiconductor layer 40, as a result, further suppression of resin peeling in the mounting substrate and further stabilization of the position of the semiconductor device 1 inside the mounting substrate are achieved.

[0182] However, in the plan view of the semiconductor layer 40, the first wall surface 201 and the second wall surface that become inverted taper shapes can also become an encircling inverted taper shape along the outer periphery of the first wiring electrode 12 and the second wiring electrode 52, but can also become an inverted taper shape only in a part along the outer periphery.

[0183] In a case where the first wall surface 201 and the second wall surface are provided with the inverted taper shape only in a part along the outer periphery, it is preferable to provide the inverted taper shape in a part that matches a direction in which warping of the semiconductor device 1 is the largest. For example, in a plan view of the semiconductor layer 40, in a case where the semiconductor device 1 is rectangular having a long side direction, warping in the long side direction becomes the largest warping, and thus it is preferable to provide the inverted taper shape in a part of the first wall surface 201 and the second wall surface that includes a position orthogonal to the long side direction of the semiconductor device 1.

[0184] Figure 8 is a plan view of the semiconductor device 1 in a case where the area of the first source electrode 13 is M1, the area of the first opening portion 61 is S1, the area of the first wiring electrode exposure portion 71 is P1, and the area of the first opening portion 61 relative to the area of the first source electrode 13 indicated by S1 / M1 is 0.5 or more and less than 1.0 (hereinafter, also referred to as "first case"). Figure 8 The first wiring electrode exposure portion 71 is not illustrated in Figure 10 , but the area P1 of the first wiring electrode exposure portion 71 in a plan view of the semiconductor layer 40 is the same as the area of the first wiring electrode 12 in Figure 8 and Figure 10 described later.

[0185] Figure 9 is a cross-sectional view of the semiconductor device 1 in the first case, indicating the cross section of III-III in Figure 8

[0186] Figure 10 is a plan view of the semiconductor device 1 in a case where the area of the first opening portion 61 relative to the area of the first source electrode 13 indicated by S1 / M1 is 0.9 or more and less than 1.0, and the area of the first wiring electrode exposure portion 71 relative to the area of the first source electrode 13 indicated by P1 / M1 is 0.5 or more (hereinafter, also referred to as "second case").

[0187] Figure 11 is a cross-sectional view of the semiconductor device 1 in the second case, indicating the cross section of IV-IV in Figure 10

[0188] Generally, a semiconductor device mounted in a face-down manner using a bonding material such as solder is commonly S1 / M1 less than 0.5 in order to suppress occurrence of mounting failure caused by voids and the like of the bonding material.

[0189] ​​On the other hand, the semiconductor device 1 according to the present application is mounted in an upward-facing manner without using a bonding material such as solder, and thus does not have to worry about mounting failure due to voids or the like of the bonding material. Therefore, from the viewpoint of reducing the on-resistance of the semiconductor device 1 and improving the heat dissipation characteristics of the semiconductor device 1, as shown in the example of Figure 8 , Figure 9 In the semiconductor device 1, S1 / M1 is preferably 0.5 or more, that is, S1 / M1 is preferably 0.5 or more and less than 1.0.

[0190] The reason why S1 / M1 is less than 1.0 is that, in the plan view of the semiconductor layer 40, if the area S1 of the first opening portion 61 is larger than the area M1 of the first source electrode 13, the region of the oxide film 34 that is not covered by the first source electrode 13 is opened by the first opening portion 61.

[0191] From the viewpoint of reducing the on-resistance of the semiconductor device 1 and improving the heat dissipation characteristics of the semiconductor device 1, further, in the semiconductor device 1, as shown in the example of Figure 10 , Figure 11 It is more preferable that, in the semiconductor device 1, S1 / M1 be 0.9 or more and less than 1.0, and P1 / M1 be 0.9 or more and 1.1 or less. This is to increase the exposure of the first source electrode 13 to the outside as much as possible for the reduction of the on-resistance of the semiconductor device 1 and the heat dissipation characteristics of the semiconductor device 1.

[0192] Further, in the example shown in Figure 10 , Figure 11 In the plan view of the semiconductor layer 40, in a case where the area of the first gate electrode 19 is set to M2, the area of the second opening portion 62 is set to S2, and the area of the second wiring electrode exposure portion 72 is set to P2, the ratio of the area of the second wiring electrode exposure portion 72 to the area of the first gate electrode 19, which is represented by P2 / M2, is 0.9 or more and 1.1 or less.

[0193] As shown in the example of Figure 10 , Figure 11 It is effective that the ratio of the area of the second wiring electrode exposure portion 72 to the area of the first gate electrode 19, which is represented by P2 / M2, be 0.9 or more and 1.1 or less.

[0194] In order to connect the second wiring electrode exposure portion 72 to the outside of the semiconductor device 1 via a hole provided in a resin that seals the semiconductor device 1, it is preferable that the area P2 of the second wiring electrode exposure portion 72 in the plan view of the semiconductor layer 40 be larger than the area S2 of the second opening portion 62 in the plan view of the semiconductor layer 40.

[0195] Generally, the second opening portion 62 is mostly circular in the plan view of the semiconductor layer 40. In contrast, as described above, the semiconductor device 1 is rectangular in the plan view of the semiconductor layer 40.

[0196] Therefore, when P2 is made larger than S2, it is preferable that the second wiring electrode exposed portion 72 in the plan view of the semiconductor layer 40 be rectangular. In this case, in the plan view of the semiconductor layer 40, the shape of the rectangular second wiring electrode exposed portion 72 that is larger than S2 is a square circumscribed to the circular second opening portion 62. Here, the square circumscribed to the circle is 1.27 times the area of the circle.

[0197] It can thus be said that the ratio of the area of the second wiring electrode exposed portion 72 represented by P2 / S2 to the area of the second opening portion 62 is preferably 1.27 or more.

[0198] In addition, in order to make the first wiring electrode exposed portion 71 connect well with an external wiring of the semiconductor device 1 via a hole opened in a resin that seals the semiconductor device 1, and to make the second wiring electrode exposed portion 72 connect well with an external wiring of the semiconductor device 1 via a hole opened in a resin that seals the semiconductor device 1, it is preferable that, in the plan view of the semiconductor layer 40, the area of the first wiring electrode 12 and the area of the second wiring electrode 52 be as large as possible, and that the shape of the first wiring electrode 12 and the shape of the second wiring electrode 52 be equal.

[0199] Figure 12 is a plan view that represents one example of the configuration of the semiconductor device 1 in which the first wiring electrode 12 and the second wiring electrode 52 achieve the above-described desired shape.

[0200] As Figure 12 indicated, in the plan view of the semiconductor layer 40, the shape of the first wiring electrode 12 and the shape of the second wiring electrode 52 are made line-symmetrical with a central line as the axis of symmetry, and the central line becomes a shape that equally divides the semiconductor device 1 in area, whereby the semiconductor device 1 achieves the above-described preferable shape.

[0201] (Embodiment 2)

[0202] Hereinafter, a semiconductor device according to Embodiment 2 will be described, which is configured by changing the first outer peripheral configuration 101 of the semiconductor device 1 according to Embodiment 1 to a first outer peripheral configuration according to Embodiment 2, and changing the second outer peripheral configuration 102 to a second outer peripheral configuration according to Embodiment 2.

[0203] Here, regarding the semiconductor device according to Embodiment 2, the same structural elements as those of the semiconductor device 1 are marked with the same reference numerals and detailed descriptions thereof are omitted, and the description will be made focusing on the differences from the semiconductor device 1.

[0204] Further, in Embodiment 1, it is described that the protective film 35 possessed by the semiconductor device 1 can be either a single-layer structure or a multi-layer structure, but in Embodiment 2, the protective film 35 possessed by the semiconductor device concerned in Embodiment 2 must be a multi-layer structure. Therefore, hereinafter, the protective film 35 possessed by the semiconductor device concerned in Embodiment 2 is described as a multi-layer structure (2-layer structure here) in which a first protective film layer 35A and a second protective film layer 35B are laminated.

[0205] <Structure>

[0206] Figure 13 is a plan view showing one example of the configuration of the semiconductor device 1A concerned in Embodiment 2.

[0207] Figure 14 is a cross-sectional view showing one example of the configuration of the semiconductor device 1A. Figure 14 shows a cross section at V-V in Figure 13

[0208] As shown in Figure 13 , 14 , the semiconductor device 1A is configured by changing the first outer peripheral configuration 101 of the semiconductor device 1 concerned in Embodiment 1 to the first outer peripheral configuration 101A concerned in Embodiment 2 and changing the second outer peripheral configuration 102 to the second outer peripheral configuration 102A concerned in Embodiment 2.

[0209] More specifically, as shown in Figure 14 , in the semiconductor device 1A, the first outer peripheral configuration 101A in which the first source electrode 13, the first protective film layer 35A, the first wiring electrode 12, and the second protective film layer 35B are laminated in this order is formed in the outer peripheral portion in the plan view of the semiconductor layer 40 of the first wiring electrode 12, and the second outer peripheral configuration 102A in which the first gate electrode 19, the first protective film layer 35A, the second wiring electrode 52, and the second protective film layer 35B are laminated in this order is formed in the outer peripheral portion in the plan view of the semiconductor layer 40 of the second wiring electrode 52.

[0210] Here, the uppermost layer of the first outer peripheral configuration 101A is the second protective film layer 35B, and the uppermost layer of the second outer peripheral configuration 102A is the second protective film layer 35B.

[0211] ​With the above-described change, in the semiconductor device 1 according to Embodiment 1, the entire upper surface of the first wiring electrode 12 is exposed to the outside of the semiconductor device 1, and the entire upper surface of the second wiring electrode 52 is exposed to the outside of the semiconductor device 1, in contrast to this, in the semiconductor device 1A, a portion of the upper surface of the first wiring electrode 12 that is not included in the first outer peripheral structure 101A is exposed to the outside of the semiconductor device 1A, and a portion of the upper surface of the second wiring electrode 52 that is not included in the second outer peripheral structure 102A is exposed to the outside of the semiconductor device 1A.

[0212] As described above, in the present application, a portion of the upper surface of the first wiring electrode 12 that is exposed to the outside of the semiconductor device 1A is defined as a first wiring electrode exposed portion 71, and a portion of the upper surface of the second wiring electrode 52 that is exposed to the outside of the semiconductor device 1A is defined as a second wiring electrode exposed portion 72.

[0213] Therefore, in Embodiment 2, the first wiring electrode exposed portion 71 is a portion of the upper surface of the first wiring electrode 12 that is not included in the first outer peripheral structure 101A, and the second wiring electrode exposed portion 72 is a portion of the upper surface of the second wiring electrode 52 that is not included in the second outer peripheral structure 102A.

[0214] That is, in Embodiment 2, a portion of the upper surface of the first wiring electrode 12 that is not included in the first outer peripheral structure 101A, that is, the first wiring electrode exposed portion 71, is exposed to the outside of the semiconductor device 1A, and a portion of the upper surface of the second wiring electrode 52 that is not included in the second outer peripheral structure 102A, that is, the second wiring electrode exposed portion 72, is exposed to the outside of the semiconductor device 1A.

[0215] Further, in the semiconductor device 1A, as with the semiconductor device 1 according to Embodiment 1, in a plan view of the semiconductor layer 40, the area of the first wiring electrode exposed portion 71 is larger than the area of the first opening portion 61, and the area of the second wiring electrode exposed portion 72 is larger than the area of the second opening portion 62.

[0216] As Figure 14 indicated, the first outer peripheral structure 101A protrudes upward more than the upper surface of the first wiring electrode exposed portion 71, the second outer peripheral structure 102A protrudes upward more than the upper surface of the second wiring electrode exposed portion 72, and the uppermost position of the semiconductor device 1A is present in the first outer peripheral structure 101A and / or the second outer peripheral structure 102A.

[0217] Here, in order to make the first outer peripheral structure 101A protrude more upward than the upper surface of the first wiring electrode exposed portion 71, if the thickness of the first wiring electrode 12 in the first outer peripheral structure 101A is set to a first thickness and the thickness of the second protective film layer 35B in the first outer peripheral structure 101A is set to a second thickness, the second thickness is preferably equal to or less than the first thickness.

[0218] This is because, if the second thickness exceeds the first thickness, the second protective film layer 35B uniformly covers the first wiring electrode 12, and thus it is difficult to form the first outer peripheral structure 101A.

[0219] As the second thickness becomes greater than the first thickness, the tendency of the second protective film layer 35B to uniformly cover the first wiring electrode 12 increases. Therefore, it is preferable that at least the second thickness be equal to or less than the first thickness.

[0220] Similarly, in order to make the second outer peripheral structure 102A protrude more upward than the upper surface of the second wiring electrode exposed portion 72, if the thickness of the second wiring electrode 52 in the second outer peripheral structure 102A is set to a third thickness and the thickness of the second protective film layer 35B in the second outer peripheral structure 102A is set to a fourth thickness, the fourth thickness is preferably equal to or less than the third thickness.

[0221] On the other hand, the inventors and the like repeatedly conducted experiments and research on the height of the first outer peripheral structure 101A with reference to the upper surface of the first wiring electrode exposed portion 71 and the height of the second outer peripheral structure 102A with reference to the upper surface of the second wiring electrode exposed portion 72, which are required in order to make the first outer peripheral structure 101A and the second outer peripheral structure 102A sufficiently sink into resin in the case where the semiconductor device 1A is resin-sealed in a mounting substrate and mounted in a face-up manner. As a result, the inventors and the like obtained the following insight: if the height of the first outer peripheral structure 101A with reference to the upper surface of the first wiring electrode exposed portion 71 is 50% of the thickness of the first wiring electrode 12 at the first opening portion 61 and the height of the second outer peripheral structure 102A with reference to the upper surface of the second wiring electrode exposed portion 72 is 50% of the thickness of the second wiring electrode 52 at the second opening portion 62, the first outer peripheral structure 101A and the second outer peripheral structure 102A can be made to sufficiently sink into resin.

[0222] Here, making the first outer peripheral structure 101A and the second outer peripheral structure 102A sufficiently sink into resin means making the first outer peripheral structure 101A and the second outer peripheral structure 102A that sink into resin sink to the extent of functioning as an anchor that fixes the position of the semiconductor device 1A in resin.

[0223] That is, the inventors discovered through experiments and research that in order to enhance the embedding of the first peripheral structure 101A into the resin, if there is an embedding amount of more than 10% relative to the thickness of the resin, it is effective in obtaining a stable and firm anchoring effect.

[0224] As will be described later, the thickness of the first wiring electrode 12 must have sufficient margin for subsequent processes such as laser processing to open the resin. Therefore, the thickness of the first wiring electrode 12 is required to be at least one-third of the thickness of the resin sealed directly above it.

[0225] Therefore, the desired embedment amount (the height of the first peripheral structure 101A based on the upper surface of the first wiring electrode exposed portion 71 and the height of the second peripheral structure 102A based on the upper surface of the second wiring electrode exposed portion 72) is at least 30% or more of the thickness of the first wiring electrode 12. However, in this invention, in order to obtain a more stable and firm anchoring effect, it is set to be at least 50% of the thickness of the first wiring electrode 12.

[0226] Furthermore, the inventors have realized that if the height of the first peripheral structure 101A, based on the upper surface of the first wiring electrode exposed portion 71, is 50% of the thickness of the first wiring electrode 12 at the first opening portion 61, and the height of the second peripheral structure 102A, based on the upper surface of the second wiring electrode exposed portion 72, is 50% of the thickness of the second wiring electrode 52 at the second opening portion 62, then a protrusion reflecting the first peripheral structure 101A and the second peripheral structure 102A is formed on the upper surface of the resin cured after the semiconductor device 1A is encapsulated.

[0227] Therefore, the inventors have defined the semiconductor device 1A as having a second thickness that is greater than half the first thickness but less than or equal to the first thickness, and a fourth thickness that is greater than half the third thickness but less than or equal to the third thickness.

[0228] However, the second protective film layer 35B is typically formed of a viscous polyimide. Therefore, when it is desired to form the second protective film layer 35B on a portion of a structure having a height difference, such as the first peripheral structure 101A and the second peripheral structure 102A, the polyimide on the upper side of the height difference flows to the lower side of the height difference, thus sometimes making it impossible to form the second protective film layer 35B of the desired shape.

[0229] Therefore, the inventors repeatedly conducted experiments and research on the shape of the second protective film layer 35B and the shapes of the first outer peripheral structure 101A and the second outer peripheral structure 102A, which enable the suppression of the flow of polyimide on the upper side of the step to the lower side of the step when the first outer peripheral structure 101A and the second outer peripheral structure 102A are formed. As a result, the inventors obtained the following insight: if the minimum width of the portion of the second protective film layer 35B that overlaps the first wiring electrode 12 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, then the flow of polyimide on the upper side of the step to the lower side of the step can be suppressed when the first outer peripheral structure 101A is formed, and if the minimum width of the portion of the second protective film layer 35B that overlaps the second wiring electrode 52 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, then the flow of polyimide on the upper side of the step to the lower side of the step can be suppressed when the second outer peripheral structure 102A is formed.

[0230] Therefore, with respect to the semiconductor device 1A, the inventors believe that the minimum width of the portion of the second protective film layer 35B that overlaps the first wiring electrode 12 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, and the minimum width of the portion of the second protective film layer 35B that overlaps the second wiring electrode 52 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40.

[0231] <Investigation>

[0232] The semiconductor device 1A according to the above-described structure, like the case of the semiconductor device 1 according to Embodiment 1, in the case where the semiconductor device 1A is resin-sealed in a mounting substrate and mounted in a face-up manner, the first outer peripheral structure 101A and the second outer peripheral structure 102A are recessed in the resin on the upper surface of the semiconductor device 1A.

[0233] Therefore, the first outer peripheral structure 101A and the second outer peripheral structure 102A that are recessed in the resin function as anchors that fix the position of the semiconductor device 1A in the resin, and as a result, the suppression of resin peeling in the mounting substrate and the stabilization of the position of the semiconductor device 1A inside the mounting substrate are achieved.

[0234] In addition, as with the semiconductor device 1 according to Embodiment 1, a protrusion reflecting the first outer peripheral structure 101A and the second outer peripheral structure 102A is formed on the upper surface of the resin into which the semiconductor device 1A is enclosed.

[0235] Therefore, in the case of processing the resin to form a hole reaching the first wiring electrode exposure portion 71 from the upper surface of the resin, the protrusion corresponding to the first outer peripheral structure 101A formed on the upper surface of the resin is used as a guide line, and processing is performed to form a hole inside the protrusion, whereby the processing to form a hole reaching the first wiring electrode exposure portion 71 from the upper surface of the resin can be performed with higher precision than in the case where the protrusion is not present.

[0236] Furthermore, as with the semiconductor device 1 according to Embodiment 1, in the case of processing the resin to form a hole reaching the second wiring electrode exposure portion 72 from the upper surface of the resin, the protrusion corresponding to the second outer peripheral structure 102A formed on the upper surface of the resin is used as a guide line, and processing is performed to form a hole inside the protrusion, whereby the processing to form a hole reaching the second wiring electrode exposure portion 72 from the upper surface of the resin can be performed with higher precision than in the case where the protrusion is not present.

[0237] Thus, the semiconductor device 1A according to the above-described structure, as with the semiconductor device 1 according to Embodiment 1, provides a semiconductor device having a configuration suitable for mounting by being buried in a mounting substrate.

[0238] As described above, in the plan view of the semiconductor layer 40, the area of the first wiring electrode exposure portion 71 is larger than the area of the first opening portion 61, and the area of the second wiring electrode exposure portion 72 is larger than the area of the second opening portion 62.

[0239] Thus, as with the semiconductor device 1 according to Embodiment 1, in the plan view of the semiconductor layer 40, the area of the first wiring electrode exposure portion 71 is larger than the area of the first opening portion 61, and the area of the second wiring electrode exposure portion 72 is larger than the area of the second opening portion 62.

[0240] In addition, as with the semiconductor device 1 according to Embodiment 1, in the semiconductor device 1A, S1 / M1 is preferably 0.5 or greater, that is, S1 / M1 is preferably 0.5 or greater and less than 1.0, and further, in the semiconductor device 1A, S1 / M1 is more preferably 0.9 or greater and less than 1.0, and P1 / M1 is more preferably 0.9 or greater and 1.1 or less.

[0241] Also in the semiconductor device 1A, as with the case of the semiconductor device 1 according to Embodiment 1, it is effective that P2 / M2 be 0.9 or greater and 1.1 or less.

[0242] Also in the semiconductor device 1A, as with the case of the semiconductor device 1 according to Embodiment 1, it can be said that P2 / S2 is preferably greater than or equal to 1.27.

[0243] Also in the semiconductor device 1A, as with the case of the semiconductor device 1 according to Embodiment 1, in the plan view of the semiconductor layer 40, the shape of the first wiring electrode 12 and the shape of the second wiring electrode 52 are made line-symmetrical with a center line as the axis of symmetry, and the center line becomes a shape that bisects the semiconductor device 1A in area, whereby the semiconductor device 1A can achieve a preferable shape in terms of making the first wiring electrode exposed portion 71 connect to an external wiring of the semiconductor device 1A via a hole opened in a resin that seals the semiconductor device 1A, and making the second wiring electrode exposed portion 72 connect to an external wiring of the semiconductor device 1A via a hole opened in a resin that seals the semiconductor device 1A.

[0244] Further, in Embodiment 2, it was explained that the protective film 35 is a two-layer structure in which the first protective film layer 35A and the second protective film layer 35B are laminated, but the protective film 35 can also be a multilayer structure in which three or more layers are laminated.

[0245] Figure 15 is an enlarged cross-sectional view that shows an example of the configuration of the first outer peripheral configuration 101A in the case where the protective film 35 has a three-layer structure.

[0246] As Figure 15 shown, in the case where the protective film 35 has a three-layer structure, in addition to the first protective film layer 35A and the second protective film layer 35B, a third protective film layer 35C can also be laminated between the first protective film layer 35A and the second protective film layer 35B.

[0247] Further, it should be noted that the logic discussed in the item of <Consideration> in Embodiment 2 can not hold in the case where the thicknesses of the first wiring electrode 12 and the second wiring electrode 52 are thinner than 10 μm.

[0248] (Embodiment 3)

[0249] The following describes a semiconductor device (hereinafter also referred to as "mounting semiconductor device") of the same structure as the semiconductor device 1 or semiconductor device 1A of Embodiment 1 or Embodiment 2, or the first wiring electrode 12, second wiring electrode 52, and protective film 35, mounted in the mounting substrate of Embodiment 3 in a face-up manner.

[0250] Here, regarding the mounting substrate of Embodiment 3, the structure elements of the semiconductor device 1 are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted.

[0251] Further, in Embodiment 3, the case where the semiconductor device mounted by the mounting substrate of Embodiment 3 is the semiconductor device 1 is described, but the case where the semiconductor device mounted by the mounting substrate of Embodiment 3 is the semiconductor device 1A or the mounting semiconductor device is the same.

[0252] Figure 16 is a plan view showing one example of the configuration of the mounting substrate 70 of Embodiment 3. As shown in Figure 16 , the mounting substrate 70 has a shape with a long side direction. Here, Figure 16 , the X-axis direction in

[0253] Figure 17 is a cross-sectional view showing one example of the configuration of the mounting substrate 70. Figure 17 shows Figure 16 VI-VI cross section of

[0254] As shown in Figure 16 , Figure 17 , the mounting substrate 70 includes a first wiring layer 76, interlayer insulating layer 78, and second wiring layer 77, and is configured by sequentially stacking the first wiring layer 76, interlayer insulating layer 78, and second wiring layer 77.

[0255] Further, here, the case where the mounting substrate 70 includes two wiring layers of the first wiring layer 76 and second wiring layer 77 as wiring layers is described, but the mounting substrate 70 need not be limited to the structure including two wiring layers of the first wiring layer 76 and second wiring layer 77 as wiring layers.

[0256] As another configuration example, the mounting substrate 70 may, for example, also have a structure including one or more wiring layers on a lower layer side than the first wiring layer 76 and / or on an upper layer side than the second wiring layer 77.

[0257] The mounting substrate 70 also includes the semiconductor device 1, electronic component 81, one or more first connection wiring 91 (here, one), and second connection wiring 92 (here, one) in the interlayer insulating layer 78.Figure 16 , Figure 17 The first connection wiring 91A to the first connection wiring 91D, the four first connection wirings 91A to the first connection wiring 91D, and the second connection wiring 92 are provided in the second wiring layer 77. The first wiring 96 and the second wiring 97 are provided in the second wiring layer 77. The electronic component 82 and the electronic component 83 are provided on the second wiring layer 77.

[0258] Here, the semiconductor device 1 is assumed to be a rectangle with its long side, and the electronic component 83 is assumed to be a rectangle with its long side. Figure 16 The Y-axis direction in the diagram is the direction of the long side of semiconductor device 1. Figure 16 The X-axis direction is the long side direction of electronic component 83.

[0259] In addition, Figure 16 In the illustration, the semiconductor device 1, electronic component 81, one or more first connection wirings 91, second connection wirings 92, first wiring electrode 12, and second wiring electrode 52 are shown as components that can be visually identified by dashed lines, but in reality, these components cannot be visually identified from the outside of the mounting substrate 70.

[0260] The first wiring layer 76 and the second wiring layer 77 are layers for forming wiring, which is used to electrically connect components mounted on the mounting substrate 70 and / or components outside the mounting substrate 70.

[0261] The interlayer insulating layer 78 is an insulating film sandwiched between the first wiring layer 76 and the second wiring layer 77. Here, we will describe the case where the interlayer insulating layer 78 is made of resin.

[0262] Semiconductor device 1 is mounted face-up within interlayer insulating layer 78. At this time, semiconductor device 1 is positioned along its long side (here, the longitudinal direction) in the plan view of mounting substrate 70. Figure 16 The Y-axis direction in the middle) and the long side direction of the mounting base 70 (here) Figure 16 The X-axis direction is perpendicular to each other and they are installed.

[0263] Electronic component 81 is mounted inside interlayer insulation layer 78, and electronic component 82 is mounted on second wiring layer 77.

[0264] Electronic component 83 is mounted on the second wiring layer 77. At this time, in the plan view of the mounting substrate 70, at least a portion of electronic component 83 overlaps with the semiconductor device 1, and the long side direction of electronic component 83 (here, ) Figure 16 The X-axis direction in the diagram) and the long side direction of semiconductor device 1 (here) Figure 16 The Y-axis direction is installed in a mutually orthogonal orientation.

[0265] The first wiring 96 is a wiring formed in the second wiring layer 77, for example, composed of copper, silver, or an alloy thereof.

[0266] The second wiring 97 is a wiring formed in the second wiring layer 77, for example, composed of copper, silver, or an alloy thereof.

[0267] The one or more first connection wirings 91 are each a wiring composed of copper, extending in a direction orthogonal to the mounting substrate 70 (in this case, the Z-axis direction) to connect the first wiring 96 and the upper surface of the first wiring electrode 12 of the semiconductor device 1. Figure 16 、 Figure 17 The one or more first connection wirings 91 are each a wiring composed of copper, extending in a direction orthogonal to the mounting substrate 70 (in this case, the Z-axis direction) to connect the first wiring 96 and the upper surface of the first wiring electrode 12 of the semiconductor device 1.

[0268] The one or more first connection wirings 91 are each connected to the upper surface of the first wiring electrode 12 at a portion in the first wiring electrode 12 that does not overlap the first outer peripheral structure 101 in a plan view of the semiconductor layer 40.

[0269] For example, after the semiconductor device 1 is mounted in the interlayer insulating layer 78 with the face upward, the interlayer insulating layer 78 is subjected to, for example, laser processing to form a hole reaching the upper surface of the first wiring electrode 12 from the upper surface of the interlayer insulating layer 78, and copper is filled in the hole, thereby forming the one or more first connection wirings 91.

[0270] The cross section of each of the one or more first connection wirings 91 orthogonal to the direction in which each of the one or more first connection wirings 91 extends is circular.

[0271] Further, here, it is assumed that the one or more first connection wirings 91 are four, the first connection wirings 91A to 91D, but it is not necessarily limited to four, and can be one or a plurality of more than four.

[0272] The first connection wirings 91 are each a wiring composed of copper, extending in a direction orthogonal to the mounting substrate 70 (in this case, the Z-axis direction) to connect the first wiring 96 and the upper surface of the first wiring electrode 12 of the semiconductor device 1.

[0273] If the one or more first connection wirings 91 are a plurality, even if one of the plurality of first connection wirings 91 is broken, the connection of the first wiring electrode 12 and the first wiring 96 can be maintained by the other one or more first connection wirings 91.

[0274] Further, if the one or more first connection wirings 91 are a plurality, compared to the case where the one or more first connection wirings 91 are one, reduction of the resistance value of the one or more first connection wirings 91 and the efficiency of heat dissipation via the one or more first connection wirings 91 can be improved.

[0275] The second connection wirings 92 are each a wiring composed of copper, extending in a direction orthogonal to the mounting substrate 70 (in this case, the Z-axis direction) to connect the second wiring 97 and the upper surface of the second wiring electrode 52 of the semiconductor device 1. Figure 16 ,Figure 17 The second connection wiring 92 is formed of copper.

[0276] The second connection wiring 92 is connected to the upper surface of the second wiring electrode 52 at a portion in the second wiring electrode 52 that does not overlap the second outer peripheral structure 102 in a plan view of the semiconductor layer 40.

[0277] The second connection wiring 92 is formed, for example, by mounting the semiconductor device 1 with the face upward in the interlayer insulating layer 78, forming a hole reaching the upper surface of the second wiring electrode 52 from the upper surface of the interlayer insulating layer 78 in the interlayer insulating layer 78 by laser processing, for example, and filling copper in the hole.

[0278] In addition, the cross section of at least one of the one or more first connection wirings 91 can also be larger than the cross section of the second connection wiring 92 described later. This is because, in the first vertical MOS transistor 10, the current flowing through the first source electrode 13 is larger than the current flowing through the first gate electrode 19.

[0279] Figure 18 is an enlarged plan view showing one example of the configuration of the mounting substrate 70 in the case where the first wiring electrode 12 provided in the semiconductor device 1 is a plurality of (six in this case, the first wiring electrode 12A to the first wiring electrode 12F).

[0280] In addition, in Figure 18 , the semiconductor device 1, the first wiring electrode 12 (the first wiring electrode 12A to the first wiring electrode 12F in this case), the second wiring electrode 52, the first connection wiring 91 (the first connection wiring 91E to the first connection wiring 91J in this case), the second connection wiring 92, and the like are illustrated as being visually recognizable by the broken lines, but in fact, these constituent elements cannot be visually recognized from the outside of the mounting substrate 70.

[0281] As shown in Figure 18 , in the case where the first wiring electrode 12 provided in the semiconductor device 1 is a plurality of, one or more first connection wirings 91 are a plurality corresponding to each of the plurality of first wiring electrodes 12 in pairs. In this case, each of the plurality of first wiring electrodes 12 is connected to the first wiring 96 through one first connection wiring 91 corresponding to the first wiring electrode 12 in pairs.

[0282] At this time, the cross section of each of the plurality of first connection wirings 91 orthogonal to the direction in which each of the plurality of first connection wirings 91 extends can also be equal to each other.

[0283] Thus, it is possible to make the manufacturing of the mounting substrate 70 relatively easy.

[0284] <Investigation>

[0285] As explained in Embodiment 1, the semiconductor device 1 is a semiconductor device having a configuration suitable for a mounting method of being mounted so as to be buried in the mounting substrate 70.

[0286] Therefore, according to the mounting substrate 70 of the above-described configuration, a mounting substrate of mounting a semiconductor device 1 having a configuration suitable for a mounting method of being mounted so as to be buried in the mounting substrate 70 is provided.

[0287] Further, the same applies to the case where the semiconductor device mounted by the mounting substrate 70 is the semiconductor device 1A and the case where the semiconductor device is a mounting-use semiconductor device.

[0288] As described above, in the plan view of the mounting substrate 70, the mounting substrate 70 has a shape having a long-side direction, the semiconductor device 1 has a shape having a long-side direction, and the long-side direction of the mounting substrate 70 and the long-side direction of the semiconductor device 1 are orthogonal to each other.

[0289] Thus, it is possible to suppress the warping of the mounting substrate 70 and the warping of the semiconductor device 1 from mutually promoting each other at the time of heat treatment in the manufacturing process of the mounting substrate 70.

[0290] Further, as described above, in the plan view of the mounting substrate 70, at least a part of the electronic component 83 overlapping the semiconductor device 1 has a shape having a long-side direction, the semiconductor device 1 has a shape having a long-side direction, and the long-side direction of the electronic component 83 and the long-side direction of the semiconductor device 1 are orthogonal to each other.

[0291] Thus, it is possible to suppress the warping of the electronic component 83 and the warping of the semiconductor device 1 from mutually promoting each other at the time of heat treatment in the manufacturing process of the mounting substrate 70.

[0292] Further, in the mounting substrate 70, the height from the lowest position in the upper surface of the first wiring electrode 12 to the uppermost position of the semiconductor device 1 can also be 15% or more of the length of one or more first connection wirings 91 in the direction orthogonal to the mounting substrate 70.

[0293] The length of the first connection wiring 91 is equal to the thickness of the resin sealed directly above the semiconductor device 1.

[0294] The height from the lowest position in the upper surface of the first wiring electrode 12 to the uppermost position of the semiconductor device 1 is the amount of sinking into the resin, and in the present application, it is assumed that 50% of the thickness of the first wiring electrode 12 is ensured.

[0295] As described above, since the thickness of the first wiring electrode 12 is 1 / 3 or more of the thickness of the resin directly above, a sufficient anchoring effect can be obtained when the amount of sinking is 1 / 3 x 0.5 (50%) = 1 / 6 ≒ 0.15, that is, 15% or more.

[0296] Thus, a protrusion reflecting the first outer peripheral structure 101 is formed on the upper surface of the interlayer insulating layer 78, and during formation of the first connection wiring 91, by laser processing of the mounting substrate 70, the thickness of the first wiring electrode 12 can be sufficiently ensured when forming a hole reaching the upper surface of the first wiring electrode 12 from the upper surface of the interlayer insulating layer 78.

[0297] (Supplement)

[0298] The semiconductor device and the mounting substrate according to one embodiment of the present application have been described above based on Embodiments 1 to 3, but the present application is not limited to these embodiments. As long as the gist of the present application is not deviated from, a mode obtained by applying various modifications that can be thought of by those skilled in the art to these embodiments, a mode constructed by combining the constituent elements in different embodiments can also be included in the scope of one or more modes of the present application.

[0299] [Industrial Applicability]

[0300] The present application can be widely used for semiconductor devices, mounting substrates, and the like.

[0301] Symbol Explanation

[0302] 1, 1A Semiconductor device

[0303] 10 First vertical MOS transistor

[0304] 12, 12A, 12B, 12C, 12D, 12E, 12F First wiring electrode

[0305] 13 First source electrode

[0306] 14 First source region

[0307] 15 First gate conductor

[0308] 16 First gate insulating film

[0309] 18 First body region

[0310] 19 First gate electrode

[0311] 20 Second vertical MOS transistor

[0312] 22 Third wiring electrode

[0313] 23 Second source electrode

[0314] 24 second source region

[0315] 25 second gate conductor

[0316] 26 second gate insulating film

[0317] 28 second body region

[0318] 29 second gate electrode

[0319] 30 metal layer

[0320] 32 semiconductor substrate

[0321] 33 low-concentration impurity layer

[0322] 34 oxide film

[0323] 35 protective film

[0324] 35A first protective film layer

[0325] 35B second protective film layer

[0326] 35C third protective film layer

[0327] 40 semiconductor layer

[0328] 52 second wiring electrode

[0329] 54 fourth wiring electrode

[0330] 61 first opening portion

[0331] 62 second opening portion

[0332] 63 third opening portion

[0333] 64 fourth opening portion

[0334] 70 mounting substrate

[0335] 71 first wiring electrode exposure portion

[0336] 72 second wiring electrode exposure portion

[0337] 76 first wiring layer

[0338] 77 second wiring layer

[0339] 78 interlayer insulating layer

[0340] 81, 82, 83 electronic component

[0341] 91, 91A, 91B, 91C, 91D, 91E, 91F, 91G, 91H, 91I, 91J first connection wiring

[0342] 92 second connection wiring

[0343] 96 first wiring

[0344] 97 second wiring

[0345] 101, 101A first outer peripheral structure

[0346] 102, 102A second outer peripheral structure

[0347] 201 first wall surface

[0348] 202 first tapered region

Claims

1. A semiconductor device, It is a chip-scale packaged semiconductor device that features: Semiconductor layer; A vertical MOS transistor is formed within the semiconductor layer; the vertical MOS transistor is a vertical metal-oxide-semiconductor transistor. The protective film is a protective film covering the upper surface of the vertical MOS transistor, having a first opening that exposes the source electrode of the vertical MOS transistor to the outside of the protective film, and a second opening that exposes the gate electrode of the vertical MOS transistor to the outside of the protective film. A first wiring electrode, connected to the source electrode, is primarily composed of copper and seamlessly covers the exposed portion of the source electrode in the first opening that extends outward from the protective film; and The second wiring electrode, connected to the gate electrode, is primarily composed of copper and seamlessly covers the exposed portion of the gate electrode in the second opening that extends outward from the protective film. In the plan view of the semiconductor layer, the semiconductor device is rectangular. The entire outer periphery of the first opening is sealed by the protective film. The entire outer periphery of the second opening is sealed by the protective film. In the outer peripheral portion of the semiconductor layer in the plan view of the first wiring electrode, a first peripheral structure is formed by sequentially stacking the source electrode, the protective film, and the first wiring electrode. The uppermost layer of the first peripheral structure is the first wiring electrode. In the outer peripheral portion of the semiconductor layer in the plan view of the second wiring electrode, a second peripheral structure is formed, consisting of the gate electrode, the protective film, and the second wiring electrode stacked sequentially. The uppermost layer of the second peripheral structure is the second wiring electrode. The exposed portion of the first wiring electrode, which is the upper surface of the first wiring electrode, is exposed to the outside of the semiconductor device. The exposed portion of the second wiring electrode, which is the upper surface of the second wiring electrode, is exposed to the outside of the semiconductor device. The first peripheral structure protrudes upward from the upper surface of the portion of the first exposed wiring electrode that is not included in the first peripheral structure. The second peripheral structure protrudes upward from the upper surface of the portion of the second exposed wiring electrode that is not included in the second peripheral structure. The uppermost position of the semiconductor device is located in the first peripheral structure and / or the second peripheral structure. In the plan view of the semiconductor layer, the area of ​​the exposed portion of the first wiring electrode is larger than the area of ​​the first opening. In the plan view of the semiconductor layer, the area of ​​the exposed portion of the second wiring electrode is larger than the area of ​​the second opening. The semiconductor device further includes a metal layer formed in contact with the lower surface of the semiconductor layer. The thickness of the metal layer is greater than the maximum thickness of the first wiring electrode. In the outer peripheral portion of the plan view of the semiconductor layer, the first wiring electrode has a wall surface that forms an inverted cone shape towards the outside of the first wiring electrode in the cross-sectional view of the semiconductor layer. The wall surface does not come into contact with the protective film.

2. The semiconductor device according to claim 1, In the plan view of the semiconductor layer, the protective film has a tapered region that tapers towards the first opening in the cross-sectional view. In the plan view of the semiconductor layer, the wall is located inside the conical region.

3. A semiconductor device, It is a chip-scale packaged semiconductor device that features: Semiconductor layer; A vertical MOS transistor is formed within the semiconductor layer; The protective film is a protective film covering the upper surface of the vertical MOS transistor, having a first opening that exposes the source electrode of the vertical MOS transistor to the outside of the protective film, and a second opening that exposes the gate electrode of the vertical MOS transistor to the outside of the protective film. A first wiring electrode, connected to the source electrode, is primarily composed of copper and seamlessly covers the exposed portion of the source electrode in the first opening that extends outward from the protective film; and The second wiring electrode, connected to the gate electrode, is primarily composed of copper and seamlessly covers the exposed portion of the gate electrode in the second opening that extends outward from the protective film. In the plan view of the semiconductor layer, the semiconductor device is rectangular. The entire outer periphery of the first opening is sealed by the protective film. The entire outer periphery of the second opening is sealed by the protective film. The protective film is a multilayer structure consisting of multiple protective film layers, including a first protective film layer and a second protective film layer located above the first protective film layer. In the outer peripheral portion of the semiconductor layer in the plan view of the first wiring electrode, a first peripheral structure is formed by sequentially stacking the source electrode, the first protective film layer, the first wiring electrode, and the second protective film layer. The uppermost layer of the first peripheral structure is the second protective film layer. In the outer peripheral portion of the semiconductor layer in the plan view of the second wiring electrode, a second peripheral structure is formed, consisting of the gate electrode, the first protective film layer, the second wiring electrode, and the second protective film layer stacked sequentially. The uppermost layer of the second peripheral structure is the second protective film layer. The exposed portion of the first wiring electrode, which is a part of the upper surface of the first wiring electrode that is not included in the first peripheral structure, is exposed to the outside of the semiconductor device. The exposed portion of the second wiring electrode, which is a part of the upper surface of the second wiring electrode that is not included in the second outer peripheral structure, is exposed to the outside of the semiconductor device. The first peripheral structure protrudes upwards from the upper surface of the first exposed wiring electrode portion. The second peripheral structure protrudes upwards from the upper surface of the exposed portion of the second wiring electrode. The uppermost position of the semiconductor device is located in the first peripheral structure and / or the second peripheral structure. If the thickness of the first wiring electrode in the first peripheral structure is set as the first thickness, and the thickness of the second protective film layer in the first peripheral structure is set as the second thickness, then the second thickness is less than or equal to the first thickness. In the outer peripheral portion of the plan view of the semiconductor layer, the first wiring electrode has a wall surface that is tapered in shape towards the outside of the first wiring electrode in the cross-sectional view of the semiconductor layer.

4. The semiconductor device according to claim 1 or 3, In the plan view of the semiconductor layer, the wall is formed along the entire length of the outer periphery of the first wiring electrode.

5. The semiconductor device according to claim 1 or 3, In the plan view of the semiconductor layer, the semiconductor device is a rectangle with its long side facing outwards. In the plan view of the semiconductor layer, the wall formed on the outer periphery of the first wiring electrode includes at least a portion of the wall that is orthogonal to the direction of the long side.

6. The semiconductor device according to claim 1 or 3, There are multiple first openings. The first wiring electrode is a plurality of electrodes that correspond in pairs to the plurality of first openings and are the same number as the plurality of first openings.

7. The semiconductor device according to claim 6, In the plan view of the semiconductor layer, the area of ​​the first exposed portion of each of the plurality of first wiring electrodes is larger than the area of ​​the first opening that corresponds to the first wiring electrode in pairs among the plurality of first openings.

8. The semiconductor device according to claim 1 or 3, When the area of ​​the source electrode in the planar view of the semiconductor layer is set to M1 and the area of ​​the first opening in the planar view of the semiconductor layer is set to S1, The first occupancy rate, which is the occupancy of the area of ​​the first opening in the planar view of the semiconductor layer, as represented by S1 / M1, relative to the area of ​​the source electrode in the planar view of the semiconductor layer, is 0.5 or more and less than 1.

0.

9. The semiconductor device according to claim 1 or 3, There are multiple first openings. The first wiring electrode consists of a plurality of electrodes that correspond in pairs to the plurality of first openings, and the number of such electrodes is the same as the number of the plurality of first openings. When the area of ​​the source electrode in the planar view of the semiconductor layer is set to M1, and the total area of ​​the plurality of first openings in the planar view of the semiconductor layer is set to S1, The first occupancy rate, which is the occupancy rate of the total area of ​​the plurality of first openings in the plan view of the semiconductor layer, represented by S1 / M1, relative to the area of ​​the source electrode in the plan view of the semiconductor layer, is 0.5 or more and less than 1.

0.

10. The semiconductor device according to claim 8, The first occupancy rate is 0.9 or higher and less than 1.

0. When the area of ​​the first exposed wiring electrode in the planar view of the semiconductor layer is set to P1, The second occupancy rate, which is the occupancy rate of the area of ​​the first exposed wiring electrode in the plan view of the semiconductor layer, represented by P1 / M1, relative to the area of ​​the source electrode in the plan view of the semiconductor layer, is 0.9 or more and 1.1 or less.

11. The semiconductor device according to claim 9, The first occupancy rate is 0.9 or higher and less than 1.

0. When the total area of ​​the exposed portion of the first wiring electrode of each of the plurality of first wiring electrodes in the planar view of the semiconductor layer is set as P1, The second occupancy rate, which is the occupancy rate of the total area of ​​the first wiring electrode exposed portion of each of the plurality of first wiring electrodes in the plan view of the semiconductor layer, represented by P1 / M1, relative to the area of ​​the source electrode in the plan view of the semiconductor layer, is 0.5 or more and 1.0 or less.

12. A mounting substrate, It is a mounting substrate having a first wiring layer, an interlayer insulating layer, and a second wiring layer stacked sequentially, and having the following features: The semiconductor device of claim 1 or 3 is mounted face-up within the interlayer insulating layer; The first wiring is formed in the second wiring layer; and One or more first connection wirings connect the first wirings to the upper surface of the first wiring electrode and extend in a direction orthogonal to the mounting substrate. The one or more first connection wirings are connected to the portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in the plan view of the semiconductor layer.

13. The mounting substrate according to claim 12, further comprising: The second wiring is formed on the second wiring layer; and A second connection wiring connects the second wiring and the upper surface of the second wiring electrode, extending in a direction orthogonal to the mounting substrate. The second connection wiring connects to the portion of the upper surface of the second wiring electrode that does not overlap with the second peripheral structure in the plan view of the semiconductor layer. The cross-section of each of the more than one first connecting wires orthogonal to the direction in which the more than one first connecting wires extends, and the cross-section of the second connecting wire orthogonal to the direction in which the second connecting wire extends, are circular. The cross-section of at least one of the more than one first connection wirings is larger than the cross-section of the second connection wiring.

14. The mounting substrate according to claim 12, The one or more first connection wirings can be multiple.

15. The mounting substrate according to claim 12, The height from the lowest position on the upper surface of the first wiring electrode to the topmost position of the semiconductor device is at least 15% of the length of the one or more first connection wirings in a direction orthogonal to the mounting substrate.

16. The mounting substrate according to claim 12, The first wiring electrode is multiple. The one or more first connection wirings are multiple first wiring electrodes that correspond in pairs to each of the plurality of first wiring electrodes. Each of the plurality of first connection wires is connected to the first wire through one of the plurality of first wire electrodes that are paired with the first connection wire. The cross-sections of each of the plurality of first connecting wires, which are orthogonal to the direction in which each of the plurality of first connecting wires extends, are equal to each other.

17. The mounting substrate according to claim 12, In the plan view of the mounting substrate, The mounting base plate has a shape with its long side facing outwards. The semiconductor device has a shape with its long side facing outwards. The long side direction of the mounting substrate is orthogonal to the long side direction of the semiconductor device.

18. The mounting substrate according to claim 12, It also includes electronic components positioned above the interlayer insulating layer. In the plan view of the mounting substrate, The electronic component has a shape with its long side facing outwards. The semiconductor device has a shape with its long side facing outwards. At least a portion of the electronic component overlaps with the semiconductor device. The long side direction of the electronic component is orthogonal to the long side direction of the semiconductor device.

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