Coaccelerator-based polynomial modular multiplication efficient calculation method and device

Abstract

The invention provides an efficient calculation method and device for polynomial modular multiplication based on a coaccelerator, and the method comprises the steps: obtaining an original polynomial pair, adjusting the coefficient of each original polynomial in a preset modulus range into a format for number theory transformation, and obtaining a preprocessed polynomial; the time domain coefficient of the preprocessed polynomial is converted into frequency domain representation by executing NTT transformation, and polynomial frequency domain representation is obtained; loading the polynomial frequency domain representation from a memory, and carrying out element-by-element dot multiplication on the polynomial frequency domain representation in parallel by a plurality of processing units in the co-accelerator; reading the point multiplication result, and performing NTT (inverse number theory) transformation on the point multiplication result to convert the frequency domain data into time domain representation so as to obtain polynomial time domain representation; and the processor adjusts the polynomial time domain representation to obtain a polynomial modular multiplication result of the original polynomial pair.

Description

Technical Field

[0001] The present invention relates to the field of privacy computing technology in the computer field, and in particular to an efficient computing method, device, electronic device, computer-readable storage medium and computer program product of polynomial modular multiplication based on a co-accelerator. Background Art

[0002] In privacy computing, number theoretic transformation (NTT) operations are often used in homomorphic encryption, secure multi-party computing, and privacy-preserving machine learning algorithms. These application scenarios require joint analysis and computation of data without leaking each other’s data.

[0003] The principle of time-domain polynomial multiplication in the prior art is to directly calculate the product between the polynomial coefficients and accumulate them. The polynomials P(x) and Q(x) represent encrypted data or features in privacy computing. These polynomials are transformed to the number theory domain through NTT, so that effective mathematical operations can be performed even in the encrypted state. For two polynomials A(x) and B(x), the coefficient c of their product C(x) is k It can be expressed as: The computational complexity is O(n 2 ). Its implementation is simple and suitable for small-scale operations. For large-scale polynomial operations, the computational efficiency is low. For this reason, the number theoretic transformation (NTT) converts the polynomial to the number theory domain for point multiplication, and then converts it back to the time domain through the inverse NTT. The computational complexity is O(nlogn).

[0004] C(x)=INTT(NTT(A(x)).NTT(B(x)))

[0005] Although number theoretic transforms (NTT) are efficient, especially in the context of modular operations, their implementation is complex and requires specific choices of moduli and primitive roots.

[0006] Hardware acceleration and parallel computing use the parallel processing capabilities of modern hardware, such as the single instruction multiple data (SIMD) architecture, to accelerate computing. SIMD can perform the same operation on multiple data at the same time, thereby significantly improving computing speed and the performance of large-scale and high-complexity operations. It requires optimized design for specific hardware, which increases implementation complexity.

[0007] In summary, the above technology has the following technical defects:

[0008] Time-domain polynomial multiplication has low computational efficiency and high computational complexity, making it difficult to perform well in large-scale operations. It also lacks parallel processing and cannot effectively utilize the parallel processing capabilities of modern hardware. Number theoretic transform (NTT) is complex to implement. NTT requires specific moduli and primitive roots, which are complex to select and optimize. In addition, hardware acceleration is limited in its use. Traditional NTT implementations have not fully utilized the parallel processing capabilities of hardware accelerators, especially the SIMD architecture. Hardware acceleration and parallel computing optimization and implementation are complex. Using hardware accelerators for operations requires specialized optimization and implementation, and has limited versatility. It needs to be optimized for specific hardware and is difficult to use in different computing environments.

[0009] In view of the above technical defects, the present invention fully utilizes the parallel processing capability of modern hardware architecture (especially SIMD) to accelerate polynomial modular multiplication operations during the calculation process of NTT. Summary of the invention

[0010] There are significant performance bottlenecks in the existing technologies when processing large-scale and high-complexity polynomial operations, which are as follows: 1. Low computational efficiency: Traditional time-domain polynomial multiplication cannot meet the needs of large-scale operations in terms of computational complexity. 2. Inadequate use of hardware acceleration capabilities: Existing NTT implementations do not fully utilize the parallel processing capabilities of modern hardware architectures (such as Hwacha SIMD). 3. Low data transmission efficiency: Data exchange between NTT operations and hardware acceleration modules has not been effectively optimized, affecting overall performance.

[0011] The present invention aims to solve the above-mentioned problems of the prior art by proposing an efficient calculation method and system for polynomial modular multiplication combining the Hwacha SIMD architecture and NTT, thereby significantly improving the efficiency and performance of polynomial modular multiplication operations, especially in the application scenarios of privacy computing and cryptography. The present invention can significantly reduce the calculation time of polynomial multiplication through the combination of SIMD and NTT, thereby speeding up the data processing speed in privacy computing. Improve security: The efficient calculation method can ensure the security and stability of the operation when processing large-scale encrypted data. Strong adaptability: This method is not only suitable for privacy computing, but can also be widely used in other fields that require efficient polynomial operations, such as cryptography, digital signatures, etc.

[0012] In view of the shortcomings of existing technologies, such as Figure 3 As shown, the present invention proposes an efficient calculation method for polynomial modular multiplication based on a co-accelerator, which includes:

[0013] In a preprocessing step, the processor obtains the original polynomial pair to be subjected to polynomial modular multiplication from the memory, adjusts the coefficients of each original polynomial to a format for number-theoretic transformation within a predetermined modulus range, obtains a preprocessed polynomial, and writes it back to the memory;

[0014] In the forward transformation step, the number theory transformation unit reads the preprocessing polynomial pair, and converts the time domain coefficients of the preprocessing polynomial into the frequency domain representation by performing the forward number theory transformation NTT transformation, obtains the frequency domain representation of the polynomial and writes it back to the memory;

[0015] In the dot multiplication step, the processor starts and controls the co-accelerator to load the frequency domain representation of the polynomial from the memory, and multiple processing units in the co-accelerator perform element-by-element dot multiplication on the frequency domain representation of the polynomial in parallel, and the dot multiplication result is stored back to the memory;

[0016] Inverse transformation step, the processor schedules and controls the number theory transformation unit to read the point multiplication result and perform an inverse number theory transformation NTT transformation on it to convert the frequency domain data into a time domain representation to obtain a polynomial time domain representation;

[0017] In the result processing step, the processor adjusts the time domain representation of the polynomial to obtain the polynomial modular multiplication result of the original polynomial pair.

[0018] The efficient calculation method of polynomial modular multiplication based on the co-accelerator, wherein the point multiplication step includes:

[0019] The coefficient operation of the polynomial is distributed to multiple processing units in the co-accelerator, and the processing unit includes a vector register and an arithmetic logic unit ALU. The same operation is performed on multiple processing units simultaneously through a single instruction multiple data stream SIMD instruction, thereby realizing parallel processing of the dot multiplication operation.

[0020] The efficient calculation method of polynomial modular multiplication based on the co-accelerator, wherein when the number theory transformation unit and the co-accelerator interact with each other, the multi-channel memory access of the co-accelerator is utilized to accelerate the loading and storage of data; the data transmission overhead is reduced by loop unrolling and vectorization; and the number of data transmissions from the memory to the co-accelerator is reduced by a cache mechanism.

[0021] The efficient calculation method of polynomial modular multiplication based on the co-accelerator, wherein the result processing step includes:

[0022] Format adjustment: converting the polynomial time domain representation into a preset format, and combining the results of multiple stages or multiple data blocks involved in the polynomial multiplication to obtain the polynomial modular multiplication result.

[0023] like Figure 4 As shown, the present invention also proposes an efficient computing device for polynomial modular multiplication based on a co-accelerator, which includes:

[0024] In the preprocessing module, the processor obtains the original polynomial pair to be subjected to polynomial modular multiplication from the memory, adjusts the coefficients of each original polynomial to a format for number-theoretic transformation within a predetermined modulus range, obtains the preprocessing polynomial, and writes it back to the memory;

[0025] The forward transformation module, the number theory transformation unit reads the preprocessing polynomial pair, converts the time domain coefficients of the preprocessing polynomial into the frequency domain representation by performing the forward number theory transformation NTT transformation, obtains the polynomial frequency domain representation and writes it back to the memory;

[0026] A dot multiplication module, in which the processor starts and controls the co-accelerator to load the frequency domain representation of the polynomial from the memory, and multiple processing units in the co-accelerator perform element-by-element dot multiplication on the frequency domain representation of the polynomial in parallel, and the dot multiplication result is stored back to the memory;

[0027] An inverse transformation module, wherein the processor schedules and controls the number theory transformation unit to read the point multiplication result and perform an inverse number theory transformation NTT transformation on it to convert the frequency domain data into a time domain representation to obtain a polynomial time domain representation;

[0028] The result processing module adjusts the time domain representation of the polynomial to obtain the polynomial modular multiplication result of the original polynomial pair.

[0029] The efficient computing device for polynomial modular multiplication based on the co-accelerator, wherein the dot multiplication module comprises:

[0030] The coefficient operation of the polynomial is distributed to multiple processing units in the co-accelerator, and the processing unit includes a vector register and an arithmetic logic unit ALU. The same operation is performed on multiple processing units simultaneously through a single instruction multiple data stream SIMD instruction, thereby realizing parallel processing of the dot multiplication operation.

[0031] The efficient computing device for polynomial modular multiplication based on a co-accelerator, wherein when the number theory transformation unit and the co-accelerator interact with each other, the co-accelerator's multi-channel memory access is used to accelerate data loading and storage; the data transmission overhead is reduced by loop unrolling and vectorization; and the number of data transmissions from the memory to the co-accelerator is reduced by a cache mechanism;

[0032] The result processing module includes:

[0033] Format adjustment: converting the polynomial time domain representation into a preset format, and combining the results of multiple stages or multiple data blocks involved in the polynomial multiplication to obtain the polynomial modular multiplication result.

[0034] The present invention also proposes an electronic device, which includes the above-mentioned efficient computing device for polynomial modular multiplication based on a co-accelerator. The electronic device may be connected to an information display device, and the information display device is used to display the polynomial modular multiplication result according to display parameters and attributes set by the user or through an artificial intelligence model.

[0035] The present invention also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the efficient calculation method of polynomial modular multiplication based on a co-accelerator are implemented.

[0036] The present invention also proposes a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the efficient calculation method of polynomial modular multiplication based on a co-accelerator are implemented.

[0037] It can be seen from the above scheme that the advantages of the present invention are:

[0038] 1. Significantly improve computing efficiency:

[0039] By utilizing the parallel processing capabilities of the Hwacha SIMD architecture, the point multiplication operations in NTT are greatly accelerated, which significantly improves the efficiency of the overall polynomial modular multiplication operations.

[0040] 2. Improve system performance and processing capabilities:

[0041] The method of the present invention fully utilizes the performance potential of modern hardware, especially the parallel processing capability of the Hwacha SIMD architecture, so that the performance and processing capability of the system are greatly improved when processing highly complex computing tasks.

[0042] 3. Optimize resource utilization:

[0043] Through efficient data transmission and calculation process design, the data transmission time and resource consumption between different modules are reduced, thereby optimizing the resource utilization of the system. Compared with traditional methods, the present invention is more economical in resource consumption and can handle larger-scale computing tasks under the same hardware conditions.

[0044] 4. Strong adaptability and wide application:

[0045] This method is not only suitable for polynomial modular multiplication operations in privacy computing and cryptography, but can also be widely used in other fields that require efficient polynomial operations, such as signal processing, coding theory, etc. Its optimized parallel computing capability enables it to perform well in a variety of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is the overall flow chart of the present invention;

[0047] Figure 2 This is a hardware implementation architecture diagram of the present invention;

[0048] Figure 3 is a flow chart of the method of the present invention;

[0049] Figure 4It is a module diagram of the device of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of a first electronic device of the present invention;

[0051] Figure 6 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0052] Figure 7 It is a schematic diagram of the structure of a second electronic device of the present invention.

[0053] Reference numerals:

[0054] A-First electronic device;

[0055] An efficient computing device for modular multiplication of B-polynomials;

[0056] C-data acquisition equipment;

[0057] D-information display device;

[0058] 1000 - second electronic device;

[0059] Ⅰ-computational unit;

[0060] II-ROM;

[0061] III-RAM;

[0062] IV-bus;

[0063] V-interface;

[0064] VI - input unit;

[0065] VII-output unit;

[0066] VIII- Storage medium;

[0067] Ⅸ-Communication unit. DETAILED DESCRIPTION

[0068] It should be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0069] Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0070] The processor described in the present invention is the control center of the electronic device, which can be a processor or a general term for multiple processing elements. For example, it can be one or more central processing units (CPUs), or application specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs).

[0071] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0072] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smart phones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0073] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0074] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0075] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0076] It should also be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0077] In the present invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0078] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0079] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0080] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0082] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0083] When calculating polynomial modular multiplication for privacy calculation, the inventors noticed that the current polynomial modular multiplication method has significant limitations in performance and efficiency, especially in application scenarios of large-scale and high-complexity calculations. These limitations are mainly manifested in the following two aspects:

[0084] First, the computational complexity of time domain polynomial multiplication is O(n 2 ), which is inefficient for large-scale polynomial operations. It is difficult to fully utilize the parallel processing capabilities of modern hardware and cannot meet the needs of efficient computing.

[0085] Second, although NTT is highly efficient in modular computing environments, its potential for acceleration using modern hardware has not been fully explored. Existing NTT implementations often fail to fully utilize the parallel processing capabilities of hardware accelerators, especially on SIMD architectures. In large-scale polynomial operations, the dot multiplication operation of NTT is a performance bottleneck, affecting the efficiency of the overall calculation.

[0086] When studying how to use modern hardware to improve the efficiency of polynomial modular multiplication operations, the inventors of the present invention found that the point multiplication operation in NTT is the key performance bottleneck in the entire operation process. As an advanced parallel processing architecture, the Hwacha SIMD architecture can be used as a coprocessor of the RISCV CPU, performing the same operation on multiple data at the same time, and has significant parallel processing capabilities. It should be noted that the present invention is not limited to the Hwacha SIMD architecture. The Hwacha SIMD architecture is only used as a specific embodiment. The technical solution of this application can be applied to any SIMD architecture with a coprocessor. This means that as long as the hardware platform supports the SIMD instruction set and can achieve parallel processing, the method of this application can be applied. . The inventors of the present invention believe that how to efficiently map the point multiplication operation of NTT to the Hwacha SIMD architecture and make full use of its parallel processing capabilities is the key to achieving efficient polynomial modular multiplication operations. The solution to these problems will be able to significantly improve the efficiency of NTT operations and give full play to the computing potential of modern hardware.

[0087] In order to solve the above problems, the present invention overcomes the following technical difficulties:

[0088] First, the combination of data parallel processing and Hwacha SIMD architecture. NTT's point multiplication operations need to be performed in the field of number theory. In this environment, to efficiently map these operations to the Hwacha SIMD architecture, a deep understanding of the Hwacha SIMD instruction set and data processing methods is required. A method needs to be designed so that point multiplication operations can be performed in parallel on the Hwacha SIMD architecture, thereby significantly improving the calculation speed.

[0089] Second, the optimization of data transmission and computing processes. Efficient data transmission between the Hwacha SIMD module and the NTT computing module is a key challenge, and it is necessary to ensure the efficiency of data transmission and the continuity of computing. The computing process needs to be designed and optimized to maximize the parallel processing capabilities of the Hwacha SIMD architecture and reduce the overhead of data transmission.

[0090] Third, parallel improvement of the NTT algorithm. The existing NTT algorithm needs to be improved to adapt to and fully utilize the parallel processing characteristics of the Hwacha SIMD architecture. In the point multiplication stage, how to assign the coefficient operations of the polynomial to multiple processing units of the Hwacha SIMD architecture is a technical difficulty that needs to be solved.

[0091] In order to overcome the above technical difficulties, the inventors of the present invention proposed a solution to combine the point multiplication operation in NTT with the Hwacha SIMD architecture. The specific technical points are as follows:

[0092] Technical Points 1. Analyze the characteristics of NTT point multiplication operations. By analyzing the point multiplication steps in NTT operations in detail, determine the calculation parts suitable for parallel processing. Identify that the point multiplication operation can be accelerated in parallel through the Hwacha SIMD architecture, thereby significantly improving the operation efficiency.

[0093] Technical Point 2: Design a Hwacha SIMD-based NTT dot multiplication method. Based on the instruction set and parallel processing characteristics of Hwacha SIMD, an efficient dot multiplication method is designed. In this method, the coefficient calculation of the polynomial is distributed to multiple processing units of Hwacha SIMD, and parallel calculation is performed simultaneously.

[0094] Technical Point 3: Optimize data transmission and computing processes. Design an efficient data transmission mechanism to ensure rapid and seamless data exchange between the NTT computing module and the Hwacha SIMD module. Optimize the computing process, reduce the time overhead of data transmission, and improve the efficiency of overall computing.

[0095] In order to achieve rapid and seamless exchange between NTT and SIMD, the following measures can be taken: Hardware support: Utilize the characteristics of SIMD hardware, such as multi-channel memory access, to accelerate data loading and storage; Software optimization: Reduce data transmission overhead through software-level optimization, such as loop unrolling and vectorization; Cache optimization: Rationally use the cache mechanism to reduce the number of data transmissions from main memory to SIMD processing units.

[0096] The present invention implements this method on the Hwacha SIMD architecture and verifies its performance through actual polynomial modular multiplication operation tests. Through performance testing and comparison, it is proved that the efficiency of this method in large-scale polynomial operations is improved.

[0097] In order to make the above features and effects of the present invention more clearly and understandably described, embodiments are given below and described in detail with reference to the accompanying drawings. This specification discloses one or more embodiments that include the features of the present invention. The disclosed embodiments are only for illustration. The scope of protection of the present invention is not limited to the disclosed embodiments, and the present invention is defined by the attached claims.

[0098] This paper proposes an efficient computing method and system for realizing efficient polynomial modular multiplication by accelerating NTT (Number Theoretic Transform) using the Hwacha SIMD architecture. By mapping the point multiplication operation in NTT to the Hwacha SIMD architecture, optimizing data transmission and computing processes, the efficient computing efficiency of polynomial modular multiplication is significantly improved, which is particularly suitable for large-scale computing scenarios in privacy computing and cryptography applications.

[0099] Overall technical solution

[0100] like Figure 1 , Figure 2 As shown, Figure 2 The horizontal line in the middle represents the system bus. The overall technical solution of the present invention includes the following main steps:

[0101] Step 1. Preprocessing: Adjust the coefficients of the input polynomials P(x) and Q(x) to a format suitable for NTT transformation and ensure that they are within the predetermined modulus range. Data flow: The data of the input polynomial is read from the memory (MEM), preprocessed by the RISC-V CPU, and the adjusted coefficients are stored back to the memory.

[0102] Adjusting the coefficients to a format suitable for NTT transformation may include the following according to the actual situation: 1. Modulus adjustment: Ensure that the coefficients of the polynomial are within the predetermined modulus range. This is because NTT is performed on the field of number theory, and all operations need to be completed under this modulus. 2. Coefficient alignment: The coefficients of the polynomial may need to be padded or truncated to ensure that their length meets the requirements of the NTT algorithm. This usually involves adjusting the length of the polynomial to a power of 2, because the FFT and NTT algorithms are most efficient at this length. 3. Coefficient range adjustment: In some cases, the coefficients may need to be scaled to avoid overflow during the NTT transformation. For example: In polynomial multiplication in privacy computing, there are two polynomials P(x)P(x) and Q(x)Q(x), which represent encrypted data, and their product R(x)=P(x)·Q(x)R(x)=P(x)·Q(x) needs to be calculated without leaking their respective data.

[0103] Polynomial examples, such as when:

[0104] P(x)=3x3+2x2+4x+1P(x)=3x3+2x2+4x+1

[0105] Q(x)=5x3+6x2+2x+7Q(x)=5x3+6x2+2x+7

[0106] Pre-processing steps may include:

[0107] 1. Modulus adjustment: select a suitable modulus mm, such as m=13m=13 (in privacy computing, the choice of modulus is usually related to the encryption scheme);

[0108] 2. Coefficient alignment: Make sure the length of the polynomial is a power of 2. Here, we can pad the polynomial to a length of 4 (because 22=422=4): P(x)=3x3+2x2+4x+1P(x)=3x3+2x2+4x+1Q(x)=5x3+6x2+2x+7Q(x)=5x3+6x2+2x+7After padding (assuming padding with 0s):

[0109] P(x)=3x3+2x2+4x+1+0x4P(x)=3x3+2x2+4x+1+0x4;

[0110] Q(x)=5x3+6x2+2x+7+0x4Q(x)=5x3+6x2+2x+7+0x4;

[0111] 3. Coefficient range adjustment: Adjust the coefficients to within the modulus mm range. For P(x)P(x) and Q(x)Q(x), all coefficients are already less than 13, so no further adjustment is required.

[0112] Step 2. Forward NTT transform: The NTT unit is a separate module dedicated to processing NTT operations and is a separate IP. The NTT unit is used to convert the polynomial from the time domain to the frequency domain. Data flow: The preprocessed polynomial data is read from the memory (MEM) to the NTT unit. The NTT unit performs a forward NTT transform, converting the time domain coefficients into a frequency domain representation through discrete Fourier transform (DFT) or variant fast Fourier transform (FFT), and stores the results back to the memory. The RISC-V CPU is responsible for directing and scheduling the operations of the NTT unit.

[0113] Step 3: Dot multiplication stage: In the frequency domain, the Hwacha SIMD accelerator is used to perform element-by-element dot multiplication on the frequency domain representation of the transformed polynomial. Data flow: The frequency domain data after NTT transformation is loaded from the memory to the Hwacha SIMD accelerator. The Hwacha SIMD processes this data in parallel and performs the dot multiplication operation. The dot multiplication result is stored back to the memory for subsequent inverse transformation. The RISC-V CPU is responsible for starting and controlling the operation of the Hwacha SIMD to ensure the smooth progress of the dot multiplication process.

[0114] Step 4: Inverse INTT Transform: Use inverse NTT (INTT) to convert the frequency domain result after dot multiplication back to the time domain and restore the polynomial coefficients. Data flow: The frequency domain result after dot multiplication is read from the memory to the NTT unit. The NTT unit performs the inverse NTT transform to convert the frequency domain data back to the time domain representation. The time domain result after INTT transform is stored back to the memory. The RISC-V CPU schedules and controls the inverse NTT process to ensure the correctness of the time domain recovery.

[0115] Step 5: Result processing: Process the time domain result after the inverse NTT transformation and output the final polynomial modular multiplication result. Data flow: The time domain data after the INTT transformation is read from the memory to the RISC-V CPU for post-processing. After the RISC-V CPU makes necessary adjustments and formatting, it stores the final result back to the memory or directly outputs it for use. During the whole process, the data flows between the memory and each processing unit, and the final result is processed by the RISC-V CPU and output.

[0116] Adjustments and formatting include:

[0117] Formatting and merging. Formatting: This may involve converting data from one format to another, such as from binary to hexadecimal or from floating point to integer. Merging: If the polynomial multiplication involves multiple stages or multiple blocks of data, you may need to merge the results of these stages or blocks of data. For example, if a divide-and-conquer strategy is used, you may need to merge the solutions to the subproblems into the final solution.

[0118] Result processing: Process the time domain data obtained after the inverse NTT transform to conform to the final output format or meet specific application requirements, including:

[0119] Modulus Adjustment: Ensures that the result is within the predetermined modulus range.

[0120] Coefficient Formatting: Convert coefficients to a format suitable for output or further processing.

[0121] Result merging: If there are multiple intermediate results in the calculation process, they need to be merged into the final result.

[0122] Data flow: Processed data is read from memory and post-processed by the RISC-V CPU. This includes reading, processing, and storing data. Final output: After processing by the RISC-V CPU, the final result is stored back to memory or directly output for use. This may involve transferring the result data from memory to an output device or sending it over a network.

[0123] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0124] like Figure 4 As shown, the present invention also proposes an efficient computing device for polynomial modular multiplication based on a co-accelerator, which includes:

[0125] In the preprocessing module, the processor obtains the original polynomial pair to be subjected to polynomial modular multiplication from the memory, adjusts the coefficients of each original polynomial to a format for number-theoretic transformation within a predetermined modulus range, obtains the preprocessing polynomial, and writes it back to the memory;

[0126] The forward transformation module, the number theory transformation unit reads the preprocessing polynomial pair, converts the time domain coefficients of the preprocessing polynomial into the frequency domain representation by performing the forward number theory transformation NTT transformation, obtains the polynomial frequency domain representation and writes it back to the memory;

[0127] A dot multiplication module, in which the processor starts and controls the co-accelerator to load the frequency domain representation of the polynomial from the memory, and multiple processing units in the co-accelerator perform element-by-element dot multiplication on the frequency domain representation of the polynomial in parallel, and the dot multiplication result is stored back to the memory;

[0128] An inverse transformation module, wherein the processor schedules and controls the number theory transformation unit to read the point multiplication result and perform an inverse number theory transformation NTT transformation on it to convert the frequency domain data into a time domain representation to obtain a polynomial time domain representation;

[0129] The result processing module adjusts the time domain representation of the polynomial to obtain the polynomial modular multiplication result of the original polynomial pair.

[0130] The efficient computing device for polynomial modular multiplication based on the co-accelerator, wherein the dot multiplication module comprises:

[0131] The coefficient operation of the polynomial is distributed to multiple processing units in the co-accelerator, and the processing unit includes a vector register and an arithmetic logic unit ALU. The same operation is performed on multiple processing units simultaneously through a single instruction multiple data stream SIMD instruction, thereby realizing parallel processing of the dot multiplication operation.

[0132] The efficient computing device for polynomial modular multiplication based on a co-accelerator, wherein when the number theory transformation unit and the co-accelerator interact with each other, the co-accelerator's multi-channel memory access is used to accelerate data loading and storage; the data transmission overhead is reduced by loop unrolling and vectorization; and the number of data transmissions from the memory to the co-accelerator is reduced by a cache mechanism;

[0133] The result processing module includes:

[0134] Format adjustment: converting the polynomial time domain representation into a preset format, and combining the results of multiple stages or multiple data blocks involved in the polynomial multiplication to obtain the polynomial modular multiplication result.

[0135] like Figure 5 As shown, the present invention further proposes a first electronic device A in another embodiment, which includes the efficient computing device B for polynomial modular multiplication based on a co-accelerator.

[0136] like Figure 6 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect encrypted data, such as the original polynomial pair described in the embodiment of the present invention, and the information display device D is used to display the polynomial modular multiplication result obtained by the analysis of the present invention.

[0137] The information display device D can sort and process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll and play, etc. The user is presented with the key information specified by the user, and the user can understand the information more promptly without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present rich and necessary key information to the user.

[0138] The present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the efficient calculation method of polynomial modular multiplication based on the co-accelerator provided by the above methods.

[0139] The present invention also proposes a storage medium VIII in another embodiment for storing a computer program for executing the efficient computing method of polynomial modular multiplication based on the co-accelerator. It should be understood that the storage medium in the embodiment of the present invention can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0140] Figure 7 A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same or different from the first electronic device A.

[0141] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. In RAM III, various programs and data required for the operation of the device 1000 can also be stored. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0142] A plurality of components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard, a mouse, etc.; an output unit VII, such as various types of displays, speakers, etc.; a storage medium VIII, such as a disk, an optical disk, etc.; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0143] The computing unit I may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S5. For example, in some embodiments, the method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via ROM II and / or a communication unit IX. When the computer program is loaded into RAM III and executed by the computing unit I, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit I may be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0144] In summary, the key technical points of the present invention include:

[0145] Key point 1: Using the Hwacha SIMD architecture to accelerate the dot multiplication operation in NTT. By mapping the dot multiplication operation in NTT to the Hwacha SIMD instruction set, the parallel processing capability of SIMD is used to accelerate the calculation, which greatly improves the speed of the dot multiplication operation. In this way, when processing large-scale polynomial operations, the calculation time can be significantly reduced, thereby improving the overall efficiency.

[0146] Key point 2: Optimize data transmission and computing processes. An efficient data transmission mechanism was designed to optimize the data exchange process between the NTT computing module and the Hwacha SIMD module. By reducing the time overhead of data transmission and improving the continuity of data processing, the overall computing efficiency has been significantly improved.

[0147] Key point 3: Implementing an efficient NTT dot multiplication algorithm on the Hwacha SIMD architecture. Based on the characteristics of Hwacha SIMD, an optimized NTT dot multiplication algorithm is proposed and implemented, which can fully utilize the parallel processing capabilities of Hwacha SIMD and achieve the best balance between calculation accuracy and speed. This allows polynomial modular multiplication operations to maintain efficiency and stability in high-complexity applications.

[0148] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. An efficient calculation method for polynomial modular multiplication based on a co-accelerator, characterized in that: include: In a preprocessing step, the processor obtains the original polynomial pair to be subjected to polynomial modular multiplication from the memory, adjusts the coefficients of each original polynomial to a format for number-theoretic transformation within a predetermined modulus range, obtains a preprocessed polynomial, and writes it back to the memory; In the forward transformation step, the number theory transformation unit reads the preprocessing polynomial pair, and converts the time domain coefficients of the preprocessing polynomial into the frequency domain representation by performing the forward number theory transformation NTT transformation, obtains the frequency domain representation of the polynomial and writes it back to the memory; In the dot multiplication step, the processor starts and controls the co-accelerator to load the frequency domain representation of the polynomial from the memory, and multiple processing units in the co-accelerator perform element-by-element dot multiplication on the frequency domain representation of the polynomial in parallel, and the dot multiplication result is stored back to the memory; Inverse transformation step, the processor schedules and controls the number theory transformation unit to read the point multiplication result and perform an inverse number theory transformation NTT transformation on it to convert the frequency domain data into a time domain representation to obtain a polynomial time domain representation; In the result processing step, the processor adjusts the time domain representation of the polynomial to obtain the polynomial modular multiplication result of the original polynomial pair.

2. The efficient calculation method of polynomial modular multiplication based on the co-accelerator as claimed in claim 1, characterized in that: The dot product step includes: The coefficient operation of the polynomial is distributed to multiple processing units in the co-accelerator, and the processing unit includes a vector register and an arithmetic logic unit ALU. The same operation is performed on multiple processing units simultaneously through a single instruction multiple data stream SIMD instruction, thereby realizing parallel processing of the dot multiplication operation.

3. The efficient calculation method of polynomial modular multiplication based on the co-accelerator as claimed in claim 1 or 2, characterized in that: When the number theory transformation unit interacts with the co-accelerator, the co-accelerator's multi-channel memory access is used to accelerate data loading and storage; the data transmission overhead is reduced through loop unrolling and vectorization; and the number of data transmissions from the memory to the co-accelerator is reduced through a cache mechanism.

4. The efficient calculation method of polynomial modular multiplication based on the co-accelerator as claimed in claim 1 or 2, characterized in that: The result processing steps include: Format adjustment: converting the polynomial time domain representation into a preset format, and combining the results of multiple stages or multiple data blocks involved in the polynomial multiplication to obtain the polynomial modular multiplication result.

5. An efficient computing device for polynomial modular multiplication based on a co-accelerator, characterized in that: include: In the preprocessing module, the processor obtains the original polynomial pair to be subjected to polynomial modular multiplication from the memory, adjusts the coefficients of each original polynomial to a format for number-theoretic transformation within a predetermined modulus range, obtains the preprocessing polynomial, and writes it back to the memory; The forward transformation module, the number theory transformation unit reads the preprocessing polynomial pair, converts the time domain coefficients of the preprocessing polynomial into the frequency domain representation by performing the forward number theory transformation NTT transformation, obtains the polynomial frequency domain representation and writes it back to the memory; A dot multiplication module, in which the processor starts and controls the co-accelerator to load the frequency domain representation of the polynomial from the memory, and multiple processing units in the co-accelerator perform element-by-element dot multiplication on the frequency domain representation of the polynomial in parallel, and the dot multiplication result is stored back to the memory; An inverse transformation module, wherein the processor schedules and controls the number theory transformation unit to read the point multiplication result and perform an inverse number theory transformation NTT transformation on it to convert the frequency domain data into a time domain representation to obtain a polynomial time domain representation; The result processing module adjusts the time domain representation of the polynomial to obtain the polynomial modular multiplication result of the original polynomial pair.

6. The efficient computing device for polynomial modular multiplication based on a co-accelerator as claimed in claim 5, characterized in that: The dot product module includes: The coefficient operation of the polynomial is distributed to multiple processing units in the co-accelerator, and the processing unit includes a vector register and an arithmetic logic unit ALU. The same operation is performed on multiple processing units simultaneously through a single instruction multiple data stream SIMD instruction, thereby realizing parallel processing of the dot multiplication operation.

7. The efficient computing device for polynomial modular multiplication based on a co-accelerator as claimed in claim 5 or 6, characterized in that: When the number theory transformation unit interacts with the co-accelerator, the co-accelerator's multi-channel memory access is used to accelerate data loading and storage; loop unrolling and vectorization are used to reduce data transmission overhead; Through the cache mechanism, the number of data transmissions from the memory to the co-accelerator is reduced; The result processing module includes: Format adjustment: converting the polynomial time domain representation into a preset format, and combining the results of multiple stages or multiple data blocks involved in the polynomial multiplication to obtain the polynomial modular multiplication result.

8. An electronic device, characterized in that: An efficient computing device for polynomial modular multiplication based on a co-accelerator as described in claims 5-7, wherein the electronic device is connected to an information display device, and the information display device is used to display the result of the polynomial modular multiplication with display parameters and attributes set by the user or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the efficient calculation method of polynomial modular multiplication based on a co-accelerator as recited in any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the efficient calculation method of polynomial modular multiplication based on a co-accelerator as recited in any one of claims 1 to 4 are implemented.

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