DRC checking method for high-temperature co-fired multilayer ceramic packaging shell ceramic piece layout CAD file

Abstract

The invention discloses a DRC inspection method for a high-temperature co-fired multilayer ceramic packaging shell ceramic layout CAD file, and the method comprises the steps: printing an amplified single-layer design file with transparent parchment paper, and the single-layer design file comprises a printing graph, a punching graph, a cavity opening graph and a ceramic outer contour; the printed single-layer design files are aligned and stacked according to the porcelain wiring layer design sequence and then bound into a porcelain layout amplification transparent printed piece; performing single-layer design rule check, short circuit check and on-off check according to the ceramic layout amplification transparent printed piece and the ceramic layout electronic edition file, and traversing all ceramic wiring layers; and according to the porcelain layout amplification transparent printed piece and the porcelain layout electronic edition file, adjacent layer design rule checking, short circuit checking and on-off checking are carried out, and all networks are traversed according to the porcelain network list file. According to the method, by manufacturing the ceramic layout amplification transparent printing piece, a designer can more visually check the design rule and the electric connection relation of ceramic wiring.

Description

Technical Field

[0001] The invention relates to a DRC inspection method for a high-temperature co-fired multi-layer ceramic packaging shell ceramic part layout CAD file, belonging to electronic packaging design technology. Background Art

[0002] Semiconductor integrated circuit products such as operational amplifiers, memories, AD conversion, FPGA, ASIC, etc. are generally designed using commercial EDA software such as Protel, Autium Designer, Cadence, etc. This type of commercial software has powerful functions, friendly user interfaces, a wide range of application scenarios, and advanced design and analysis tools, which can achieve design tasks such as schematic design, circuit simulation, layout design, and design rule checking. However, this type of large-scale software also has disadvantages such as high prices, high hardware requirements, and long learning cycles.

[0003] Autocad has become one of the most widely used computer-aided drawing and design software in the field of engineering design due to its powerful and flexible drawing and design functions. The DWG format output by Autocad and its ASCII format variant DXF have become the de facto file standard for CAD drawing data exchange. The graphical interface, operating habits and file format of domestic ZWCAD or HaochenCAD are well compatible with Autocad, and their market share in the design software of the mechanical and electronic industries is also gradually increasing.

[0004] Autocad has stronger two-dimensional editing functions than EDA software and is simpler to learn, which is enough to meet the design requirements of ceramic substrates and shells. Manufacturers of high-low temperature co-fired ceramic substrates (HTCC / LTCC Substrate) or ceramic shells sometimes need to convert circuit layout files (.pcb format) designed by EDA software such as Protel, Autium Designer, Cadence, etc. into the .dwg format of Autocad software for subsequent layout, editing and modification. Sometimes, according to the circuit schematics provided by integrated circuit designers, Autocad can also be used directly for layout design. Autocad does not support automatic design rule checking and continuity checking for .dwg layout files, and can only be converted to EDA software through third-party software.

[0005] The present invention provides a simple, easy and reliable method to implement the design rule check of .dwg layout files and the continuity and short circuit check of the network table. Summary of the invention

[0006] The present invention uses an ordinary office laser printer and transfer sulfuric acid paper as the printing medium to print out the layout file layer by layer, so as to use manual visual inspection to traverse the network table one by one to realize the inspection of design rules and on / off and short circuits. A detailed preparation method of "printed layout design file" and a manual inspection method are proposed.

[0007] Since the network of an integrated circuit usually spans multiple layers of a layout file, when performing design rule and continuity and short circuit checks on the network, it is necessary to repeatedly open and close layers in the Autocad software to eliminate interference and misjudgment. Using the "printed layout design file" as an auxiliary tool for design rule checks and continuity and short circuit checks can greatly improve work efficiency and inspection accuracy.

[0008] By making an "enlarged transparent printout of the ceramic layout" and combining it with the electronic version of the ceramic layout dwg file to check whether the wiring of each layer of the HTCC ceramic component meets the design rules and electrical connection relationship, compared with using the electronic version of the ceramic layout file alone for DRC inspection, it can significantly improve efficiency and is more conducive to preventing missed detection and wrong detection.

[0009] Specifically, a DRC inspection method for a high-temperature co-fired multilayer ceramic package shell ceramic component layout CAD file includes the following steps: Step S01: Enlarging the printed graphics and punched graphics on each ceramic wiring layer in the ceramic layout, printing the printed graphics and punched graphics on each ceramic wiring layer on a transparent material respectively, aligning and stacking them in sequence according to the layer order of the HTCC ceramic layout design, and binding them so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer are aligned; Step S02: Check the single-layer graphics by comparing the enlarged transparent printout and the electronic version of the ceramic pattern in step S01. ; Step S03: According to step S02, all layers are checked and traversed in sequence; Step S04: Check the interconnection relationship of adjacent layers by comparing the layout file and the electronic version file printed out in step S01; Step S05: According to step S04, all networks are checked and traversed in sequence.

[0010] Furthermore, step S01 includes the following steps: Step S01-01: Open the layout file in the CAD software, and only display the printing file and the punching file on the ceramic layer Layer 1 at the same time, and close other layers; wherein the geometric figures of the printing file are in a non-pattern filling state, that is, only the outer contour of the geometric figures is displayed; Step S01-02: scaling the printing file and punching file displayed in step S01-01 according to the ratio xScale, so that the graphics can be placed in the effective printing area of ​​A3 or A4 printing paper and the graphics can be clearly identified; Step S01-03: From the 2nd layer to the Nth layer, traverse the printing files and punching files of all ceramic layers of the substrate, repeat the operations of steps S01-01 and S01-02, and generate a series of printing layout files; Step S01-04: setting the printer to the same printing parameters, and printing out all the print layout files generated in step S01-03 using transparent sulphuric acid paper; Step S01-05: According to the layer sequence of the HTCC ceramic layout design, the files printed out in step S01-04 are aligned, stacked and bound in sequence, so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer remain aligned.

[0011] Furthermore, the single-layer pattern inspection in step S02 includes: appearance inspection and real-time measurement of geometric parameters of suspicious positions or extreme positions, checking whether the pattern complies with HTCC design rules; and checking whether the pattern has short circuits and open circuits.

[0012] Further, step S02 includes the following steps: Step S02-01: Check the line width and line spacing of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the line width and line spacing meet the design rules; Step S02-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the distance between the adjacent network is less than the safe distance.

[0013] Furthermore, the checking of the interconnection relationship of adjacent layers in step S04 includes: Visual inspection and immediate measurement of geometric parameters at suspicious or extreme positions to check whether the graphics comply with HTCC design rules; check whether there are short circuits and open circuits in the graphic design; this step checks the continuity and disconnection of a single network at each layer connection and the short circuit with adjacent networks according to the network table definition of the HTCC substrate.

[0014] Further, step S04 includes the following steps: Step S04-01: Check the connectivity of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2, …, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there are any graphic errors including extra punching, missing punching, and misaligned punching.

[0015] Step S04-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there is a short circuit between the adjacent networks or the spacing is less than the safe distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 MCP24-130 ceramic layout file with layers opened simultaneously; Figure 2 For the printed MCP24-130_Layer14; Figure 3 For the printed MCP24-130_Layer13; Figure 4 For the printed MCP24-130_Layer12; Figure 5 For the printed MCP24-130_Layer11; Figure 6 For the printed MCP24-130_Layer10; Figure 7 For the printed MCP24-130_Layer9; Figure 8 For the printed MCP24-130_Layer8. DETAILED DESCRIPTION

[0017] In the embodiments of the present invention, the technical solutions will be described clearly and completely in conjunction with the accompanying drawings. It is worth noting that the embodiments only represent some applications of the present invention, not all of them. According to the principles of the present invention, ordinary technicians in this field can obtain all other embodiments without performing creative work, and these embodiments are also protected by the present invention. In the following description, two specific embodiments will be elaborated in detail to demonstrate the feasibility and application potential of the present invention.

[0018] See also Figure 1-8 , a DRC inspection method for a high temperature co-fired multilayer ceramic package shell ceramic component layout CAD file, comprising the following steps: Step S01: Enlarging the printed graphics and punched graphics on each ceramic wiring layer in the ceramic layout, printing the printed graphics and punched graphics on each ceramic wiring layer on a transparent material respectively, aligning and stacking them in sequence according to the layer order of the HTCC ceramic layout design, and binding them so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer are aligned; Step S02: Check the single-layer graphics by comparing the enlarged transparent printout and the electronic version of the ceramic pattern in step S01. ; Step S03: According to step S02, all layers are checked and traversed in sequence; Step S04: Check the interconnection relationship of adjacent layers by comparing the layout file and the electronic version file printed out in step S01; Step S05: According to step S04, all networks are checked and traversed in sequence.

[0019] Furthermore, step S01 includes the following steps: Step S01-01: Open the layout file in the CAD software, and only display the printing file and the punching file on the ceramic layer Layer 1 at the same time, and close other layers; wherein the geometric figures of the printing file are in a non-pattern filling state, that is, only the outer contour of the geometric figures is displayed; Step S01-02: scaling the printing file and punching file displayed in step S01-01 according to the ratio xScale, so that the graphics can be placed in the effective printing area of ​​A3 or A4 printing paper and the graphics can be clearly identified; Step S01-03: From the 2nd layer to the Nth layer, traverse the printing files and punching files of all ceramic layers of the substrate, repeat the operations of steps S01-01 and S01-02, and generate a series of printing layout files; Step S01-04: setting the printer to the same printing parameters, and printing out all the print layout files generated in step S01-03 using transparent sulphuric acid paper; Step S01-05: According to the layer sequence of the HTCC ceramic layout design, the files printed out in step S01-04 are aligned, stacked and bound in sequence, so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer remain aligned.

[0020] Furthermore, the single-layer pattern inspection in step S02 includes: appearance inspection and real-time measurement of geometric parameters of suspicious positions or extreme positions, checking whether the pattern complies with HTCC design rules; and checking whether the pattern has short circuits and open circuits.

[0021] Further, step S02 includes the following steps: Step S02-01: Check the line width and line spacing of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the line width and line spacing meet the design rules; Step S02-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the distance between the adjacent network is less than the safe distance.

[0022] Furthermore, the checking of the interconnection relationship of adjacent layers in step S04 includes: Visual inspection and immediate measurement of geometric parameters at suspicious or extreme positions to check whether the graphics comply with HTCC design rules; check whether there are short circuits and open circuits in the graphic design; this step checks the continuity and disconnection of a single network at each layer connection and the short circuit with adjacent networks according to the network table definition of the HTCC substrate.

[0023] Further, step S04 includes the following steps: Step S04-01: Check the connectivity of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2, …, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there are any graphic errors including extra punching, missing punching, and misaligned punching.

[0024] Step S04-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there is a short circuit between the adjacent networks or the spacing is less than the safe distance.

[0025] like Figure 1 The ceramic layout of the MCP24-130 multi-chip package is shown. Figure 1 In the example, all 7 layers from Layer 14 to Layer 8 are turned on. The status when Layer 14 to Layer 8 including Via and Trace are turned on separately is as follows: Figure 2 to Figure 8 As shown, when Figure 2 to Figure 8 After printing on translucent sulfuric acid paper at the same scale, and then arranging and aligning them in order up and down, the correctness of the network table connection relationship can be checked intuitively and efficiently.

[0026] As a general multi-layer wiring substrate and packaging technology, high temperature co-fired multi-layer ceramic HTCC can be used to manufacture various types of high-performance, high-reliability, hermetic or non-hermetic packaging substrates and housing products, and is used to package semiconductor discrete devices, integrated circuits, hybrid integrated circuits, optoelectronic devices, MEMS sensors, etc. In addition to the above embodiments, the HTCC ceramic layout DRC inspection method of the present invention is applicable to the ceramic layout DRC inspection of most of the above HTCC substrates and housings, and has a wide range of applicability.

[0027] The examples described in the present invention are merely descriptions of the preferred implementation modes of the present invention, and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by engineers and technicians in this field should all fall within the protection scope of the present invention.

Claims

1. A DRC inspection method for a high temperature co-fired multilayer ceramic package shell ceramic part layout CAD file, characterized in that The steps include: Step S01: Enlarging the printed graphics and punched graphics on each ceramic wiring layer in the ceramic layout, printing the printed graphics and punched graphics on each ceramic wiring layer on a transparent material respectively, aligning and stacking them in sequence according to the layer order of the HTCC ceramic layout design, and binding them so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer are aligned; Step S02: Check the single-layer pattern by comparing the enlarged transparent printout and the electronic version of the ceramic pattern in step S01; Step S03: According to step S02, all layers are checked and traversed in sequence; Step S04: Check the interconnection relationship of adjacent layers by comparing the layout file and the electronic version file printed out in step S01; Step S05: According to step S04, all networks are checked and traversed in sequence.

2. A method for inspecting the layout DRC of a high temperature co-fired multi-layer ceramic package shell ceramic component as claimed in claim 1, characterized in that: Step S01 includes the following steps: Step S01-01: Open the layout file in the CAD software, and only display the printing file and the punching file on the ceramic layer Layer 1 at the same time, and close other layers; wherein the geometric figures of the printing file are in a non-pattern filling state, that is, only the outer contour of the geometric figures is displayed; Step S01-02: scaling the printing file and punching file displayed in step S01-01 according to the ratio xScale, so that the graphics can be placed in the effective printing area of ​​A3 or A4 printing paper and the graphics can be clearly identified; Step S01-03: From the 2nd layer to the Nth layer, traverse the printing files and punching files of all ceramic layers of the substrate, repeat the operations of steps S01-01 and S01-02, and generate a series of printing layout files; Step S01-04: setting the printer to the same printing parameters, and printing out all the print layout files generated in step S01-03 using transparent sulphuric acid paper; Step S01-05: According to the layer sequence of the HTCC ceramic layout design, the files printed out in step S01-04 are aligned, stacked and bound in sequence, so that the printed graphics and punched graphics with the same XY coordinates distributed on each layer remain aligned.

3. The method for inspecting the layout DRC of a high temperature co-fired multilayer ceramic package shell ceramic component according to claim 1, characterized in that: Step S02: Single-layer pattern inspection includes: appearance inspection and real-time measurement of geometric parameters of suspicious positions or extreme positions, inspection of whether the pattern complies with HTCC design rules, and inspection of whether the pattern has short circuits and open circuits.

4. The method for inspecting the layout DRC of a high temperature co-fired multilayer ceramic package shell ceramic component according to claim 3, characterized in that: Step S02 includes the following steps: Step S02-01: Check the line width and line spacing of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the line width and line spacing meet the design rules; Step S02-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if the distance between the adjacent network is less than the safe distance.

5. The method for inspecting the layout DRC of a high temperature co-fired multi-layer ceramic package shell ceramic component according to claim 1, characterized in that: Step S04 of checking the interconnection relationship of adjacent layers includes: Visual inspection and immediate measurement of geometric parameters at suspicious or extreme positions to check whether the graphics comply with HTCC design rules; check whether there are short circuits and open circuits in the graphic design; this step checks the continuity and disconnection of a single network at each layer connection and the short circuit with adjacent networks according to the network table definition of the HTCC substrate.

6. The method for inspecting the layout DRC of a high temperature co-fired multilayer ceramic package shell ceramic component according to claim 5, characterized in that: Step S04 includes the following steps: Step S04-01: Check the connectivity of the network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2, ..., LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there are any graphic errors including extra punching, missing punching, and misaligned punching; Step S04-02: Check the short circuit between the network and the adjacent network, starting from the external pin pin1 of Layer0, in the order of Layer0, Layer1, Layer2,…, LayerM, check the printed graphics and punched graphics of each layer from bottom to top to see if there is a short circuit between the adjacent networks or the spacing is less than the safe distance.

Images