Semiconductor device and preparation method thereof, and chip detection system

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, and a chip detection system, relates to the technical field of chip detection, and is used for improving the test efficiency and reliability of a chip. The semiconductor device comprises a circuit substrate, an adapter plate, a connecting piece and a detection contact piece. The adapter plate and the circuit substrate are arranged in a stacked mode, the connecting piece is located between the adapter plate and the circuit substrate and connected with the adapter plate and the circuit substrate, and the detection contact piece is located on the side, away from the circuit substrate, of the adapter plate. The circuit substrate comprises a detection circuit, the adapter plate comprises an adapter line, and the detection contact is electrically connected to the detection circuit through the adapter line. The semiconductor device can be used as a probe card structure and applied to a chip detection system.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip detection technology, and in particular, to a semiconductor device and a method for manufacturing the same, and a chip detection system. Background Art

[0002] The probe card structure is a very important technology in the chip manufacturing process. Before the chip is packaged, the probe on the probe card structure contacts the chip's pad or bump, and cooperates with test equipment such as a probe station to achieve automated measurement and screen known good die (KGD). At present, the existing probe card structure has the problem of low test efficiency. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a semiconductor device and a method for manufacturing the same, and a chip detection system.

[0004] In order to achieve the above purpose, the present application provides the following solutions:

[0005] On the one hand, a semiconductor device is provided, comprising: a circuit substrate, an adapter board, a connector and a detection contact. The adapter board and the circuit substrate are stacked, the connector is located between the adapter board and the circuit substrate, the connector connects the adapter board and the circuit substrate, and the detection contact is located on the side of the adapter board away from the circuit substrate. The circuit substrate includes a detection circuit, the adapter board includes a transfer circuit, and the detection contact is electrically connected to the detection circuit through the transfer circuit.

[0006] The semiconductor device provided in the embodiment of the present application has an adapter plate and a connector, so that the adapter plate can be formed independently of the circuit substrate. Thereafter, the formed adapter plate can be connected to the circuit substrate through the adapter. In this way, compared with forming the adapter circuit directly above the circuit substrate through photoforming, developing, and electroplating methods, the line width and line spacing of the adapter circuit in the adapter plate can be set narrower and denser. Furthermore, when the detection contact is set on the side of the adapter plate away from the circuit substrate, the setting range of the detection contact can be larger. For example, the detection contact can include a plurality of probes arranged at intervals, and the setting range and density of the probes can be increased. In this way, when the semiconductor device is used as a probe card structure, the detection efficiency of the chip can be improved, and since the probe spacing can better match the chip pad spacing, it is also beneficial to improve the reliability during detection.

[0007] In some embodiments, the adapter board includes a stacked support connection layer and an interconnection layer; the interconnection layer includes an interconnection line and an interlayer dielectric layer, and the interconnection line is embedded in the interlayer dielectric layer; the support connection layer includes a conductive column and a support material layer, and the conductive column is embedded in the support material layer; the support material layer is stacked with the interlayer dielectric layer, and the conductive column is electrically connected to the interconnection line; the adapter line includes the conductive column and the interconnection line. In this embodiment, since the interconnection layer can be formed on other carriers first, the line width and line spacing of the interconnection line therein can be smaller than the previous thin film wire. As a result, the layout range and layout density of the detection contact can be effectively improved, thereby improving the detection efficiency. In addition, since the stacked support connection layer is also provided to form the adapter board together, the support effect on the interconnection layer can also be improved, thereby improving the reliability of the interconnection layer, and thus the reliability of the semiconductor device will also be improved.

[0008] In some embodiments, the material of the support material layer includes polymer materials. Such as polyimide (PI), glass, etc. Such a setting has at least the following advantages: 1. Lightweight and high strength: Compared with traditional metal materials, polymer materials have a lower density, light weight, and high strength; 2. Corrosion resistance: polymer materials are corrosion-resistant and can be used for a long time in acidic and alkaline environments, and are not easily corroded and damaged by chemical substances; 3. Good processability: polymer materials have good plasticity and are easy to shape. They can be formed into products of various shapes through processes such as blow molding, extrusion, and injection molding, thereby facilitating the formation of a support connection layer surrounding the conductive column; 4. Excellent insulation performance: polymer materials have good insulation performance; 5. Strong impact resistance: polymer synthetic materials have good impact resistance, making the support connection layer shock-resistant and collision-resistant.

[0009] In some embodiments, fillers are added to the polymer material. After adding the fillers, for example, a molding compound or an aromatic benzocyclobutene film (ABF) can be formed. The main component of ABF is an aromatic benzocyclobutane monomer. In addition, it also contains some auxiliary components (i.e., fillers), such as solvents, stabilizers, hardeners, etc. In addition, the fillers can also be other materials that can improve the performance of the film layer (such as hardness, toughness, etc.). In this way, the supporting material layer can better support the interconnection layer, greatly improving the structural stability of the semiconductor device.

[0010] In some embodiments, the semiconductor device further comprises a mesh structure embedded in the supporting material layer, wherein each mesh of the mesh structure surrounds at least one of the conductive pillars. Such a configuration can provide a better support effect for the conductive pillars, thereby preventing the conductive pillars from tipping over, thereby preventing problems such as poor contact and circuit breakage in the transfer circuit of the transfer board.

[0011] In some embodiments, the support material layer is provided between the mesh structure and the conductive column. This arrangement can not only improve the support effect on the conductive column through the mesh structure, but also utilize the support material layer between the mesh structure and the conductive column to release stress to a certain extent, thereby facilitating the stability of the adapter plate.

[0012] In some embodiments, the wall thickness of the support material layer between the mesh structure and the conductive column is smaller than the wall thickness of the mesh structure. In this way, the support material layer between the mesh structure and the conductive column can be used to release stress to a certain extent, but it is not easy to cause the mesh structure to have insufficient support effect on the conductive column due to the excessive wall thickness of the support material layer between the mesh structure and the conductive column.

[0013] In some embodiments, the hardness of the mesh structure is greater than the hardness of the supporting material layer. This configuration can better enhance the supporting effect of the mesh structure on the conductive column.

[0014] In some embodiments, the material of the mesh structure includes one or more combinations of silicon, glass, metal and ceramic. Such a configuration can effectively enhance the supporting effect of the mesh structure on the conductive column.

[0015] In some embodiments, the line width of the interconnection line is greater than or equal to 2 microns and less than 50 microns, and the line spacing of the interconnection line is greater than or equal to 20 microns and less than 50 microns. The interconnection lines in this embodiment have smaller line width and line spacing and higher density, thereby effectively improving the layout range and layout density of the detection contact members, thereby improving the detection efficiency.

[0016] In some embodiments, the interlayer dielectric layer includes at least 4 stacked sub-layers. In this embodiment, the number of sub-layers of the interlayer dielectric layer in the interconnect layer and the number of layers of the corresponding interconnect lines can be increased, such as 4 or more layers, which effectively reduces the difficulty of wiring.

[0017] In some embodiments, the supporting connection layer is closer to the circuit substrate than the interconnection layer. In this way, the supporting connection layer can be used to support the interconnection layer, thereby improving the structural strength of the adapter board.

[0018] In some embodiments, the interconnection layer is closer to the circuit substrate than the supporting connection layer. In this way, the supporting connection layer can be used to support the interconnection layer, thereby improving the structural strength of the adapter board.

[0019] In some embodiments, the number of the supporting connection layers is two, and the interconnection layer is sandwiched between the two supporting connection layers. In this embodiment, since two supporting connection layers are provided, a better supporting effect can be played on the interconnection layer.

[0020] In some embodiments, the number of the interconnection layers is two, and the supporting connection layer is sandwiched between the two interconnection layers. In this embodiment, since two interconnection layers are included, it is easier to arrange the switching circuit, and thus it is easier to realize the detection function.

[0021] In some embodiments, the connector includes a plurality of solders arranged at intervals, so as to facilitate the stable and reliable soldering of the adapter board to the circuit substrate.

[0022] In some embodiments, the semiconductor device further comprises a filling material layer, which is filled between the circuit substrate and the adapter plate and surrounds the connector. In this embodiment, by providing the filling material layer, the connector (e.g., a plurality of solders) can be protected, for example, from water vapor corrosion, etc., thereby improving the connection stability between the adapter plate and the circuit substrate.

[0023] In some embodiments, the semiconductor device further comprises a mounting frame connected to a side of the circuit substrate away from the adapter plate. In this embodiment, the circuit substrate can be supported by the mounting frame, and the entire semiconductor device can be moved by moving the mounting frame.

[0024] In some embodiments, the semiconductor device is a probe card structure, and the detection contact element includes a plurality of probes arranged at intervals. In this embodiment, the semiconductor device is used as a probe card structure and can be applied to a chip detection system.

[0025] On the other hand, a chip detection system is provided, comprising: a probe station and a probe card structure connected to each other, wherein the probe card structure comprises the semiconductor device in any of the above embodiments. The chip detection system in this embodiment, since it comprises the above semiconductor device, has at least the technical effect corresponding to the above, and will not be described in detail here.

[0026] On the other hand, a method for preparing a semiconductor device is provided, comprising: forming an adapter board on a carrier board, the adapter board including a adapter circuit; forming a connector on the adapter board; transferring the adapter board on the carrier board to one side of a ceramic board, and connecting the adapter board to the ceramic board through the connector; forming a detection contact on a side of the adapter board facing away from the ceramic board; electrically connecting a surface of the ceramic board facing away from the adapter board to a printed circuit board; the printed circuit board and the ceramic board constitute a circuit substrate, the circuit substrate including a detection circuit, the adapter board including a adapter circuit, and the detection contact electrically connected to the detection circuit through the adapter circuit.

[0027] Compared with forming the adapter circuit directly on the circuit substrate by photoforming, developing, and electroplating methods, the preparation method provided in the present embodiment can set the line width and line spacing of the adapter circuit in the adapter board to be narrower and denser. Furthermore, when the detection contact piece is set on the side of the adapter board away from the circuit substrate, the setting range of the detection contact piece is larger. For example, the detection contact piece can include a plurality of probes arranged at intervals, and the setting range and density of the probes can be increased. In this way, when the formed semiconductor device is used as a probe card structure, the detection efficiency of the chip can be improved. Moreover, since the probe spacing can better match the chip pad spacing, it is also beneficial to improve the reliability during detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A structural diagram of a semiconductor device provided in an embodiment of the present application;

[0029] Figure 2 for Figure 1 A cross-sectional view of the semiconductor device along the AA direction;

[0030] Figure 3 for Figure 2 An enlarged view of a local area B of the semiconductor device;

[0031] Figure 4-Figure 7 A structural diagram corresponding to some steps of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0032] Figure 8 A structural diagram of another semiconductor device provided in an embodiment of the present application;

[0033] Fig. 9 A structural diagram of another semiconductor device provided in an embodiment of the present application;

[0034] Fig.10 A structural diagram of another semiconductor device provided in an embodiment of the present application;

[0035] Fig.11 This is a structural diagram of the chip detection system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0038] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "electrical connection" may refer to a direct electrical connection or an indirect electrical connection via an intermediate medium.

[0039] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0040] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0041] In the embodiments of the present application, directional indications such as up, down, left, right, front, and back, etc., used to explain the structure and movement of different components in the present application are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component position changes, then these directional indications will also change accordingly.

[0042] During the chip manufacturing process, each chip requires at least one corresponding probe card structure for testing. The purpose of the test is to allow good products to enter the next packaging process after the wafer is cut, so as to avoid waste caused by continued processing of defective products. As the chip integration level is greatly improved, the distance between the chip pads is greatly reduced. For this reason, it is necessary to simultaneously reduce the line width and line spacing of the probe card structure to reduce the distance (pitch) between the probes. However, the inventors of the present application have found that in the probe card structure of the related art, the line width and line spacing are both large, which leads to a larger distance (pitch) between the probes. When testing chips with a high degree of integration, it is difficult to achieve a good match, resulting in relatively low test efficiency and reliability.

[0043] Based on this, the inventor of the present application further studied and found that the probe card structure in the related art is to form a re-distribution layer (RDL layer for short) and a bump gasket directly on a ceramic multilayer substrate by photoforming, developing, and electroplating methods. The re-distribution layer includes an insulating medium and a multilayer thin film wire embedded in the insulating medium. The bump gasket is electrically connected to the thin film wire, and then the probe is fixed to the bump gasket using an adhesive or welding. This solution has many limitations due to the fact that the RDL layer is directly formed on the ceramic substrate (for example, the manufacturing process accuracy of the RDL layer will be limited by the material properties of the ceramic substrate and the circuit structure on the ceramic substrate, etc.), resulting in a large line width and line spacing of the thin film wire of the formed RDL layer, a low density of thin film wires, and a limited number of RDL layers. Furthermore, there are fewer locations on the RDL layer where bump gaskets can be set, so the area where probes can be planted is smaller, the number of chips that can be measured at a single time is lower, and the test efficiency is lower.

[0044] In another related technology, a bump pad is directly formed on a ceramic substrate, and then the probe is fixed to the bump pad. Each probe is connected to two circuits in the interposer layer of the ceramic substrate through the bump pad. This solution can enhance the connection strength between the probe and the interposer layer, but there is also the problem of a small area where the probe can be implanted.

[0045] In another related technology, a probe is formed directly on a ceramic multilayer substrate by photoforming, developing, and electroplating methods. This solution eliminates the bonding or welding of the probe and the interposer layer on the ceramic substrate, further strengthening the connection strength between the probe and the interposer layer, but there is also the problem of a small area where the probe can be implanted.

[0046] Based on at least one technical problem existing in the above solution, an embodiment of the present application provides a semiconductor device 100 and a preparation method thereof. The semiconductor device 100 can be a probe card structure for improving the test efficiency and reliability of the probe card structure.

[0047] Figure 1 A structural diagram of a semiconductor device 100 provided in an embodiment of the present application is shown in FIG. Figure 2 for Figure 1 A cross-sectional view of the semiconductor device 100 along the AA direction (in order to conveniently illustrate the cross-sectional structure of the semiconductor device 100, Figure 2 The quantity relationship of some parts in the Figure 1 ,for example Figure 1 The number of the detection contacts 40 at the interception position is not equal to Figure 2 The cross-sectional view shown in FIG. 1 shows the number of detection contacts 40, but in reality, the two should be equal), Figure 3 for Figure 2 FIG. 1 is an enlarged view of a local area B of the semiconductor device 100 .

[0048] like Figure 1-Figure 3 As shown, the semiconductor device 100 includes: a circuit substrate 10, an adapter board 20, a connector 30 and a detection contact 40. The adapter board 20 and the circuit substrate 10 are stacked, the connector 30 is located between the adapter board 20 and the circuit substrate 10, the connector 30 connects the adapter board 20 and the circuit substrate 10, and the detection contact 40 is located on the side of the adapter board 20 away from the circuit substrate 10. The circuit substrate 10 includes a detection circuit 91, the adapter board 20 includes a transfer line 92, and the detection contact 40 is electrically connected to the detection circuit 91 through the transfer line 92.

[0049] Exemplarily, the circuit substrate 10 includes a ceramic board 102. One side of the ceramic board 102 can be electrically connected to the adapter board 20 through a connector 30. The ceramic board 102 can be provided with a detection circuit 91 or a part of the detection circuit 91 (such as Figure 3 On this basis, the circuit substrate 10 may further include a printed circuit board 101. The printed circuit board 101 is connected to the other side of the ceramic board 102 away from the adapter board 20, and the detection circuit 91 or another part of the detection circuit 91 may also be arranged in the printed circuit board 101.

[0050] In addition, in order to facilitate the movement of the semiconductor device 100, a mounting frame 60 may be provided on the side of the printed circuit board 101 away from the ceramic board 102. The structure of the mounting frame 60 may be as follows: Figure 2As shown, the mounting frame 60 can be connected to only a part of the surface of the side of the printed circuit board 101 away from the ceramic plate 102, so that it is conducive to reducing the use of materials, saving costs, and the semiconductor device 100 can be stably and reliably moved by the mounting frame 60. Exemplarily, a boss 601 can be formed on the side of the mounting frame 60 away from the printed circuit board 101, which is convenient for the robot to grasp. In this way, when the semiconductor device 100 is a probe card structure, it is convenient to apply it to a chip detection system composed of test equipment such as a probe station. Of course, in other examples, a notch 602 (the notch 602 can expose the printed circuit board 101 to facilitate better heat dissipation of the printed circuit board 101) and other structures that are convenient for grasping can also be formed on the side of the mounting frame 60 away from the printed circuit board 101, and this application does not limit this.

[0051] The semiconductor device 100 provided in the embodiment of the present application has an adapter board 20 and a connector 30, so that the adapter board 20 can be formed independently of the circuit substrate 10. Afterwards, the formed adapter board 20 can be connected to the circuit substrate 10 through the adapter 30. In this way, compared with forming the adapter circuit directly above the circuit substrate 10 by photoforming, developing, and electroplating methods, the line width and line spacing of the adapter circuit in the adapter board 20 can be set narrower and denser. Furthermore, when the detection contact 40 is set on the side of the adapter board 20 away from the circuit substrate 10, the setting range of the detection contact 40 can be larger. For example, the detection contact 40 can include a plurality of probes 401 arranged at intervals, and the setting range and density of the probes 401 can be increased. In this way, when the semiconductor device 100 is used as a probe card structure, the detection efficiency of the chip can be improved, and since the probe spacing can better match the chip pad spacing, it is also beneficial to improve the reliability during detection.

[0052] Next, continue to combine Figure 1-Figure 3 , the structure of the adapter plate 20 is described in detail.

[0053] In some embodiments, the adapter board 20 includes a stacked support connection layer 210 and an interconnection layer 220. The interconnection layer 220 includes an interconnection line 221 and an interlayer dielectric layer 222, and the interconnection line 221 is embedded in the interlayer dielectric layer 222. The support connection layer 210 includes a conductive column 202 and a support material layer 201, and the conductive column 202 is embedded in the support material layer 201. The support material layer 201 and the interlayer dielectric layer 222 are stacked, and the conductive column 202 is electrically connected to the interconnection line 221. The adapter circuit 92 includes a conductive column 202 and an interconnection line 221.

[0054] The interconnection layer 220 in this embodiment can function as the previous RDL layer, and since the interconnection layer 220 can be formed on other carriers first, the line width and line spacing of the interconnection lines 221 therein can be smaller than the previous thin film wires. As a result, the arrangement range and arrangement density of the detection contact members 40 can be effectively improved, thereby improving the detection efficiency. In addition, since a stacked support connection layer 210 is also provided to form the adapter board 20, the support effect of the interconnection layer 220 can also be improved, thereby improving the reliability of the interconnection layer 220, and thus the reliability of the semiconductor device 100 will also be improved.

[0055] Exemplarily, the line width of the interconnection line 221 is greater than or equal to 2 microns and less than 50 microns, and the line spacing of the interconnection line 221 is greater than or equal to 20 microns and less than 50 microns. The interconnection line 221 in the embodiment of the present application has a smaller line width and line spacing, and a higher density, thereby effectively improving the arrangement range and arrangement density of the detection contact member 40, thereby improving the detection efficiency.

[0056] Exemplarily, the interlayer dielectric layer 222 includes at least 4 stacked sub-film layers. As mentioned above, since the interconnection layer 220 can be formed on other substrates first, the number of sub-film layers of the interlayer dielectric layer 222 in the interconnection layer 220 and the number of layers of the corresponding interconnection lines 221 can be made larger, such as 4 layers or more, which effectively reduces the wiring difficulty.

[0057] In some embodiments, the material of the support material layer 201 includes polymer materials, such as polyimide (PI), glass, etc. Such a configuration has at least the following advantages: 1. Lightweight and high strength: Compared with traditional metal materials, polymer materials have a lower density, are light in weight, and have high strength; 2. Corrosion resistance: polymer materials are corrosion-resistant and can be used for a long time in an acidic and alkaline environment, and are not easily corroded and damaged by chemical substances; 3. Good processability: polymer materials have good plasticity and are easy to shape. They can be formed into products of various shapes through processes such as blow molding, extrusion, and injection molding, thereby facilitating the formation of a support connection layer 210 surrounding the conductive column; 4. Excellent insulation performance: polymer materials have good insulation performance; 5. Strong impact resistance: polymer synthetic materials have good impact resistance, making the support connection layer 210 shock-resistant and collision-resistant.

[0058] Exemplarily, fillers are added to the polymer material. After adding the fillers, for example, a molding compound or an aromatic benzocyclobutene film (ABF) can be formed. The main component of ABF is an aromatic benzocyclobutane monomer. In addition, it also contains some auxiliary components (i.e., fillers), such as solvents, stabilizers, hardeners, etc. In addition, the fillers can also be other materials that can improve the performance of the film layer (such as hardness, toughness, etc.). In this way, the supporting material layer 201 can better support the interconnect layer and greatly improve the structural stability of the semiconductor device 100.

[0059] In some embodiments, the semiconductor device 100 further includes a mesh structure 203 embedded in the support material layer, and each mesh of the mesh structure 203 surrounds at least one conductive column 202. Such a configuration can provide a better support effect for the conductive column 202. This prevents the conductive column 202 from tipping over, thereby preventing the transfer circuit 92 of the transfer board 20 from having poor contact, circuit breakage, and other problems.

[0060] Exemplarily, the material of the mesh structure 203 includes one or more combinations of silicon, glass, metal and ceramic. Such a configuration can effectively improve the supporting effect of the mesh structure 203 on the conductive pillar 202 .

[0061] In some examples, the hardness of the mesh structure 203 is greater than the hardness of the supporting material layer 201. Such a configuration can better enhance the supporting effect of the mesh structure 203 on the conductive pillars 202.

[0062] In some embodiments, there is a support material layer 201 between the mesh structure 203 and the conductive column 202. In this way, the mesh structure 203 can improve the support effect of the conductive column 202, and the support material layer between the mesh structure 203 and the conductive column 202 can be used to release stress to a certain extent, thereby facilitating the stability of the adapter board 20.

[0063] Exemplarily, the wall thickness d2 of the support material layer 201 between the mesh structure 203 and the conductive pillars 202 is less than the wall thickness d1 of the mesh structure 203. In this way, the support material layer 201 between the mesh structure 203 and the conductive pillars 202 can be used to release stress to a certain extent, while the mesh structure 203 is not likely to have an insufficient support effect on the conductive pillars 202 due to the excessive wall thickness of the support material layer 201 between the mesh structure 203 and the conductive pillars 202.

[0064] Exemplarily, the detection contact 40, such as a plurality of probes, can be welded to the adapter plate 20, for example, by laser assisted bonding (LAB) (high temperature solder melting point (mp)>260°C). In the related art, increasing the laser power is prone to damage to the circuit substrate; therefore, the welding power needs to be controlled, but at this time, problems such as cold welding / false welding are prone to occur, and the welding strength is low. Since the probe has a certain force on the pad / bump of the chip during the test, it will affect the service life of subsequent tests. The adapter plate 20 provided in the embodiment of the present application has a greatly improved strength of the adapter plate 20 due to the addition of a supporting connection layer 210 (that is, equivalent to adding a fine structure to the adapter plate 20). In this way, when welding with the detection contact, it is not easy to damage the circuit substrate 10, and the welding strength is also correspondingly improved.

[0065] Four stacking methods of the supporting connection layer 210 and the interconnection layer 220 in the semiconductor device 100 are provided below.

[0066] Method 1: If Figure 1-Figure 3 As shown, the interconnection layer 220 is closer to the circuit substrate than the supporting connection layer 210 .

[0067] Based on the structure of the first method, the present application embodiment provides a method for preparing a semiconductor device, Figure 4-Figure 7 As shown, Figure 4-Figure 7 The structure diagram corresponding to some steps of a method for preparing a semiconductor device provided in an embodiment of the present application. The method comprises: S1, forming a transfer board 20 on a carrier 70, the transfer board 20 comprising a transfer circuit 92, that is, Figure 4 As shown; S2, forming a connecting piece on the adapter plate, that is, Figure 4 As shown; S3, the adapter plate 20 on the carrier plate 70 is transferred to one side of the ceramic plate 102, and the adapter plate 20 is connected to the ceramic plate 102 through the connecting member 30 (that is, the adapter plate 20 and the carrier plate 70 are first debonded (debonding), and then the adapter plate 20 and the ceramic plate 102 are combined), that is Figure 5 The state after the transfer board 20 and the carrier board are debonded is shown. Figure 6 The state after the adapter plate 20 and the ceramic plate are combined is shown; S4, a detection contact member 40 is formed on the side of the adapter plate 20 away from the ceramic plate 102, that is, Figure 7 As shown; S5, the surface of the ceramic plate 102 facing away from the adapter plate 20 is electrically connected to the printed circuit board 101; return Figure 2 and Figure 3As shown, the printed circuit board 101 and the ceramic board 102 constitute the circuit substrate 10, the circuit substrate 10 includes the detection circuit 91, the adapter board 20 includes the adapter circuit 92, and the detection contact 40 is electrically connected to the detection circuit 91 through the adapter circuit 92. In S5, the printed circuit board 101 can be directly connected to the mounting frame 60, and then the printed circuit board 101 is combined with the ceramic board 102 to form a circuit board 101 as shown in FIG. Figure 2 The structure shown. In this preparation method, since the adapter plate 20 is first formed on the carrier 70, the formed adapter plate 20 is then connected to the circuit substrate 10 through the adapter 30. Thus, compared with forming the adapter circuit directly on the circuit substrate 10 by photoforming, developing, and electroplating methods, the line width and line spacing of the adapter circuit in the adapter plate 20 can be set narrower and denser. Furthermore, when the detection contact 40 is set on the side of the adapter plate 20 away from the circuit substrate 10, the setting range of the detection contact 40 is larger. For example, the detection contact 40 can include a plurality of probes arranged at intervals, and the setting range and density of the probes can be increased. Thus, when the semiconductor device 100 is used as a probe card structure, the detection efficiency of the chip can be improved, and since the probe spacing can better match the chip pad spacing, it is also beneficial to improve the reliability during detection.

[0068] Method 2: If Figure 8 As shown, Figure 8 A structural diagram of another semiconductor device 100 provided in an embodiment of the present application, wherein the supporting connection layer 210 is closer to the circuit substrate 10 than the interconnection layer 220. The preparation method corresponding to the structure of the second mode can refer to the preparation method of the structure of the first mode, the difference being that when the adapter plate 20 is formed on the carrier 70, the formation of the interconnection layer 220 and the supporting connection layer 210 of the adapter plate 20 is reversed in the backward order. Moreover, in this structure, since the interconnection layer 220 is closer to the detection contact 40, in order to stably connect the detection contact 40 with the interconnection layer 220, a connection pad 80 may be further provided between the detection contact 40 and the interconnection layer 220, so that the stability of the detection contact 40 is better.

[0069] Method 3: If Fig. 9 As shown, Fig. 9 A structural diagram of another semiconductor device 100 provided in an embodiment of the present application, wherein the number of supporting connection layers 210 is two, and the interconnection layer 220 is sandwiched between the two supporting connection layers 210. The structure of the third method includes two supporting connection layers 210, so that the structure strength of the adapter plate 20 is higher and more reliable. In addition, the preparation method corresponding to the structure of the third method can still refer to the preparation method of the structure of the first method, the difference being that, on the basis of the first method, an additional supporting connection layer 210 is formed.

[0070] Method 4: If Fig.10 As shown, Fig.10 A structural diagram of another semiconductor device 100 provided in an embodiment of the present application, wherein the number of interconnection layers 220 is two, and the supporting connection layer 210 is sandwiched between the two interconnection layers. The structure of mode 4 includes two interconnection layers 220, which makes it easier to arrange the switching circuit, and thus it is easier to realize the detection function. In addition, the preparation method corresponding to the structure of mode 4 can refer to the preparation method of the structure of mode 2, the difference being that, on the basis of mode 2, an additional interconnection layer 220 is formed.

[0071] The following is a detailed description of the connection between the adapter board 20 and the circuit substrate 10. In the following connection, it is not limited whether the interconnection layer 220 or the supporting connection layer 210 is closest to the circuit substrate 10 in the adapter board 20.

[0072] In some embodiments, refer back to Figure 2 The connector 30 includes a plurality of solders 301 arranged at intervals. With such arrangement, the adapter plate can be soldered to the circuit substrate 10 using a plurality of solders 301, and the reliability after connection is high.

[0073] In some embodiments, refer back to Figure 2 The semiconductor device 100 further includes a filling material layer 50, which is filled between the circuit substrate 10 and the adapter board 20 and surrounds the connector 30. In this embodiment, by providing the filling material layer 50, the connector 30 (e.g., a plurality of solders 301) can be protected, for example, to prevent water vapor corrosion, etc., so that the connection stability between the adapter board 20 and the circuit substrate 10 can be improved.

[0074] Based on the semiconductor device 100, the present application embodiment provides a chip detection system 1000, such as Fig.11 As shown, Fig.11 The structure diagram of the chip detection system 1000 provided in the embodiment of the present application, the chip detection system 1000 includes a probe card structure 1002 and a probe station 1001, wherein the probe card structure 1002 is connected to the probe station 1001, the probe card structure 1002 includes the semiconductor device 100 in any of the previous embodiments, and the detection contact member 40 in the semiconductor device 100 includes a plurality of probes 401. The chip detection system provided in this embodiment has at least the advantages of high detection efficiency and high reliability due to the inclusion of the previous semiconductor device 100.

[0075] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A circuit substrate, an adapter board, a connector and a detection contact; the adapter board and the circuit substrate are stacked, the connector is located between the adapter board and the circuit substrate, the connector connects the adapter board and the circuit substrate, and the detection contact is located on a side of the adapter board away from the circuit substrate; The circuit substrate includes a detection circuit, the adapter board includes a transfer circuit, and the detection contact is electrically connected to the detection circuit through the transfer circuit.

2. The semiconductor device according to claim 1, wherein: The adapter plate comprises a supporting connection layer and an interconnection layer which are stacked; the interconnection layer comprises an interconnection line and an interlayer dielectric layer, and the interconnection line is embedded in the interlayer dielectric layer; the supporting connection layer comprises a conductive column and a supporting material layer, and the conductive column is embedded in the supporting material layer; The support material layer is stacked with the interlayer dielectric layer, the conductive pillar is electrically connected with the interconnection line; and the switching circuit includes the conductive pillar and the interconnection line.

3. The semiconductor device according to claim 2, characterized in that The material of the supporting material layer includes polymer material.

4. The semiconductor device according to claim 3, characterized in that Fillers are added into the polymer material.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: It also includes a mesh structure embedded in the support material layer, and each mesh hole of the mesh structure surrounds at least one of the conductive pillars.

6. The semiconductor device according to claim 5, characterized in that The supporting material layer is disposed between the mesh structure and the conductive pillars.

7. The semiconductor device according to claim 6, characterized in that The wall thickness of the support material layer between the mesh structure and the conductive pillars is smaller than the wall thickness of the mesh structure.

8. The semiconductor device according to any one of claims 5 to 7, characterized in that: The hardness of the mesh structure is greater than the hardness of the supporting material layer.

9. The semiconductor device according to any one of claims 5 to 8, characterized in that: The material of the network structure includes one or more combinations of silicon, glass, metal and ceramic.

10. The semiconductor device according to any one of claims 2 to 9, characterized in that: The line width of the interconnection line is greater than or equal to 2 microns and less than 50 microns, and the line spacing of the interconnection line is greater than or equal to 20 microns and less than 50 microns.

11. The semiconductor device according to any one of claims 2 to 10, characterized in that: The interlayer dielectric layer includes at least four stacked sub-film layers.

12. The semiconductor device according to any one of claims 2 to 11, characterized in that: The supporting connection layer is closer to the circuit substrate than the interconnection layer; Alternatively, the interconnection layer is closer to the circuit substrate than the supporting connection layer; Alternatively, the number of the supporting connection layers is two, and the interconnection layer is sandwiched between the two supporting connection layers; Alternatively, the number of the interconnection layers is two, and the supporting connection layer is sandwiched between the two interconnection layers.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that: The connecting member includes a plurality of solders arranged at intervals.

14. The semiconductor device according to any one of claims 1 to 13, characterized in that: It also includes a filling material layer, which is filled between the circuit substrate and the adapter board and surrounds the connector.

15. The semiconductor device according to any one of claims 1 to 14, characterized in that: It also includes a mounting frame connected to a side of the circuit substrate facing away from the adapter board.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that: The semiconductor device is a probe card structure, and the detection contact element includes a plurality of probes arranged at intervals.

17. A method for preparing a semiconductor device, characterized in that: include: forming a transfer board on the carrier board, wherein the transfer board includes a transfer circuit; forming a connector on the adapter plate; Transferring the adapter plate on the carrier plate to one side of the ceramic plate, and connecting the adapter plate to the ceramic plate through the connecting piece; forming a detection contact piece on a side of the adapter plate facing away from the ceramic plate; electrically connecting the surface of the ceramic board facing away from the adapter board to the printed circuit board; The printed circuit board and the ceramic board constitute a circuit substrate, the circuit substrate includes a detection circuit, the adapter board includes a transfer line, and the detection contact is electrically connected to the detection circuit through the transfer line.

18. A chip detection system, characterized in that: include: A probe station and a probe card structure connected together, wherein the probe card structure comprises a semiconductor device as claimed in any one of claims 1 to 16.

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