Circuit, phase shifter and system

Abstract

The invention provides a circuit. The circuit generates an output signal on an output node according to an input signal received from an input node; the circuit comprises a first path, a second path, a first switch and a second switch, the first path comprises a high-pass filter, the second path comprises another filter, and the first path and the second path are both connected between an input node and an output node in parallel. The first switch and the second switch respectively control whether the first path and the second path transmit an input signal to generate an output signal; wherein, at any specific moment, only one of the first switch and the second switch is configured to allow a corresponding path to transmit an input signal; the high-pass filter comprises a first capacitor and a first inductor; the first switch is connected between the first capacitance and the first inductance in the first path. The invention also provides a phase shifter and a system. According to the invention, the influence of parasitic capacitance in a high-pass filter which is used in parallel with another filter in a switching configuration can be reduced.

Description

[0001] Priority declaration

[0002] This patent application is related to and claims priority from Indian provisional patent application entitled “IMPROVED S11 PARAMETERS AND PHASE FLATTENNESS IN PHASE SHIFTERS” and having serial number

[0003] 202441009293, filed on February 12, 2024; agent file number AURA-356-INPR, this patent application introduces the entire contents of the Indian provisional patent application, but only to the parts that do not conflict with the description herein. Technical Field

[0004] The present invention relates to the technical field of high-pass filters (HPF), and in particular to a circuit, a phase shifter and a system. Background Art

[0005] A high-pass filter is a circuit that allows input signals with frequencies above a certain frequency (the cutoff frequency) to "pass" while blocking (attenuating) input signals with other frequencies. As we all know, high-pass filters are widely used in audio and image processing applications, amplifiers, phase shifters, and other fields.

[0006] In some applications, a high-pass filter is used in parallel with another filter in a switching configuration so that the input signal can take a path through either the high-pass filter or the other filter. Thus, the input signal may pass through the high-pass filter during some time periods and through the parallel path during other (non-overlapping) time periods.

[0007] High-pass filters are usually accompanied by undesirable parasitic capacitances, which can cause the output signal to deviate from the expected value. Therefore, it is necessary to reduce the impact of such parasitic capacitances. Summary of the invention

[0008] In view of the above, the present application provides a circuit, a phase shifter and a system to reduce the effect of parasitic capacitance in a high pass filter used in parallel with another filter in a switching configuration.

[0009] In a first aspect, the present application provides a circuit for generating an output signal at an output node based on an input signal received from an input node, the circuit comprising a first path having a high-pass filter, a second path having another filter, a first switch, and a second switch; the first path and the second path are both connected in parallel between the input node and the output node; the first switch and the second switch respectively control whether the first path and the second path transmit the input signal to generate the output signal; wherein, at any particular moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal; the high-pass filter comprises a first capacitor and a first inductor; the first switch is connected between the first capacitor and the first inductor in the first path.

[0010] In a second aspect, the present application provides a phase shifter, configured to receive an input signal from an input node and generate a phase-shifted signal at an output node, the phase shifter comprising:

[0011] A plurality of phase shifting units connected in series, wherein an output signal generated at an output node of one of the plurality of phase shifting units is used as an input signal at an input node of a next phase shifting unit;

[0012] The first phase shift unit among the plurality of phase shift units receives an input signal at its input node, and the last phase shift unit among the plurality of phase shift units generates the phase shift signal at its output node;

[0013] Each of the plurality of phase shifting units comprises:

[0014] a first inductor, a first capacitor, a first switch, a second inductor and a second switch on a first path between an input node of the phase shift unit and an output node of the phase shift unit, wherein the first capacitor and the second inductor form a high pass filter; and

[0015] a third switch, a second filter and a fourth switch on a second path between an input node of the phase shift unit and an output node of the phase shift unit;

[0016] Wherein, the first end of the first inductor is connected to the input node of the phase shift unit to receive the input signal of the phase shift unit, and the second end of the first inductor is connected to the first end of the first capacitor at a first node;

[0017] The first switch is connected between the second end of the first capacitor and a second node;

[0018] The second inductor is connected between the second node and a constant reference potential;

[0019] The second switch is connected between the second node and the output node of the phase shift unit;

[0020] The third switch is connected between the first node and the second filter;

[0021] The fourth switch is connected between the second filter and an output node of the phase shift unit.

[0022] In a third aspect, the present application provides a system, the system comprising:

[0023] a power supply for receiving an input voltage and generating a radio frequency signal;

[0024] a power distributor, configured to receive the radio frequency signal from the power supply and generate a plurality of distribution signals, wherein each distribution signal has a portion of the power of the radio frequency signal and has the same amplitude and phase;

[0025] a plurality of phase shifters, each phase shifter receiving a corresponding distribution signal and a control signal from among the plurality of distribution signals at a corresponding input node, and generating a corresponding phase-shifted signal at a corresponding output node;

[0026] A plurality of power amplifiers, each power amplifier receiving a corresponding phase-shifted signal among the plurality of phase-shifted signals and generating a corresponding amplified signal;

[0027] an antenna, comprising a combiner and a plurality of antenna elements, each antenna element receiving a corresponding one of the plurality of amplified signals, the combiner being configured to combine the plurality of amplified signals to generate a single transmit signal;

[0028] Each of the plurality of phase shifters comprises a plurality of phase shifting units connected in series, a first phase shifting unit among the plurality of phase shifting units receives a corresponding distribution signal among the plurality of distribution signals, and a last phase shifting unit among the plurality of phase shifting units is used to generate a corresponding phase shifting signal among the plurality of phase shifting signals;

[0029] Each of the plurality of phase shifting units comprises:

[0030] A first path, including a high pass filter;

[0031] a second path including another filter; the first path and the second path are both connected in parallel between the input node and the output node; and

[0032] A first switch and a second switch, respectively controlling whether the first path and the second path transmit the input signal to generate the output signal; wherein, at any specific moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal; the high-pass filter includes a first capacitor and a first inductor; the first switch is connected between the first capacitor and the first inductor in the first path.

[0033] The present application controls whether the first path and the second path transmit input signals to generate output signals through the first switch and the second switch respectively, and at any specific moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal. Through such a switch configuration, the parasitic capacitance can be placed in a path shared by the high-pass filter when it is connected in parallel with another filter, so that the influence of the parasitic capacitance can be eliminated or offset through a suitable matching network. Therefore, the present application can reduce the influence of the parasitic capacitance in the high-pass filter used in parallel with another filter in the switch configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Example embodiments of the present application will be described with reference to the following drawings.

[0035] Figure 1 It is a block diagram of the device provided in the embodiment of the present application.

[0036] Figure 2 It is a specific block diagram of a phase shifting unit of a phase shifter provided in one embodiment of the present application.

[0037] Figure 3A It is a specific block diagram of a phase shifting unit of a phase shifter provided in another embodiment of the present application.

[0038] Figure 3B It is a block diagram of a phase shift unit compensation network of a phase shifter provided in an embodiment of the present application.

[0039] Figure 4 It is a block diagram of a phase shifting unit of a phase shifter in the prior art.

[0040] Figure 5 It is a specific block diagram of the high-pass filter group provided in the embodiment of the present application.

[0041] Figure 6 It is a specific block diagram of a system that applies the above-mentioned device provided in an embodiment of the present application.

[0042] In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (or digit combination) in the corresponding reference numeral. DETAILED DESCRIPTION

[0043] 1. Overview

[0044] The present application provides a circuit that generates an output signal at an output node according to an input signal received from an input node. The circuit includes a first path and a second path, the first path includes a high-pass filter, the second path includes another filter, and the first path and the second path are both connected in parallel between the input node and the output node. The first switch and the second switch respectively control whether the first path and the second path transmit an input signal (i.e., whether the input signal is allowed to pass) to generate an output signal, and at any particular moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal (i.e., allow the input signal to pass). The high-pass filter includes a first capacitor and a first inductor, and the first switch is connected between the first capacitor and the first inductor in the first path.

[0045] By placing the first switch after the first capacitor, the effect of any parasitic capacitance associated with the first capacitor can be reduced.

[0046] According to another aspect of the present application, the first path includes a third switch, the second path includes a fourth switch, the third switch is connected between the first inductor and the output node, another filter is connected between the second switch and the fourth switch, and the fourth switch is connected between the other filter and the output node.

[0047] In one embodiment, the other filter is a part of the phase shifter, and the other filter is a low-pass filter (LPF). In another embodiment, the other filter is a part of a high-pass filter bank, that is, the other filter is another high-pass filter (that is, the other high-pass filter is not the same high-pass filter as the high-pass filter in the first path).

[0048] According to another aspect of the present application, a first compensation inductor is connected to an input node common to the first path and the second path. The first compensation inductor has a first inductance value, which is used to minimize the influence of a first parasitic capacitance related to the first capacitor on one or more characteristics of the high-pass filter, wherein the first parasitic capacitance exists between the input node and the first constant reference potential, and the first compensation inductor is connected in series with the first capacitor.

[0049] In one embodiment, a first conductive line is connected between the input node and the first compensation inductor, and the first conductive line has a first additional inductance value to further reduce the influence of the first parasitic capacitance.

[0050] According to another aspect of the present application, when the first logic signal is in a first state (e.g., a logic high level), the first switch and the third switch may be controlled to be in a closed state; and when the first logic signal is in a second state (e.g., a logic low level), the first switch and the third switch may be controlled to be in an open state. When the first logic signal is in the second state, the second switch and the fourth switch may be controlled to be in a closed state; and when the first logic signal is in the first state, the second switch and the fourth switch may be controlled to be in an open state.

[0051] The present application will be described below in conjunction with examples. However, it should be clear to those skilled in the art that the present application can be implemented in the absence of one or more specific details, or by other methods, components, materials, etc. In other cases, well-known structures, materials or operations are not shown in detail to avoid covering up the features of the present application. In addition, although for the sake of brevity, only some combinations of features / aspects are described herein, the described features / aspects can be practiced in various combinations.

[0052] 2. Embodiment of the device

[0053] Figure 1 It is a logic block diagram of a phase shifting unit of the device provided in an embodiment of the present application. Figure 1 The circuit structure of the phase shifter's phase shifter unit 100 is depicted. The phase shifter unit 100 is connected to the path 101, receives the input signal s-in from the path 101, and generates the output signal s-out on the path 109. The phase shifter unit 100 includes switches 115, 125, 145 and 155, a high pass filter 150 and a low pass filter 160.

[0054] In one embodiment, the input signal s-in (path 101) represents a radio frequency signal, generally a sine wave with a fixed frequency. The frequency of the input signal s-in (path 101) may be within a frequency range suitable for the target application, which is well known in the relevant art.

[0055] The high-pass filter 150 receives the input signal s-in on the path 101, performs high-pass filtering on the input signal s-in, and transmits the high-pass filtered signal through the path 109. High-pass filtering refers to a filtering operation that allows frequency components in a signal (here, the input signal s-in (path 101)) with a frequency higher than a selected cutoff frequency to pass, while frequency components with a frequency lower than the cutoff frequency are attenuated or "cut off". In addition, the high-pass filter can be implemented in a known manner.

[0056] The low-pass filter 160 receives the input signal s-in on the path 101, performs low-pass filtering on the input signal s-in, and transmits the low-pass filtered signal through the path 109. Low-pass filtering refers to a filtering operation that allows frequency components of a signal (here, the input signal s-in (path 101)) with a frequency lower than a selected cutoff frequency to pass, while frequency components with a frequency higher than the cutoff frequency are attenuated or "cut off". In addition, the low-pass filter can be implemented in a known manner.

[0057] Switches 115 and 145 can be used to select or deselect high-pass filter 150 to provide output signal s-out (path 109) under the control of control bit ph-sel-ib (path 113). Switches 125 and 155 can be used to select or deselect low-pass filter 160 to provide output signal s-out (path 109) under the control of control bit ph-sel-i (path 111). In one embodiment, switches 115, 125, 145 and 155 are single-pole single-throw complementary metal-oxide semiconductor (CMOS) switches. However, in other embodiments, switches 115, 125, 145 and 155 can also be implemented using other technologies, which is obvious to those skilled in the art. When switches 115 and 145 are closed, the input signal s-in (path 101) flows through the path including high-pass filter 150. On the other hand, when switches 125 and 155 are closed, the input signal s-in (path 101 ) flows through the path including the low-pass filter 160 .

[0058] Therefore, the phase shift unit 100 can be regarded as providing two parallel paths between the input node (path 101) and the output node (path 109) - one is a high-pass path including the high-pass filter 150, and the other is a low-pass path including the low-pass filter 160. The control bits ph-sel-ib (path 113) and ph-sel-i (path 111) control the closing and opening of the switches 115 / 145 and 125 / 155, respectively, to ensure that only one corresponding path is allowed to transmit the input signal s-in (path 101) at any particular time. In other words, during the time period when the switches 125 and 155 are closed by the control bit ph-sel-i (path 111), the input signal s-in (path 101) is transmitted through the low-pass filter 160. During the same time period, switches 115 and 145 are in the off state (controlled by control bit ph-sel-ib (path 113), ph-sel-ib is the complement of ph-sel-i (path 111)), so that the input signal s-in (path 101) will not be transmitted through the high-pass filter 150.

[0059] The output signal s-out (path 109) of the high-pass filter 150 / low-pass filter 160 will be phase-shifted (i.e., phase offset) relative to the input signal s-in (path 101), which is well known in the relevant technical field. However, the amplitude of the output signal s-out (path 109) is substantially equal to the amplitude of the input signal s-in (path 101). As is well known in the relevant technical field, the phase shift in the output signal is caused by the presence of reactive elements (capacitors and / or inductors) in the filter. The high-pass filter 150 will produce a positive phase shift, i.e., the phase of the output signal is ahead of the phase of the input signal; while the low-pass filter 160 will produce a negative phase shift, i.e., the phase of the output signal is behind the phase of the input signal.

[0060] The high pass filter 150 and the low pass filter 160 are each designed to provide a corresponding preset phase shift around their respective center frequencies. The desired phase shift in the output signal is achieved by switching between the high pass filter 150 and the low pass filter 160 .

[0061] Phase shifter 100 is part of a phase shifter (not shown) that is capable of providing a desired amount of phase shift around a center frequency. The operation of phase shifter 100 is controlled by a 1-bit signal (path 111). Thus, for example, in a 4-bit phase shifter, the four Figure 1 Similar phase shifting units are connected in series, but each phase shifting unit has a corresponding high pass filter 150 and a low pass filter 160 to provide a preset phase shift. Figure 1 The phase shifter is generated by a control module (not shown in the figure) and is controlled separately. Therefore, in a 4-phase shifter, 16 possible phase shift amounts can be obtained under the action of a 4-bit control signal. For example, the four phase shift units of the 4-phase shifter may provide phase shift amounts of 180 degrees, 90 degrees, 45 degrees, and 22.5 degrees, respectively. One of the high-pass path or the low-pass path is considered to provide a reference phase shift, while the other path provides the desired phase shift amount relative to the reference phase shift. This switch configuration for obtaining the desired phase shift range is used to improve phase flatness and impedance matching within a larger bandwidth. Phase flatness refers to the ability of a device to provide a flat phase shift (i.e., the phase error / deviation from the expected phase shift amount is minimized) within a frequency range, which is well known in the relevant technical field.

[0062] The parasitic capacitance in the high-pass filter and / or the low-pass filter may cause the output signal to deviate from the expected value. The present application aims to reduce the influence of such parasitic capacitance. Figure 2 and 3A -3B describes this in detail.

[0063] 3. Embodiment of a phase shift unit including a second-order high-pass filter

[0064] Figure 2 FIG. 2 is a specific block diagram of a phase shift unit 200 of a phase shifter provided in an embodiment of the present application. Figure 2 As shown, the phase shift unit 200 includes a compensation inductor 205 , a high-pass filter 250 , a low-pass filter 260 , and switches 215 , 225 , 245 , and 255 . Figure 2 The switches 215, 225, 245 and 255 in the Figure 1 The switches 115, 125, 145 and 155 in Figure 2 The signals 201, 209, 211 and 213 in correspond to Figure 1 For the sake of brevity, these switches and signals are not described in detail here. Node 299 represents the ground terminal.

[0065] The high pass filter 250 is a second order filter including a series capacitor 230 and a parallel inductor 240 . Figure 2 Also shown is a parasitic capacitor 232 associated with capacitor 230. In one embodiment, capacitor 230 is implemented using a metal-insulator-metal (MIM) or metal-oxide-metal (MOM) capacitor. Parasitic capacitor 232, for example, represents a bottom plate capacitor associated with capacitor 230, which is well known in the relevant art. The capacitance value of parasitic capacitor 232 may be approximately 1%-5% of the capacitance value of capacitor 230. Therefore, when the capacitance value of capacitor 230 increases, the capacitance value (absolute value) of parasitic capacitor 232 will also increase accordingly. In a high-pass filter 250 that provides a small phase shift, capacitor 230 may have a larger capacitance value. For example, for a high-pass filter 250 that can provide an 11.25 degree phase shift when the center frequency is approximately 2 GHz, the capacitance value of capacitor 230 may reach the order of tens of pico-Farads (pF).

[0066] The switch 215 is arranged after the capacitor 230 (on the signal path from the path 201 to the path 209), that is, connected between the series capacitor 230 and the parallel inductor 240. By arranging the switch 215 after the capacitor 230 instead of before (i.e., on the left side of the capacitor 230), it can be seen that the influence of the parasitic capacitor 232 is reflected at the node 203 shared by the high-pass path and the low-pass path. One advantage of the present application of setting the parasitic capacitor to be shared by the high-pass path and the low-pass path is that the influence of the parasitic capacitor 232 is eliminated or offset by adopting a suitable matching network (e.g., the compensation inductor 205), thereby reducing the impedance matching mismatch problem caused by the parasitic capacitor 232. An example of a third-order high-pass filter and its corresponding matching network will be introduced below.

[0067] 4. Embodiment of a phase shift unit including a third-order high-pass filter

[0068] Figure 3A FIG. 1 is a specific block diagram of a phase shift unit 300 of a phase shifter provided in an embodiment of the present application. Figure 3A As shown, the phase shift unit 300 includes compensation inductors 305 and 310 , a high-pass filter 350 , a low-pass filter 360 , and switches 315 , 325 , 345 , and 355 . Figure 3A The switches 315, 325, 345, and 355 in the Figure 1 Switches 115, 125, 145, 155 in Figure 3A The signals 301, 309, 311, and 313 in the diagram correspond to Figure 1 For the sake of brevity, the switches and signals 101, 109, 111, 113 are not described in detail here. Node 399 represents the ground terminal.

[0069] The high pass filter 350 is a third-order filter and includes series capacitors 330 and 370 and a parallel inductor 340 . Figure 3A Also illustrated are parasitic capacitances 332 and 372 associated with capacitances 330 and 370, respectively.

[0070] In the signal path, switch 315 is disposed after the series capacitor 330, and switch 345 is disposed before the series capacitor 370. Figure 2 As shown, due to the placement of switches 315 and 345 relative to capacitors 330 and 370, parasitic capacitors 332 and 372 are located in a path shared by the high-pass filter and the low-pass filter. The influence of parasitic capacitors 332 and 372 is reduced by using a matching network that can eliminate or offset the influence of parasitic capacitors 332 and 372.

[0071] Figure 3BA matching network (T-type matching network 375) provided by an embodiment of the present application is shown. The T-type matching network 375 includes compensation inductors 305 and 310. The capacitance value of capacitor 380 is equal to the sum of the capacitance values ​​of parasitic capacitors 332 and 372. The inductance values ​​of compensation inductors 305 and 310 can be calculated according to known methods for the desired source impedance ZS3 (path 319) and the desired load impedance ZL3 (path 329) (in RF applications, the values ​​of ZS3 and ZL3 are usually 50 ohms or 75 ohms).

[0072] Part of the inductance of the compensation inductors 305 and 310 may come from the connection lines (wires) in the layout (used to transmit signals between adjacent phase shifting units of the phase shifter), and any required additional inductance may be provided by using external inductors. The distribution of inductance between such wires and external components may be determined based on the simulation results of the wiring stage.

[0073] although Figure 2 and 3A The example embodiments describe a second-order high-pass filter and a third-order high-pass filter respectively, but the present application is also applicable to higher-order high-pass filters, and it is only necessary to adjust the positions of switches (for enabling the high-pass path) in all or selected parts of the phase shifter accordingly. This is obvious to those skilled in the art after reading the contents disclosed in this application.

[0074] Although the T-type matching network 375 includes a series inductor and a parallel capacitor, it will be apparent to those skilled in the art that in alternative embodiments, the matching network may be implemented differently (e.g., other types of L-type segments or L-type networks, depending on considerations such as frequency response type, bandwidth, ease of implementation, etc.).

[0075] When comparing the present application with conventional phase shifters, the characteristics and advantages of the present application will be more easily understood. Figure 4 Examples of existing phase shifters are briefly described.

[0076] 5. Phase shifting unit of existing phase shifter

[0077] Figure 4 The phase shifting unit 400 of the conventional phase shifter is shown, which includes a third-order high-pass filter 450, a low-pass filter 460, switches 415, 425, 445 and 455, and parasitic capacitors 432 and 472. In the phase shifting unit 400 of the conventional phase shifter, the switch 415 is connected before the series capacitor 430, and the switch 445 is connected after the series capacitor 470.

[0078] It is understandable that, due to the positional relationship between switches 415 and 445 in the conventional phase shift unit 400, parasitic capacitors 432 and 472 exist only in the high-pass path (including the high-pass filter 450), that is, they exist only when switches 415 and 445 are closed. When switches 425 and 455 are closed (that is, when signal 401 passes through the low-pass filter 460), the influence of parasitic capacitors 432 and 472 will not be apparent. In other words, parasitic capacitors 432 and 472 are not in the path shared by the high-pass filter and the low-pass filter, so their influence cannot be offset by a common matching network.

[0079] The parasitic capacitances 432 and 472 have a negative impact on the operation of the phase shift unit 400 at least in terms of phase flatness and impedance matching. Specifically, when the high-pass path is enabled, the parasitic capacitances 432 and 472 act as a low-pass network, thereby changing the absolute value and slope of the phase shift. Therefore, the phase flatness relative to the frequency is limited. In addition, the high-pass filter 450 (and the low-pass filter 460) are designed to provide a specific impedance matching within a specific frequency range. The presence of parasitic capacitances 432 and 472 changes the matched impedance, which in turn causes the value of the reflection coefficient (S11 parameter) to increase. Even if the inductance value of the parallel inductor 440 is adjusted for each high-pass filter or a matching network is added to offset the influence of the parasitic capacitance and reduce the reflection coefficient, this offset is only applicable to a single frequency. Therefore, such a solution will affect the phase flatness relative to the frequency.

[0080] By swapping the positions of the switches and series capacitors (such as Figure 2 and 3A As shown in FIG. 1 , the parasitic capacitor can be placed in a path shared by the high-pass filter and the low-pass filter. Since the capacitance value of the parasitic capacitor can be estimated based on the design value of the series capacitor in the high-pass filter in each phase shifting unit of the phase shifter, a matching network can be designed to eliminate or offset the effect of the parasitic capacitor on impedance matching.

[0081] Next, a circuit of another embodiment will be described, in which the influence of parasitic capacitance can be reduced by exchanging the switch positions (relative to the series capacitance in the high-pass filter).

[0082] 6. Example Implementation of High-Pass Filter Bank

[0083] Figure 5 is a specific block diagram of the high-pass filter group in the embodiment of the present application. Figure 5 As shown, the filter bank 500 includes high pass filters 550-1 to 550-N, switches 515-1 to 515-N, and switches 545-1 to 545-N.

[0084] The high-pass filters 550-1 to 550-N may be collectively referred to as 550 below, or individually referred to as their respective numbers, as required by the context. Similarly, the switches 515-1 to 515-N and 545-1 to 545-N may also be collectively referred to as 515 and 545, or individually referred to as their respective numbers, as required by the context. In addition, other modules / components / signals in the present application also follow similar naming conventions.

[0085] Each high pass filter 550 is a third order high pass filter including capacitors 530 and 570 connected in series and an inductor 540 connected in parallel. Figure 5 Also shown are parasitic capacitances 532 and 572 associated with capacitances 530 and 570, respectively. It should be noted that Figure 5 Only components relevant to understanding the present application are shown. It is understood that the high-pass filter bank 500 may include Figure 5 Although the embodiment of the present application shows a third-order high-pass filter, the content disclosed in the present application is also applicable to a higher-order high-pass filter, and only the circuit needs to be appropriately modified, which is obvious to those skilled in the art after reading the content disclosed in the present application.

[0086] Each high pass filter 550 receives an input signal s-in on path 501, performs a high pass filter on the input signal s-in, and transmits the filtered signal on path 509. Each pair of switches 515 and 545 can select or deselect the corresponding high pass filter 550 under the control of the corresponding high pass filter selection bits HPF-sel-1 to HPF-sel-N (path 511), thereby providing an output signal s-out (path 509).

[0087] By controlling switches 515-1 to 515-N and switches 545-1 to 545-N, the input signal s-in (path 501) passes through the corresponding high-pass filter 550 in a non-overlapping time period. Therefore, when switches 515-1 and 545-1 are closed, the input signal s-in (path 501) only flows through the path containing the high-pass filter 550-1. When switches 515-2 and 545-2 are closed, the input signal s-in (path 501) only flows through the path containing the high-pass filter 550-2. In one embodiment, switches 515-1 to 515-N and switches 545-1 to 545-N are implemented using CMOS switches. However, in other embodiments, the implementation of switches 515-1 to 515-N and switches 545-1 to 545-N may be different, which is obvious to those skilled in the art.

[0088] Control bits HPF-sel-1 (high pass filter selection bit-1, path 511-1) to HPF-sel-N (high pass filter selection bit-N, path 511-N) are used to control the closing and opening of switches 515 and 545, respectively, to ensure that only one corresponding high pass filter / path allows the input signal s-in (path 501) to pass through at any particular time. Control bit 511 can be generated by the control module ( Figure 5 not shown).

[0089] In each path, the switch 515 is arranged after the corresponding series capacitor 530 (i.e., connected between the capacitor 530 and the inductor 540), and the switch 545 is arranged before the corresponding series capacitor 570 (i.e., connected between the inductor 540 and the capacitor 570). It can be understood that due to this arrangement of the switches, the influence of the parasitic capacitances 532 and 572 is reflected at the node 503 shared by all paths. Therefore, by adopting a matching network, similar to the one for Figure 2 and Figure 3A By eliminating or counteracting the influence of the parasitic capacitances 532 and 572 in this way, the impedance matching mismatch problem caused by the parasitic capacitances 532 and 572 can be reduced.

[0090] Although the above description is in the phase shifter ( Figure 2 and Figure 3A-3B ) and a high-pass filter bank ( Figure 5 ), but the present application is generally also applicable to such a network implementation: in the network, a high-pass filter is connected in parallel with another filter and is equipped with a corresponding switch configuration to select either the high-pass filter and the other filter to transmit the input signal.

[0091] Therefore, the present application reduces the influence of parasitic capacitance in a high pass filter used in parallel with another filter in a switch configuration. The phase shifting units 200 and 300 of the phase shifter implemented in the above manner can be incorporated into a larger device or system, which is briefly described below.

[0092] 7. Embodiments of the device / system

[0093] Figure 6 is a specific block diagram of a device / system including the above-described phase shifting unit 200 / 300 in an embodiment of the present application. Figure 6As shown, the beamforming circuit 600 includes a power supply 610, a power divider 620, phase shifters 630-1 to 630-N, amplifiers 640-1 to 640-N, an antenna 660 including antenna units 650-1 to 650-N, and a combiner 665. The specific components / modules of the beamforming circuit 600 are shown only by way of example. However, the beamforming circuit 600 may include more or fewer components / modules. The beamforming circuit 600 may be part of a larger device / system, such as a user equipment (UE) or a next generation base station (gNB) in a communication system, a network relay, a radar and sonar system, etc.

[0094] The power supply 610 represents a radio frequency signal generator for generating a radio frequency signal 615 having a set of desired characteristics (eg, frequency, amplitude, phase, etc.).

[0095] The power divider 620 divides the RF signal 615 into a plurality of distribution signals 625 - 1 to 625 -N having the same (equal) amplitude and phase, and the power of these distribution signals is a portion of the power of the RF signal 615 .

[0096] Each phase shifter 630 receives the corresponding distribution signal 625 and generates a respective phase shifted signal 635. The amount of phase shift that each phase shifter 630 needs to provide can be specified by the control bit of the control signal 601. One or more phase shift units of the phase shifter 630 are implemented in the form of the phase shift unit 200 / 300 described in detail above.

[0097] Each amplifier 640 receives a corresponding phase-shifted signal 635 , amplifies the phase-shifted signal 635 , and sends the amplified phase-shifted signal to a corresponding antenna unit 650 .

[0098] Each antenna unit 650 receives the corresponding amplified phase-shifted signal 635, and the signals generated by the antenna units 650-1 to 650-N are combined (converged / merged) together through the combiner 665, so that the radiation pattern of each individual antenna unit 650 is superimposed with the radiation pattern of the adjacent antenna unit, thereby forming a desired radiation pattern. Therefore, the beamforming circuit 600 can control the signal 609 radiated by the antenna 660 to be directed in a desired direction. The desired direction is controlled by the control signal 601 mentioned above.

[0099] Thus, the present application reduces the effects of parasitic capacitance in a high pass filter used in parallel with another filter in a switching configuration.

[0100] 8. Conclusion

[0101] The "one embodiment", "one specific implementation" or similar expressions mentioned in the specification mean that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment", "in one implementation" and similar expressions appearing throughout the specification of this application may (but not necessarily) refer to the same embodiment.

[0102] exist Figure 1 , 2 , 3A, 5 and 6, although each endpoint / node is directly connected (i.e., "connected to") various other endpoints, it should be understood that there may be other components in the path that are suitable for a particular environment, and therefore, these connections can be considered to be "electrically coupled" to the connected endpoints.

[0103] In this application, the power supply and ground terminals are referred to as constant reference potentials.

[0104] Although various embodiments of the present application have been described above, it should be understood that these embodiments are provided only as examples and are not intended to set limitations. Therefore, the breadth and scope of the present application should not be limited to the limitations of any of the above-mentioned specific embodiments, but should only be defined according to the claims and their equivalents.

Claims

1. A circuit for generating an output signal at an output node based on an input signal received from an input node, characterized in that The circuit comprises: A first path, including a high pass filter; a second path including another filter; the first path and the second path are both connected in parallel between the input node and the output node; and A first switch and a second switch, respectively controlling whether the first path and the second path transmit the input signal to generate the output signal; wherein, at any specific moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal; the high-pass filter includes a first capacitor and a first inductor; the first switch is connected between the first capacitor and the first inductor in the first path.

2. The circuit according to claim 1, characterized in that The first path further includes a third switch, and the second path further includes a fourth switch; the third switch is connected between the first inductor and the output node; the other filter is connected between the second switch and the fourth switch, and the fourth switch is connected between the other filter and the output node.

3. The circuit according to claim 1, characterized in that The other filter is a low pass filter.

4. The circuit according to claim 1, characterized in that The further filter is a further high pass filter.

5. The circuit according to claim 2, characterized in that A first compensation inductor is connected to an input node common to the first path and the second path; the first compensation inductor has a first inductance value, which is used to minimize the influence of a first parasitic capacitance related to the first capacitor on one or more characteristics of the high-pass filter; wherein the first parasitic capacitance exists between the input node and a first constant reference potential, and the first compensation inductor is connected in series with the first capacitor.

6. The circuit according to claim 5, characterized in that A first conductive line is connected between the input node and the first compensation inductor, and the first conductive line has a first additional inductance value to further reduce the influence of the first parasitic capacitance.

7. The circuit according to claim 3, characterized in that When the first logic signal is in a first state, the first switch and the third switch are closed; when the first logic signal is in a second state, the first switch and the third switch are opened; wherein, when the first logic signal is in the second state, the second switch and the fourth switch are closed; when the first logic signal is in the first state, the second switch and the fourth switch are opened.

8. The circuit according to claim 2, characterized in that The high-pass filter further includes a second capacitor; the third switch is connected between the first inductor and the second capacitor, and the second capacitor is connected between the third switch and the output node.

9. The circuit according to claim 8, characterized in that A second compensation inductor is connected to an output node shared by the first path and the second path; the second compensation inductor has a second inductance value, which is used to minimize the influence of a second parasitic capacitance related to the second capacitor on one or more characteristics of the high-pass filter; wherein the second parasitic capacitance exists between the output node and the first constant reference potential, and the second compensation inductor is connected in series with the second capacitor.

10. The circuit according to claim 9, characterized in that A second wire is connected between the output node and the second compensation inductor, and the second wire has a second additional inductance value to further reduce the influence of the second parasitic capacitance.

11. The circuit according to claim 8, characterized in that The inductance value of the first inductor and the capacitance values ​​of the first capacitor and the second capacitor are preset to obtain expected values ​​of one or more characteristics of the high-pass filter; wherein the first path of the first path and the second path provides a reference phase shift between the input node and the output node, and the second path of the first path and the second path provides a desired phase shift between the input node and the output node relative to the reference phase shift.

12. The circuit according to claim 8, characterized in that The circuit is included in a phase shifter.

13. A phase shifter for receiving an input signal from an input node and generating a phase-shifted signal at an output node, characterized in that: The phase shifter comprises: A plurality of phase shifting units connected in series, wherein an output signal generated by each phase shifting unit at its output node is used as an input signal at an input node of the next phase shifting unit; The first phase shift unit among the plurality of phase shift units receives an input signal at its input node, and the last phase shift unit among the plurality of phase shift units generates the phase shift signal at its output node; Each of the plurality of phase shifting units comprises: a first inductor, a first capacitor, a first switch, a second inductor and a second switch on a first path between an input node of the phase shift unit and an output node of the phase shift unit, wherein the first capacitor and the second inductor form a high pass filter; and a third switch, a second filter and a fourth switch on a second path between an input node of the phase shift unit and an output node of the phase shift unit; Wherein, the first end of the first inductor is connected to the input node of the phase shift unit to receive the input signal of the phase shift unit, and the second end of the first inductor is connected to the first end of the first capacitor at a first node; The first switch is connected between the second end of the first capacitor and a second node; The second inductor is connected between the second node and a constant reference potential; The second switch is connected between the second node and the output node of the phase shift unit; The third switch is connected between the first node and the second filter; The fourth switch is connected between the second filter and an output node of the phase shift unit.

14. The phase shifter according to claim 13, characterized in that Each phase shift unit further comprises: A second capacitor connected between the second switch and an output node of the phase shift unit; and A third inductor is connected in series with the second capacitor to an output node of the phase shift unit.

15. A system, characterized in that: The system comprises: a power supply for receiving an input voltage and generating a radio frequency signal; a power distributor, configured to receive the radio frequency signal from the power supply and generate a plurality of distribution signals, wherein each distribution signal has a portion of the power of the radio frequency signal and has the same amplitude and phase; a plurality of phase shifters, each phase shifter receiving a corresponding distribution signal and a control signal from among the plurality of distribution signals at a corresponding input node, and generating a corresponding phase-shifted signal at a corresponding output node; A plurality of power amplifiers, each power amplifier receiving a corresponding phase-shifted signal among the plurality of phase-shifted signals and generating a corresponding amplified signal; An antenna comprising a combiner and a plurality of antenna elements, each antenna element receiving a corresponding amplified signal, wherein the combiner is used to combine the plurality of amplified signals to generate a single transmit signal; Each of the plurality of phase shifters comprises a plurality of phase shifting units connected in series, a first phase shifting unit among the plurality of phase shifting units receives a corresponding distribution signal among the plurality of distribution signals, and a last phase shifting unit among the plurality of phase shifting units is used to generate a corresponding phase shifting signal among the plurality of phase shifting signals; Each of the plurality of phase shifting units comprises: A first path, including a high pass filter; a second path including another filter; the first path and the second path are both connected in parallel between the input node and the output node; and A first switch and a second switch, respectively controlling whether the first path and the second path transmit the input signal to generate the output signal; wherein, at any specific moment, only one of the first switch and the second switch is configured to allow the corresponding path to transmit the input signal; the high-pass filter includes a first capacitor and a first inductor; the first switch is connected between the first capacitor and the first inductor in the first path.

16. The system of claim 15, wherein: The first path includes a third switch, and the second path includes a fourth switch; the third switch is connected between the first inductor and the output node; the other filter is connected between the second switch and the fourth switch, and the fourth switch is connected between the other filter and the output node.

17. The system of claim 15, wherein: The other filter is a low pass filter.

18. The system of claim 15, wherein: The another filter is another high pass filter.

19. The system of claim 16, wherein: A first compensation inductor is connected to an input node shared by the first path and the second path; the first compensation inductor has a first inductance value, which is used to minimize the influence of a first parasitic capacitance related to the first capacitor on one or more characteristics of the high-pass filter; wherein the first parasitic capacitance exists between the input node and a first constant reference potential, and the first compensation inductor is connected in series with the first capacitor; a first wire is connected between the input node and the first compensation inductor, and the first wire has a first additional inductance value, so as to further reduce the influence of the first parasitic capacitance.

20. The system of claim 16, wherein: The high-pass filter also includes a second capacitor, the third switch is connected between the first inductor and the second capacitor, and the second capacitor is connected between the third switch and the output node; wherein the second compensation inductor is connected to the output node shared by the first path and the second path; the second compensation inductor has a second inductance value, which is used to minimize the influence of a second parasitic capacitance related to the second capacitor on one or more characteristics of the high-pass filter; wherein the second parasitic capacitance exists between the output node and the first constant reference potential, and the second compensation inductor is connected in series with the second capacitor.

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