Low stray inductance GaN device and preparation method thereof

Abstract

The invention relates to the field of semiconductors, and discloses a low stray inductance GaN device and a preparation method thereof, and the GaN device comprises a lead frame pedestal, a GaN chip and an MOS chip. The lead frame base comprises a base body, and a grid electrode, a source electrode and a drain electrode of the GaN device, and a first conductive region on the base body is electrically connected with the source electrode of the GaN device; the GaN chip is arranged on the base body, and the front face of the GaN chip is provided with a first source electrode window and a drain electrode of the GaN chip. The drain electrode of the GaN chip is electrically connected with the drain electrode of the GaN device through a first metal wire, and the grid electrode of the GaN chip is electrically connected with the first conductive region; the MOS chip is arranged in the first source electrode window, and a back drain electrode of the MOS chip is electrically connected with the first source electrode window; a source electrode on the front face of the MOS chip is electrically connected with the first conductive region through a second metal wire, and a grid electrode on the front face of the MOS chip is electrically connected with a grid electrode of the GaN device through a third metal wire. The stray inductance of the GaN device can be effectively reduced, and the high-frequency performance of the GaN device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low stray inductance GaN device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), as the third-generation wide bandgap semiconductor material, has better properties than existing Si-based semiconductor devices in applications such as high temperature, high pressure, and especially high frequency.

[0003] GaN devices have extremely high switching speeds and are currently generally bonded using conventional wire bonding (such as Figure 1 The packaging style (as shown) will bring about a large package stray inductance, which will in turn cause significant switching losses, voltage overshoot and other problems, which limits the high-frequency application requirements of GaN devices.

[0004] Stray inductance is the equivalent inductance caused by the self-inductance and mutual inductance between different circuits. Stray inductance is an inherent property of a closed loop. Wherever current passes, there is stray inductance. Therefore, it can only be reduced through product packaging design and packaging technology but not completely eliminated.

[0005] Existing cascode (common source and common gate) structure GaN devices are generally made using traditional wire bonding (such as Figure 1-8 / 9 / 10 / 11 / 12) packaging, the stray inductance generated by the bonding wire is usually at the nanohenry (nH) level. Take the TO package of the lead bonding packaging type as an example, Figure 2 As shown, the large number of leads in this structure, the cumulative length of the leads is relatively long, and the effective area of ​​contact between the leads and the chip is relatively small, which will lead to a large package stray inductance L1+L2+L3>10nH, and then cause significant switching losses, voltage overshoot and other problems, which limits the application demand of the high-frequency characteristics of GaN devices.

[0006] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0007] The object of the present invention is to provide a low stray inductance GaN device and a preparation method thereof, which can effectively reduce the stray inductance of the GaN device and improve its high frequency performance.

[0008] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0009] A low stray inductance GaN device comprises a lead frame base, a GaN chip and a MOS chip;

[0010] The lead frame base comprises a base body, a gate of the GaN device, a source of the GaN device and a drain of the GaN device, and a first conductive area is provided on the base body, and the first conductive area is electrically connected to the source of the GaN device;

[0011] A first source window and a drain are provided on the front of the GaN chip, any point in the first source window is configured as the source of the GaN chip, and the size of the first source window is larger than that of the MOS chip;

[0012] The GaN chip is arranged on the base body, and the drain of the GaN chip is electrically connected to the drain of the GaN device through a first metal wire, and the gate of the GaN chip is electrically connected to the first conductive area;

[0013] The back side of the MOS chip is provided with a drain electrode, the front side of the MOS chip is provided with a gate electrode and a source electrode, the MOS chip is arranged in the first source electrode window, the back side of the MOS chip is bonded and connected to the first source electrode window, and the drain electrode of the MOS chip is electrically connected to the first source electrode window;

[0014] The source of the MOS chip is electrically connected to the first conductive region through a second metal wire, and the gate of the MOS chip is electrically connected to the gate of the GaN device through a third metal wire;

[0015] The number of the first metal wire, the second metal wire, the third metal wire and the fourth metal wire is one.

[0016] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the front side of the GaN chip is further provided with a first gate window and a first drain window, and any point in the first gate window is configured as a gate of the GaN chip, and any point in the first drain window is configured as a drain of the GaN chip;

[0017] A second source window and a second gate window are arranged on the front side of the MOS chip, any point in the second source window is configured as the source of the MOS chip, and any point in the second gate window is configured as the gate of the MOS chip;

[0018] The first gate window is electrically connected to the first conductive region through a fourth metal line, or the first gate window is electrically connected to the second source window through a fifth metal line.

[0019] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the first drain window is electrically connected to the drain of the GaN device through a first metal wire, and the first metal wire is connected to the first drain window through a double spot welding process; and / or,

[0020] The second source window is electrically connected to the drain of the GaN device through a second metal wire, and the second metal wire is connected to the second source window through a double spot welding process; and / or,

[0021] The second gate window is electrically connected to the gate of the GaN device through a third metal wire, and the third metal wire is connected to the second gate window through a double spot welding process; and / or,

[0022] The first gate window is electrically connected to the first conductive region through a fourth metal line, and the fourth metal line is connected to the first gate window through a double spot welding process.

[0023] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the first drain window is electrically connected to the drain of the GaN device through a first metal wire, and the first metal wire is connected to the first drain window through a double spot welding process; and / or,

[0024] The second source window is electrically connected to the drain of the GaN device through a second metal wire, and the second metal wire is connected to the second source window through a double spot welding process; and / or,

[0025] The second gate window is electrically connected to the gate of the GaN device through a third metal wire, and the third metal wire is connected to the second gate window through a double spot welding process; and / or,

[0026] The first gate window is electrically connected to the second source window through a fifth metal wire, and one end of the fifth metal wire is connected to the first gate window through a double spot welding process, and the other end of the fifth metal wire is connected to the second source window through a double spot welding process.

[0027] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first gate window is rectangular, the length of the first gate window is not less than 2000 μm, and the width of the first gate window is not less than 800 μm; and / or,

[0028] The first drain window is rectangular, the length of the first drain window is not less than 2000 μm, and the width of the first drain window is not less than 800 μm; and / or,

[0029] The second source window is rectangular, the length of the second source window is not less than 2000 μm, and the width of the second source window is not less than 800 μm; and / or,

[0030] The second gate window is rectangular, the length of the second gate window is not less than 2000 μm, and the width of the second gate window is not less than 800 μm.

[0031] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the cross section of the first metal wire is circular, and the diameter range of the cross section of the first metal wire is [100 μm, 600 μm]; and / or,

[0032] The cross section of the second metal wire is circular, and the diameter range of the cross section of the second metal wire is [100 μm, 600 μm]; and / or,

[0033] The cross section of the third metal wire is circular, and the diameter range of the cross section of the third metal wire is [100 μm, 600 μm]; and / or,

[0034] The cross section of the fourth metal wire is circular, and the diameter range of the cross section of the fourth metal wire is [100 μm, 600 μm]; and / or,

[0035] The cross section of the fifth metal wire is circular, and the diameter range of the cross section of the fifth metal wire is [100 μm, 600 μm].

[0036] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the cross section of the first metal wire is circular, and the diameter of the cross section of the first metal wire is 125 μm, 380 μm or 500 μm; and / or,

[0037] The cross section of the second metal wire is circular, and the diameter of the cross section of the second metal wire is 125 μm, 380 μm, or 500 μm; and / or,

[0038] The cross section of the third metal wire is circular, and the diameter of the cross section of the third metal wire is 125 μm, 380 μm, or 500 μm; and / or,

[0039] The cross section of the fourth metal wire is circular, and the diameter of the cross section of the fourth metal wire is 125 μm, 380 μm, or 500 μm; and / or,

[0040] The cross section of the fifth metal wire is circular, and the diameter of the cross section of the fifth metal wire is 125 μm, 380 μm, or 500 μm.

[0041] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, one or more of the first to fourth metal wires are three-welding-point metal wires;

[0042] A first welding spot, a second welding spot and a third welding spot are sequentially arranged on the three-welding spot metal wire, wherein the first welding spot and the second welding spot are arranged at one end of the three-welding spot metal wire, and the third welding spot is arranged at the other end of the three-welding spot metal wire;

[0043] A first shorted arc is provided between the first welding point and the second welding point, and a middle portion of the first shorted arc is bent toward a direction where welding surfaces of the first welding point and the second welding point are located;

[0044] A first elongated arc is provided between the second welding point and the third welding point, and the first elongated arc is bent in a direction away from the welding surfaces of the first welding point and the second welding point;

[0045] The length of the first elongated arc is greater than the length of the first shortened arc.

[0046] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the fifth metal wire is a four-welding-point metal wire;

[0047] The four-weld-point metal wire is provided with a fourth weld point, a fifth weld point, a sixth weld point and a seventh weld point in sequence, wherein the fourth weld point and the fifth weld point are provided at one end of the four-weld-point metal wire, and the sixth weld point and the seventh weld point are provided at the other end of the four-weld-point metal wire;

[0048] A second shortened arc is provided between the fourth welding point and the fifth welding point, and a middle portion of the second shortened arc is bent toward the direction of the welding surfaces of the fourth welding point and the fifth welding point;

[0049] A third shortened arc is provided between the sixth welding point and the seventh welding point, and a middle portion of the third shortened arc is bent toward a direction where welding surfaces of the sixth welding point and the seventh welding point are located;

[0050] A second elongated arc is provided between the fifth welding point and the sixth welding point, and the second elongated arc is bent in a direction away from the welding surfaces of the fifth welding point and the sixth welding point;

[0051] The length of the second elongated arc is greater than the length of the second shortened arc, and the length of the second elongated arc is greater than the length of the third shortened arc.

[0052] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the first metal wire, the second metal wire, the third metal wire, the fourth metal wire and the fifth metal wire are made of aluminum or aluminum alloy.

[0053] According to another aspect of the present invention, the present invention provides a method for preparing a low stray inductance GaN device, comprising the following steps:

[0054] Designing a lead frame base, which includes a base body, a gate of a GaN device, a source of the GaN device, and a drain of the GaN device, wherein a first conductive area is provided on the base body, and the first conductive area is electrically connected to the source of the GaN device;

[0055] Design and tape out GaN chips and MOS chips; wherein the back side of the GaN chip is insulated, and the front side is provided with a first source window, a first gate window and a first drain window, and the size of the first source window is larger than the size of the MOS chip; the back side of the MOS chip is provided with its drain, and the front side of the MOS chip is provided with a second source window and a second gate window;

[0056] Pasting the back side of the GaN chip onto the base body;

[0057] Adhere the back side of the MOS chip to the first source window by using conductive glue, and the drain of the MOS chip is electrically connected to the first source window through the conductive glue;

[0058] Using a first metal wire to electrically connect the first drain window to the drain of the GaN device, using a second metal wire to electrically connect the second source window to the first conductive region, and using a third metal wire to electrically connect the second gate window to the first gate window;

[0059] The first gate window is electrically connected to the first conductive region by using a fourth metal line, or the first gate window is electrically connected to the second source window by using a fifth metal line.

[0060] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first metal wire is connected to the first drain window by a double spot welding process; and / or,

[0061] The second metal wire is connected to the second source window by a double spot welding process; and / or,

[0062] The third metal wire is connected to the second gate window by a double spot welding process; and / or,

[0063] The fourth metal wire is connected to the first gate window through a double spot welding process.

[0064] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first metal wire is connected to the first drain window by a double spot welding process; and / or,

[0065] The second metal wire is connected to the second source window by a double spot welding process; and / or,

[0066] The third metal wire is connected to the second gate window by a double spot welding process; and / or,

[0067] One end of the fifth metal wire is connected to the first gate window through a double spot welding process, and the other end of the fifth metal wire is connected to the second source window through a double spot welding process.

[0068] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the cross-sections of the first metal wire, the second metal wire, the third metal wire, the fourth metal wire and the fifth metal wire are all circular, and the diameter of the circle is in the range of [100μm, 600μm].

[0069] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0070] a. The low stray inductance GaN device provided by the present invention has a structure that combines a two-dimensional stacked die leadless packaging process with a novel thick aluminum wire double solder joint welding process, which not only reduces the number of leads, but also shortens the lead length, and increases the effective contact area between the lead and the chip, thereby effectively reducing the stray inductance of the GaN device, improving the high-frequency characteristic application requirements of the product, so that the product performance of the GaN device can meet the market demand for the high-frequency characteristic application of the product, promote product market promotion and iteration, and has advancedness and high economic value;

[0071] b. The GaN device provided by the present invention uses a fifth metal wire with double solder joints at both ends to directly interconnect the gate electrode of the GaN chip and the source electrode of the MOS chip, which is not only shorter in length but also more reliable in connection performance, further effectively reducing stray inductance, so that the comprehensive inductance of the GaN device is effectively reduced to less than 1nH;

[0072] c. One end of the three-welding-point metal wire and both ends of the four-welding-point metal wire provided by the present invention have a short arc with the middle part close to the welding surface. For example, the first short arc can support the first welding point and the second welding point on both sides thereof, and can be connected against the welded surface, which not only increases the contact area between the metal wire and the electrode and reduces the stray inductance, but also can improve the reliability of the connection between the metal wire and the electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0074] Figure 1 A schematic diagram of the structure of a GaN device in the prior art;

[0075] Figure 2 A circuit diagram of parasitic inductance in a GaN device in the prior art;

[0076] Figure 3 A schematic diagram of the structure of a MOS chip provided for an exemplary embodiment of the present invention;

[0077] Figure 4 A schematic structural diagram of a GaN chip provided for an exemplary embodiment of the present invention;

[0078] Figure 5 A schematic structural diagram of a first GaN device provided for an exemplary embodiment of the present invention;

[0079] Figure 6 A schematic diagram of the structure of a three-weld point metal wire provided for an exemplary embodiment of the present invention;

[0080] Figure 7 A schematic structural diagram of a second GaN device provided as an exemplary embodiment of the present invention;

[0081] Figure 8 A schematic structural diagram of a four-welding-point metal wire provided for an exemplary embodiment of the present invention.

[0082] The reference numerals include: 1-lead frame base, 10-base body, 11-gate of GaN device, 12-source of GaN device, 13-drain of GaN device, 2-GaN chip, 21-first source window, 22-first gate window, 23-first drain window, 3-MOS chip, 31-second source window, 32-second gate window, 41-first metal wire, 411-first solder joint, 412-second solder joint, 413-third solder joint, 414- 14-first shorted arc, 415-first elongated arc, 42-second metal wire, 43-third metal wire, 44-fourth metal wire, 45-fifth metal wire, 451-fourth welding point, 452-fifth welding point, 453-sixth welding point, 454-seventh welding point, 455-second shorted arc, 456-third shorted arc, 457-second elongated arc, 5-conductive glue, 61-first copper wire, 62-second copper wire, 63-third copper wire, 64-fourth copper wire, 65-fifth copper wire. DETAILED DESCRIPTION

[0083] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0084] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0085] like Figure 1 As shown, the existing Cascode structure GaN device usually arranges GaN chip 2 and MOS chip 3, usually SiMOSFET chip, in parallel on the lead frame base, and uses copper wires to electrically connect the GaN chip, MOS chip and the electrodes of the GaN device by bonding wires. Figure 1As shown, a first copper wire 61 is used to electrically connect the drain of the GaN chip to the drain 13 of the GaN device, a second copper wire 62 is used to electrically connect the drain of the GaN chip to the drain of the GaN device, a third copper wire 63 is used to electrically connect the gate of the MOS chip 3 to the gate 11 of the GaN device, a fourth copper wire 44 is used to electrically connect the source of the GaN chip 2 to the source of the GaN device, and a fifth copper wire 65 is used to electrically connect the source of the GaN chip 2 to the drain of the MOS chip 3.

[0086] In order to ensure the reliability of the connection, it is often necessary to use multiple copper wires to bond two electrodes that need to be electrically connected, such as Figure 1 As shown, the number of the first copper wire 61, the second copper wire 62 and the fifth copper wire 65 is usually 3. Therefore, the existing Cascode structure GaN device generally requires more than a dozen copper wires to realize the electrical connection between the electrodes. Not only is the process complicated and the cost high, but also the large number of copper wires with long leads will bring a large package stray inductance to the GaN device, which will then cause significant switching losses, voltage overshoot and other problems, limiting the high-frequency application performance of the GaN device.

[0087] Based on the shortcomings of the prior art, in one embodiment of the present invention, a low stray inductance GaN device is provided. Figures 3 to 5 , the GaN device includes a lead frame base 1, a GaN chip 2 and a MOS chip 3;

[0088] The lead frame base 1 includes a base body 10, a gate 11 of a GaN device, a source 12 of the GaN device, and a drain 13 of the GaN device. A first conductive region is provided on the base body 10, and the first conductive region is electrically connected to the source 12 of the GaN device.

[0089] The front side of the GaN chip 2 is provided with a first source window 21 and a drain thereof, any point in the first source window 21 is configured as the source of the GaN chip 2, and the size of the first source window 22 is larger than the size of the MOS chip 3, so that the MOS chip 3 can be configured in the first source window 22;

[0090] The GaN chip 2 is disposed on the base body 10, and the drain of the GaN chip 2 is electrically connected to the drain 13 of the GaN device through a first metal wire 41, and the gate of the GaN chip 2 is electrically connected to the first conductive area;

[0091] The back side of the MOS chip 3 is provided with its drain, the front side of the MOS chip 3 is provided with its gate and source, the MOS chip 3 is arranged in the first source window 21, and the back side of the MOS chip 3 is attached and connected to the first source window 21, and the drain of the MOS chip 3 is electrically connected to the first source window 21;

[0092] The source of the MOS chip 3 is electrically connected to the first conductive region through a second metal wire 42, and the gate of the MOS chip 3 is electrically connected to the gate 11 of the GaN device through a third metal wire 43;

[0093] The number of the first metal wire 41 , the second metal wire 42 , the third metal wire 43 and the fourth metal wire 44 are all one.

[0094] In one embodiment of the present invention, a low stray inductance GaN device is provided. Figures 3 to 5 In this embodiment, if Figure 4 As shown, the back side of the GaN chip 2 is insulated, and the front side is also provided with a first gate window 22 and a first drain window 23, any point in the first gate window 22 is configured as the gate of the GaN chip 2, and any point in the first drain window 23 is configured as the drain of the GaN chip 2;

[0095] like Figure 3 As shown, a second source window 31 and a second gate window 32 are arranged on the front side of the MOS chip 3 , any point in the second source window 31 is configured as the source of the MOS chip 3 , and any point in the second gate window 32 is configured as the gate of the MOS chip 3 .

[0096] See also Figure 5 , the first gate window 22 is electrically connected to the first conductive region through a fourth metal line 44. The first drain window 23 is electrically connected to the drain 13 of the GaN device through a first metal line 41, and the first metal line 41 is connected to the first drain window 23 through a double spot welding process. The second source window 31 is electrically connected to the drain 13 of the GaN device through a second metal line 42, and the second metal line 42 is connected to the second source window 31 through a double spot welding process. The second gate window 32 is electrically connected to the gate 11 of the GaN device through a third metal line 43, and the third metal line 43 is connected to the second gate window 32 through a double spot welding process. The first gate window 22 is electrically connected to the first conductive region through a fourth metal line 44, and the fourth metal line 44 is connected to the first gate window 22 through a double spot welding process.

[0097] In the prior art, the specifications (cross-sectional diameter) of the copper wire (circular cross section) used for GaN devices are usually thick copper wire and thin copper wire. The specifications of the thick copper wire in the range of 30-50μm are generally 30 / 33 / 38 / 42 / 50μm, etc.; the specifications of the thin copper wire in the range of 10-25μm are 10 / 12.5 / 15 / 17.5 / 20 / 22.5 / 25μm, etc. In this embodiment, the first metal wire 41, the second metal wire 42, the third metal wire 43 and the fourth metal wire 44 are aluminum wires that are thicker than conventional copper wires. The cross-sections of the first metal wire 41, the second metal wire 42, the third metal wire 43 and the fourth metal wire 44 are circular, and the diameter range of the circular cross section is [100μm, 600μm]. More preferably, the diameter range of the cross section of the first metal wire 41, the second metal wire 42, the third metal wire 43 and the fourth metal wire 44 is [125μm, 500μm]. More preferably, the diameter of the cross section of the first metal wire 41 , the second metal wire 42 , the third metal wire 43 and the fourth metal wire 44 is 380 μm.

[0098] The first metal wire 41, the second metal wire 42, the third metal wire 43 and the fourth metal wire 44 are thickened and connected to the target electrode using a double spot welding process. The number of the first metal wire 41, the second metal wire 42, the third metal wire 43 and the fourth metal wire 44 are all 1, and the material is preferably aluminum or aluminum alloy.

[0099] Therefore, the present invention combines the structure of the two-dimensional stacked die leadless packaging process with the thick aluminum wire Double stitch new welding process, which not only reduces the number of leads, but also shortens the lead length and increases the effective contact area between the lead and the chip, thereby effectively reducing the stray inductance of the GaN device and improving the high-frequency characteristics of the product. The product performance of the GaN device can meet the market demand for the application of high-frequency characteristics of the product, and promote product market promotion and iteration. This application is advanced and has high economic value.

[0100] In this embodiment, the first metal wire 41 to the fourth metal wire 44 are all three-welding-point metal wires. Figure 6 The three-weld point metal wire is sequentially provided with a first weld point 411, a second weld point 412 and a third weld point 413. The first weld point 411 and the second weld point 412 are provided at one end of the three-weld point metal wire, and the third weld point 413 is provided at the other end of the three-weld point metal wire.

[0101] A first shorted arc 414 is provided between the first solder joint 411 and the second solder joint 412, and the middle portion of the first shorted arc 414 is bent in the direction of the soldering surfaces of the first solder joint 411 and the second solder joint 412. This structure can not only enhance the reliability of the connection between the three-soldering point metal wire and its soldering object (taking the first metal wire 41 as an example, the soldering object of the double soldering point end of the first metal wire 41 is the drain of the GaN chip, i.e., the first drain window 23) through the double soldering point method, but also the middle portion of the first shorted arc 414 is in contact with the soldering surface, thereby the first shorted arc 414 can play a role in supporting the first solder joint 411 and the second solder joint 412 on both sides thereof, further improving the reliability of the connection between the three-soldering point metal wire and the soldering object.

[0102] A first elongated arc 415 is provided between the second welding spot 412 and the third welding spot 413, and the first elongated arc 415 is bent in a direction away from the welding surfaces of the first welding spot 411 and the second welding spot 412. The length of the first elongated arc 415 is greater than the length of the first shortened arc 414, and is specifically set according to actual needs.

[0103] In addition, the first solder joint 411, the second solder joint 412 and the third solder joint 413 are all in an arc shape that is concave in a direction away from the soldering surface, thereby increasing the amount of solder between the solder joint and the soldered surface, thereby improving the reliability of soldering.

[0104] In view of the use of thicker metal wires and to ensure the reliability of the connection, the GaN device provided by the present invention enlarges the PAD windows of the electrodes G, D, and S of the GaN chip and the PAD windows of S and G of the MOS chip. The size of the first source window is not less than the size of the MOS chip.

[0105] The first gate window 22, the first drain window 23, and the second source window 31 are rectangular, and the second gate window 32 is preferably rectangular, the length of the rectangle is not less than 2000μm, and the width of the rectangle is not less than 800μm (the length and width of the original window size of each electrode are usually less than or equal to 150μm). That is, the length of the first gate window 22 is not less than 2000μm, and the width of the first gate window 22 is not less than 800μm; the first drain window 23 is rectangular, the length of the first drain window 23 is not less than 2000μm, and the width of the first drain window 23 is not less than 800μm; the second source window 31 is rectangular, the length of the second source window 31 is not less than 2000μm, and the width of the second source window 31 is not less than 800μm; the second source window 31 is rectangular, the length of the second gate window 32 is not less than 2000μm, and the width of the second gate window 32 is not less than 800μm.

[0106] Of course, in other embodiments, such as Figure 5 As shown, the second gate window 32 is in the shape of a first rectangle, the second source window 31 and the second gate window 32 form a second rectangle as a whole, and the second source window 31 is a special-shaped shape obtained by removing a corner of the second rectangle from the first rectangle.

[0107] By enlarging the PAD windows of the electrodes G, D, and S of the GaN chip and the PAD windows of S and G of the MOS chip, the length of the metal wire is further shortened. The length of the copper wire in the existing GaN device is usually 3-8 mm. In this application, the length of the metal wire ranges from 2.5 to 4 mm, thereby further reducing the impurity inductance of the GaN device.

[0108] In addition, the present invention uses thick metal wires instead of thick copper wires, which can pass a larger current and improve the on-resistance parameter of the GaN device, that is, reduce Ron.

[0109] As shown in Tables 1 to 4 below, it can be seen from Table 1 that other parameters are the same. Compared with the prior art that uses 38μm copper wire to electrically connect the electrodes in the GaN device, the high-frequency performance of using a 250μm single aluminum wire to electrically connect the electrodes in the GaN device is better. It can be seen from Table 2 that other parameters are the same. Compared with the use of a 380μm single aluminum wire to electrically connect the electrodes in the GaN device, the high-frequency performance of using a 380μm single aluminum wire to electrically connect the electrodes in the GaN device is better. It can be seen from Table 2 that other parameters are the same. By enlarging the electrode window and shortening the length of the aluminum wire, the high-frequency performance of the GaN device is better.

[0110] Table 1

[0111] Lead material and specification Lead length range High frequency characteristics Example 1 250μm aluminum wire 3-4mm Better Comparative Example 1 (Prior Art) 38μm copper wire 3-8mm /

[0112] Table 2

[0113] Lead material and specification Lead length range High frequency characteristics Example 1 250μm aluminum wire 3-4mm / Example 2 380μm aluminum wire 3-4mm Better

[0114] Table 3

[0115] First gate window length × width Lead length range High frequency characteristics Example 1 1000μm*400μm 3-4mm / Example 3 2000μm*800μm 2.5-4mm Better

[0116] The method for preparing a low stray inductance GaN device provided in this embodiment firstly forms a required large window on the S electrode of the GaN chip through a mask layer, and simultaneously forms a window size that meets the new thick aluminum wire bonding process on the D electrode and G electrode regions of the GaN, and then grows metal layers such as Ti / Al / Ti / Au layer by layer on the surface of the window region to form a surface ohmic electrode layer, and forms a final product through processes such as packaging, thick aluminum double welding point process and plastic sealing.

[0117] The preparation method comprises the following steps:

[0118] Designing a lead frame base, which includes a base body, a gate of a GaN device, a source of the GaN device, and a drain of the GaN device, wherein a first conductive area is provided on the base body, and the first conductive area is electrically connected to the source of the GaN device;

[0119] Design and tape-out of GaN chips and MOS chips; wherein the back of the GaN chip is insulated, and a first source window, a first gate window and a first drain window are arranged on the front thereof, and the size of the first source window is larger than that of the MOS chip; the back of the MOS chip is arranged with its drain, and the front of the MOS chip is arranged with a second source window and a second gate window; compared with the original GaN chip, the PAD windows of the electrodes G, D and S of the GaN chip provided in this embodiment are larger, so that WB bonding of thicker and fewer wires (Wire), realization of complex process technologies such as multi-weld point bonding, and shortening of the wire length, bring about a leap in the wire welding quality and high-frequency performance of GaN device products; in particular, the thick aluminum wire double-weld point technology of the first metal wire 41 reduces the stray inductance L3;

[0120] The back side of the GaN chip is attached to the base body. Since the back side of the GaN chip is insulated, the electrical isolation between the GaN electrode and the LF base body is achieved.

[0121] Adhere the back side of the MOS chip to the first source window by using conductive glue, and the drain of the MOS chip is electrically connected to the first source window through the conductive glue;

[0122] The first drain window is electrically connected to the drain of the GaN device using a first metal wire, and the first metal wire is connected to the first drain window by a double spot welding process;

[0123] The second source window is electrically connected to the first conductive region by a second metal wire, and the second metal wire is connected to the second source window by a double spot welding process;

[0124] The second gate window is electrically connected to the first gate window by a third metal wire, and the third metal wire is connected to the second gate window by a double spot welding process; such a two-dimensional stacked die packaging process simultaneously realizes the leadless packaging direct coupling of the drain of the Si MOSFET and the source of the GaN, thereby reducing the stray inductance L1, so that L1 approaches zero;

[0125] The first gate window is electrically connected to the first conductive region by a fourth metal wire, and the fourth metal wire is connected to the first gate window by a double spot welding process.

[0126] Molding process realizes EMC resin encapsulation and protection of products (die, wire, lead frame base, etc.), realizing electrical insulation and heat dissipation functions of products;

[0127] Electroplating, cutting into single products, electrical performance testing to eliminate defective products, to obtain low stray inductance GaN device finished products with qualified electrical performance and appearance.

[0128] The order of the above steps can be adjusted according to actual needs, and the protection scope of the present application is not limited to the order of the steps of the above preparation method.

[0129] In another embodiment of the present invention, a low stray inductance GaN device is provided. Figure 7 The GaN device provided in this embodiment is different from the GaN device provided in the above embodiment in that: the first gate window 22 is not electrically connected to the first conductive region through the fourth metal wire 44, but the first gate window 22 is electrically connected to the second source window 31 through the fifth metal wire 45, and one end of the fifth metal wire 45 is connected to the first gate window 22 through a double spot welding process, and the other end of the fifth metal wire 45 is connected to the second source window 31 through a double spot welding process. Preferably, the material of the fifth metal wire is also aluminum or aluminum alloy.

[0130] In this embodiment, the cross section of the fifth metal wire 45 is preferably circular, and the diameter range of the cross section of the fifth metal wire 45 is [100 μm, 600 μm]. More preferably, the diameter range of the cross section of the fifth metal wire 45 is [125 μm, 500 μm]. More preferably, the diameter of the cross section of the fifth metal wire 45 is 380 μm.

[0131] See also Figure 8 The fifth metal wire 45 is a four-weld-point metal wire. The four-weld-point metal wire is sequentially provided with a fourth weld point 451, a fifth weld point 452, a sixth weld point 453 and a seventh weld point 454, wherein the fourth weld point 451 and the fifth weld point 452 are provided at one end of the four-weld-point metal wire, and the sixth weld point 453 and the seventh weld point 454 are provided at the other end of the four-weld-point metal wire.

[0132] A second shortened arc 455 is provided between the fourth welding spot 451 and the fifth welding spot 452, and the middle portion of the second shortened arc 455 is bent toward the direction of the welding surfaces of the fourth welding spot 451 and the fifth welding spot 452. A third shortened arc 456 is provided between the sixth welding spot 453 and the seventh welding spot 454, and the middle portion of the third shortened arc 456 is bent toward the direction of the welding surfaces of the sixth welding spot 453 and the seventh welding spot 454.

[0133] A second elongated arc 457 is disposed between the fifth welding spot 452 and the sixth welding spot 453, and the second elongated arc 457 is bent in a direction away from the welding surfaces of the fifth welding spot 452 and the sixth welding spot 453. The length of the second elongated arc 457 is greater than the length of the second shortened arc 455, and the length of the second elongated arc 457 is greater than the length of the third shortened arc 456.

[0134] In the GaN device provided in this embodiment, the fifth metal wire 45 is not only shorter in length but also more reliable in connection performance than the fourth metal wire 44 in the above embodiment. In the above embodiment, the GaN-G electrode is connected to the base through the fourth metal wire, and the MOS-S electrode is connected to the LF base through the second metal wire. The LF base is used as a medium to realize the conduction between the GaN-G electrode and the MOS-S electrode. Due to factors such as the lead length, the L2 inductor is introduced. This embodiment is based on the above embodiment and realizes the direct interconnection and conduction between the GaN-G electrode and the MOS-S electrode by improving the bonding process ( Figure 7 The fifth metal wire) effectively reduces Figure 2 The L2 inductance in the L1 / L2 is reduced to zero. The GaN device provided in this embodiment can effectively reduce the L1 / L2 / L3 combined inductance to less than 1nH. Among them, the fifth metal wire is PAD-PAD, which is a key technology of the new welding process with thick aluminum wire double stitch (Double stitch) and innovative use.

[0135] The method for preparing a low stray inductance GaN device provided in this embodiment includes the following steps:

[0136] Designing a lead frame base, which includes a base body, a gate of a GaN device, a source of the GaN device, and a drain of the GaN device, wherein a first conductive area is provided on the base body, and the first conductive area is electrically connected to the source of the GaN device;

[0137] Design and tape-out of GaN chips and MOS chips; wherein the back of the GaN chip is insulated, and a first source window, a first gate window and a first drain window are arranged on the front thereof, and the size of the first source window is larger than that of the MOS chip; the back of the MOS chip is arranged with its drain, and the front of the MOS chip is arranged with a second source window and a second gate window; compared with the original GaN chip, the PAD windows of the electrodes G, D and S of the GaN chip provided in this embodiment are larger, so that WB bonding of thicker and fewer wires (Wire), realization of complex process technologies such as multi-weld point bonding, and shortening of the wire length, bring about a leap in the wire welding quality and high-frequency performance of GaN device products; in particular, the thick aluminum wire double-weld point technology of the first metal wire 41 reduces the stray inductance L3;

[0138] The back side of the GaN chip is attached to the base body. Since the back side of the GaN chip is insulated, the electrical isolation between the GaN electrode and the LF base body is achieved.

[0139] Adhere the back side of the MOS chip to the first source window by using conductive glue 5, and the drain of the MOS chip is electrically connected to the first source window through the conductive glue;

[0140] The first drain window is electrically connected to the drain of the GaN device using a first metal wire, and the first metal wire is connected to the first drain window by a double spot welding process;

[0141] The second source window is electrically connected to the first conductive region by a second metal wire, and the second metal wire is connected to the second source window by a double spot welding process;

[0142] The second gate window is electrically connected to the first gate window by a third metal wire, and the third metal wire is connected to the second gate window by a double spot welding process; such a two-dimensional stacked die packaging process simultaneously realizes the leadless packaging direct coupling of the drain of the Si MOSFET and the source of the GaN, thereby reducing the stray inductance L1, so that L1 approaches zero;

[0143] The first gate window and the second source window are electrically connected by a fifth metal wire, and one end of the fifth metal wire is connected to the first gate window by a double spot welding process, and the other end of the fifth metal wire is connected to the second source window by a double spot welding process, so that the L2 inductance approaches zero; preferably, the material of the fifth metal wire is also aluminum or aluminum alloy;

[0144] Molding process realizes EMC resin encapsulation and protection of products (die, wire, lead frame base, etc.), realizing electrical insulation and heat dissipation functions of products;

[0145] Electroplating, cutting into single products, electrical performance testing to eliminate defective products, to obtain low stray inductance GaN device finished products with qualified electrical performance and appearance.

[0146] The order of the above steps can be adjusted according to actual needs, and the protection scope of the present application is not limited to the order of the steps of the above preparation method.

[0147] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0148] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A low stray inductance GaN device, characterized in that: It comprises a lead frame base (1), a GaN chip (2) and a MOS chip (3); The lead frame base (1) comprises a base body (10), a gate electrode (11) of a GaN device, a source electrode (12) of the GaN device and a drain electrode (13) of the GaN device, and a first conductive region is provided on the base body (10), and the first conductive region is electrically connected to the source electrode (12) of the GaN device; A first source window (21) and a drain thereof are provided on the front side of the GaN chip (2); any point in the first source window (21) is configured as the source of the GaN chip (2); and the size of the first source window (22) is larger than that of the MOS chip (3); The GaN chip (2) is arranged on the base body (10), and the drain of the GaN chip (2) is electrically connected to the drain (13) of the GaN device via a first metal wire (41), and the gate of the GaN chip (2) is electrically connected to the first conductive region; The back side of the MOS chip (3) is provided with its drain electrode, the front side of the MOS chip (3) is provided with its gate electrode and source electrode, the MOS chip (3) is arranged in the first source electrode window (21), the back side of the MOS chip (3) is bonded and connected to the first source electrode window (21), and the drain electrode of the MOS chip (3) is electrically connected to the first source electrode window (21); The source electrode of the MOS chip (3) is electrically connected to the first conductive region via a second metal wire (42), and the gate electrode of the MOS chip (3) is electrically connected to the gate electrode (11) of the GaN device via a third metal wire (43); The number of the first metal wire (41), the second metal wire (42), the third metal wire (43) and the fourth metal wire (44) is one.

2. The low stray inductance GaN device according to claim 1, characterized in that: The front surface of the GaN chip (2) is also provided with a first gate window (22) and a first drain window (23); any point in the first gate window (22) is configured as a gate of the GaN chip (2), and any point in the first drain window (23) is configured as a drain of the GaN chip (2); A second source window (31) and a second gate window (32) are arranged on the front side of the MOS chip (3); any point in the second source window (31) is configured as a source of the MOS chip (3), and any point in the second gate window (32) is configured as a gate of the MOS chip (3); The first gate window (22) is electrically connected to the first conductive region via a fourth metal line (44), or the first gate window (22) is electrically connected to the second source window (31) via a fifth metal line (45).

3. The low stray inductance GaN device according to claim 2, characterized in that: The first drain window (23) is electrically connected to the drain (13) of the GaN device via a first metal wire (41), and the first metal wire (41) is connected to the first drain window (23) via a double spot welding process; and / or, The second source window (31) is electrically connected to the drain (13) of the GaN device via a second metal wire (42), and the second metal wire (42) is connected to the second source window (31) via a double spot welding process; and / or, The second gate window (32) is electrically connected to the gate (11) of the GaN device via a third metal wire (43), and the third metal wire (43) is connected to the second gate window (32) via a double spot welding process; and / or, The first gate window (22) is electrically connected to the first conductive region via a fourth metal wire (44), and the fourth metal wire (44) is connected to the first gate window (22) via a double spot welding process.

4. The low stray inductance GaN device according to claim 2, characterized in that: The first drain window (23) is electrically connected to the drain (13) of the GaN device via a first metal wire (41), and the first metal wire (41) is connected to the first drain window (23) via a double spot welding process; and / or, The second source window (31) is electrically connected to the drain (13) of the GaN device via a second metal wire (42), and the second metal wire (42) is connected to the second source window (31) via a double spot welding process; and / or, The second gate window (32) is electrically connected to the gate (11) of the GaN device via a third metal wire (43), and the third metal wire (43) is connected to the second gate window (32) via a double spot welding process; and / or, The first gate window (22) is electrically connected to the second source window (31) through a fifth metal wire (45), and one end of the fifth metal wire (45) is connected to the first gate window (22) through a double spot welding process, and the other end of the fifth metal wire (45) is connected to the second source window (31) through a double spot welding process.

5. The low stray inductance GaN device according to claim 2, characterized in that: The first gate window (22) is rectangular, the length of the first gate window (22) is not less than 2000 μm, and the width of the first gate window (22) is not less than 800 μm; and / or, The first drain window (23) is rectangular, the length of the first drain window (23) is not less than 2000 μm, and the width of the first drain window (23) is not less than 800 μm; and / or, The second source window (31) is rectangular, the length of the second source window (31) is not less than 2000 μm, and the width of the second source window (31) is not less than 800 μm; and / or, The second gate window (32) is rectangular, the length of the second gate window (32) is not less than 2000 μm, and the width of the second gate window (32) is not less than 800 μm.

6. The low stray inductance GaN device according to claim 2, characterized in that: The cross section of the first metal wire (41) is circular, and the diameter of the cross section of the first metal wire (41) is in the range of [100 μm, 600 μm]; and / or, The cross section of the second metal wire (42) is circular, and the diameter of the cross section of the second metal wire (42) is in the range of [100 μm, 600 μm]; and / or, The cross section of the third metal wire (43) is circular, and the diameter range of the cross section of the third metal wire (43) is [100 μm, 600 μm]; and / or, The cross section of the fourth metal wire (44) is circular, and the diameter range of the cross section of the fourth metal wire (44) is [100 μm, 600 μm]; and / or, The cross section of the fifth metal wire (45) is circular, and the diameter range of the cross section of the fifth metal wire (45) is [100 μm, 600 μm].

7. The low stray inductance GaN device according to claim 6, characterized in that: The cross section of the first metal wire (41) is circular, and the diameter of the cross section of the first metal wire (41) is 125 μm, 380 μm, or 500 μm; and / or, The cross section of the second metal wire (42) is circular, and the diameter of the cross section of the second metal wire (42) is 125 μm, 380 μm, or 500 μm; and / or, The cross section of the third metal wire (43) is circular, and the diameter of the cross section of the third metal wire (43) is 125 μm, 380 μm, or 500 μm; and / or, The cross section of the fourth metal wire (44) is circular, and the diameter of the cross section of the fourth metal wire (44) is 125 μm, 380 μm, or 500 μm; and / or, The cross section of the fifth metal wire (45) is circular, and the diameter of the cross section of the fifth metal wire (45) is 125 μm, 380 μm, or 500 μm.

8. The low stray inductance GaN device according to claim 2, characterized in that: One or more of the first metal wire (41) to the fourth metal wire (44) are three-weld point metal wires; The three-welding-point metal wire is provided with a first welding point (411), a second welding point (412) and a third welding point (413) in sequence, wherein the first welding point (411) and the second welding point (412) are provided at one end of the three-welding-point metal wire, and the third welding point (413) is provided at the other end of the three-welding-point metal wire; A first shortened arc (414) is provided between the first welding point (411) and the second welding point (412), and a middle portion of the first shortened arc (414) is bent in the direction of the welding surfaces of the first welding point (411) and the second welding point (412); A first elongated arc (415) is provided between the second welding point (412) and the third welding point (413), and the first elongated arc (415) is bent in a direction away from the welding surfaces of the first welding point (411) and the second welding point (412); The length of the first elongated arc (415) is greater than the length of the first shortened arc (414).

9. The low stray inductance GaN device according to claim 2, characterized in that: The fifth metal wire (45) is a four-weld point metal wire; The four-welding-point metal wire is provided with a fourth welding point (451), a fifth welding point (452), a sixth welding point (453) and a seventh welding point (454) in sequence, wherein the fourth welding point (451) and the fifth welding point (452) are provided at one end of the four-welding-point metal wire, and the sixth welding point (453) and the seventh welding point (454) are provided at the other end of the four-welding-point metal wire; A second shortened arc (455) is provided between the fourth welding point (451) and the fifth welding point (452), and a middle portion of the second shortened arc (455) is bent in the direction of the welding surfaces of the fourth welding point (451) and the fifth welding point (452); A third shortened arc (456) is provided between the sixth welding point (453) and the seventh welding point (454), and a middle portion of the third shortened arc (456) is bent in the direction of the welding surfaces of the sixth welding point (453) and the seventh welding point (454); A second elongated arc (457) is provided between the fifth welding point (452) and the sixth welding point (453), and the second elongated arc (457) is bent in a direction away from the welding surfaces of the fifth welding point (452) and the sixth welding point (453); The length of the second elongated arc (457) is greater than the length of the second shortened arc (455), and the length of the second elongated arc (457) is greater than the length of the third shortened arc (456).

10. The low stray inductance GaN device according to claim 2, characterized in that: The first metal wire (41), the second metal wire (42), the third metal wire (43), the fourth metal wire (44) and the fifth metal wire (45) are made of aluminum or aluminum alloy.

11. A method for preparing a low stray inductance GaN device, characterized in that: The following steps are involved: Designing a lead frame base, which includes a base body, a gate of a GaN device, a source of the GaN device, and a drain of the GaN device, wherein a first conductive area is provided on the base body, and the first conductive area is electrically connected to the source of the GaN device; Design and tape out GaN chips and MOS chips; wherein the back side of the GaN chip is insulated, and the front side is provided with a first source window, a first gate window and a first drain window, and the size of the first source window is larger than the size of the MOS chip; the back side of the MOS chip is provided with its drain, and the front side of the MOS chip is provided with a second source window and a second gate window; Pasting the back side of the GaN chip onto the base body; Adhere the back side of the MOS chip to the first source window by using conductive glue, and the drain of the MOS chip is electrically connected to the first source window through the conductive glue; Using a first metal wire to electrically connect the first drain window to the drain of the GaN device, using a second metal wire to electrically connect the second source window to the first conductive region, and using a third metal wire to electrically connect the second gate window to the first gate window; The first gate window is electrically connected to the first conductive region by using a fourth metal line, or the first gate window is electrically connected to the second source window by using a fifth metal line.

12. The method for preparing a low stray inductance GaN device according to claim 11, characterized in that: The first metal wire is connected to the first drain window by a double spot welding process; and / or, The second metal wire is connected to the second source window by a double spot welding process; and / or, The third metal wire is connected to the second gate window by a double spot welding process; and / or, The fourth metal wire is connected to the first gate window through a double spot welding process.

13. The method for preparing a low stray inductance GaN device according to claim 11, characterized in that: The first metal wire is connected to the first drain window by a double spot welding process; and / or, The second metal wire is connected to the second source window by a double spot welding process; and / or, The third metal wire is connected to the second gate window by a double spot welding process; and / or, One end of the fifth metal wire is connected to the first gate window through a double spot welding process, and the other end of the fifth metal wire is connected to the second source window through a double spot welding process.

14. The method for preparing a low stray inductance GaN device according to claim 11, characterized in that: The cross sections of the first metal wire, the second metal wire, the third metal wire, the fourth metal wire and the fifth metal wire are all circular, and the diameter of the circle is in the range of [100 μm, 600 μm].

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