Light-emitting diode chip, chip set thereof and display module

Abstract

The invention provides a light-emitting diode chip, a chip set thereof and a display module, and relates to the technical field of semiconductors, the light-emitting diode chip comprises an N-type electrode, a P-type electrode and a light-emitting layer arranged between the N-type electrode and the P-type electrode; the light-emitting layer is electrically conducted with the N-type electrode and the P-type electrode respectively; the light-emitting layer comprises at least one pixel sub-group, and the pixel sub-group comprises at least two sub-pixels; the at least two sub-pixels comprise a first sub-pixel with a first light-emitting wavelength and a second sub-pixel with a second light-emitting wavelength, and the first light-emitting wavelength is not equal to the second light-emitting wavelength. According to the invention, the sizes of the light-emitting diode chips and the RGB full-color chip set can be flexibly adjusted, and the transfer number and transfer difficulty in mass transfer are reduced, so that the problems of process, yield and cost represented by mass transfer in ultra-high-density pixel display products can be solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a chipset thereof, and a display module. Background Art

[0002] In semiconductor lighting technology, light emitting diodes (LEDs) are light emitting devices that convert electrical energy into light energy. They have the advantages of energy saving and environmental protection, long service life and high luminous efficiency. They are widely used in many fields such as indication, display, decoration, and lighting.

[0003] LED is used in the display field. Ultra-high-density display products based on micro-light-emitting diodes (micro LEDs) usually use three independent single chips to form a pixel unit, that is, three single-core monochrome sub-pixels form a pixel unit. The number of chips in the micro LED is huge and the chip size is small. In the process of micro LED, a mass transfer process is required.

[0004] However, the above-mentioned micro LED manufacturing process has problems such as high process difficulty, low yield and high cost. Summary of the invention

[0005] The present application provides a light-emitting diode chip and its chipset, and a display module, which can flexibly adjust the size of the light-emitting diode chip and the RGB full-color chipset, reduce the transfer quantity and transfer difficulty in mass transfer, and thus overcome the process, yield and cost problems represented by mass transfer in ultra-high-density pixel display products.

[0006] In a first aspect, the present application provides a light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; the light-emitting layer comprises at least one pixel subgroup, and the pixel subgroup comprises at least two sub-pixels;

[0007] The at least two sub-pixels include a first sub-pixel having a first light-emitting wavelength and a second sub-pixel having a second light-emitting wavelength, and the first light-emitting wavelength is different from the second light-emitting wavelength.

[0008] In a second aspect, the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array;

[0009] Two adjacent LED chips include a first LED chip and a second LED chip, and a part of the sub-pixels of the first LED chip and a part of the sub-pixels of the second LED chip together form a pixel unit.

[0010] In a third aspect, the present application provides a display module, including a display module, a driving backplane and the above-mentioned light-emitting diode chipset, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

[0011] The light-emitting diode chip and its chipset, and display module provided by the present application are arranged by placing the light-emitting layer between the N-type electrode and the P-type electrode, and electrically conducting with both, so that the electrons provided by the N-type electrode and the holes provided by the P-type electrode are combined in the light-emitting layer and excite the light-emitting material in the light-emitting layer to emit light. The light-emitting layer includes at least one pixel subgroup, and the pixel subgroup includes at least two sub-pixels with different luminous wavelengths. The present application adopts a single-core dual-color multi-sub-pixel arrangement, that is, at least two sub-pixels are used to form a pixel subgroup, and an RGB full-color pixel unit is formed by the arrangement of the pixel subgroups, thereby forming an RGB full-color chipset. The present application can flexibly adjust the size of the light-emitting diode chip and the RGB full-color chipset, reduce the difficulty of the transfer operation in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming the process, yield and cost issues represented by mass transfer in ultra-high-density pixel display products.

[0012] The construction of the present application and its other inventive objectives and beneficial effects will be more clearly understood through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 A top view of a first light emitting diode chip provided in an embodiment of the present application;

[0015] Figure 2 A cross-sectional view of a first light emitting diode chip provided in an embodiment of the present application;

[0016] Figure 3 A top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0017] Figure 4 A cross-sectional view of a second light-emitting diode chip provided in an embodiment of the present application;

[0018] Figure 5 A top view of a third light emitting diode chip provided in an embodiment of the present application;

[0019] Figure 6 A cross-sectional view of a third light-emitting diode chip provided in an embodiment of the present application;

[0020] Figure 7 A cross-sectional view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0021] Figure 8 A cross-sectional view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0022] Fig. 9 A cross-sectional view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0023] Fig.10 A cross-sectional view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0024] Fig.11 A cross-sectional view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0025] Fig.12 A cross-sectional view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0026] Fig.13 A cross-sectional view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0027] Fig.14 A cross-sectional view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0028] Fig.15 A cross-sectional view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0029] Fig.16 A top view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0030] Fig.17 A top view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0031] Fig.18 A top view of a fifteenth light-emitting diode chip provided in an embodiment of the present application;

[0032] Fig.19 A top view of a sixteenth light-emitting diode chip provided in an embodiment of the present application;

[0033] Fig. 20 A top view of a seventeenth light-emitting diode chip provided in an embodiment of the present application;

[0034] Fig.21A top view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0035] Fig. 22 A cross-sectional view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0036] Fig.23 A top view of a nineteenth light-emitting diode chip provided in an embodiment of the present application;

[0037] Fig.24 A top view of the twentieth light-emitting diode chip provided in the embodiment of the present application;

[0038] Fig.25 A top view of a twenty-first light-emitting diode chip provided in an embodiment of the present application;

[0039] Fig.26 A schematic diagram of a first integrated structure of a light emitting diode chip provided in an embodiment of the present application;

[0040] Fig. 27 A schematic diagram of a second integrated structure of a light emitting diode chip provided in an embodiment of the present application;

[0041] Fig.28 A schematic diagram of a third integrated structure of a light emitting diode chip provided in an embodiment of the present application;

[0042] Fig.29 A schematic diagram of a fourth integrated structure of a light emitting diode chip provided in an embodiment of the present application;

[0043] Fig.30 A structural flow chart of the first and second methods for preparing a light-emitting diode chip provided in an embodiment of the present application;

[0044] Fig.31 A structural flow chart of the third and fourth methods for preparing the light-emitting diode chip provided in the embodiments of the present application;

[0045] Fig.32 A structural flow chart of a fifth method for preparing a light-emitting diode chip provided in an embodiment of the present application;

[0046] Fig.33 A structural flow chart of a sixth method for preparing a light-emitting diode chip provided in an embodiment of the present application;

[0047] Fig.34 A schematic diagram of the first structure of a light emitting diode chipset provided in an embodiment of the present application;

[0048] Fig.35 A second structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0049] Fig.36 A third structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0050] Fig.37 A fourth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0051] Fig.38 A fifth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0052] Fig.39 A sixth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0053] Fig.40 A seventh structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0054] Fig.41 An eighth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0055] Fig.42 A ninth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0056] Fig.43 A tenth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0057] Fig.44 This is a schematic diagram of the eleventh structure of the light emitting diode chipset provided in the embodiment of the present application;

[0058] Fig.45 A twelfth structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0059] Fig.46 A thirteenth structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0060] Fig.47 This is a fourteenth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0061] Fig.48 A fifteenth structural schematic diagram of a light emitting diode chipset provided in an embodiment of the present application;

[0062] Fig.49 A sixteenth structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0063] Fig.50 A seventeenth structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0064] Fig.51 A first dimension diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0065] Fig.52 A second dimension diagram of the light emitting diode chipset provided in an embodiment of the present application;

[0066] Fig.53 A third dimension diagram of the light emitting diode chipset provided in the embodiment of the present application;

[0067] Fig.54 A fourth dimension diagram of the light emitting diode chipset provided in an embodiment of the present application;

[0068] Fig.55 A fifth dimension diagram of the light emitting diode chipset provided in the embodiment of the present application;

[0069] Fig.56 A schematic diagram of the structure of a light-emitting diode chip with a color conversion layer provided in an embodiment of the present application;

[0070] Fig.57 This is a schematic diagram of the eighteenth structure of the light emitting diode chipset provided in the embodiment of the present application;

[0071] Fig.58 A nineteenth structural schematic diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0072] Fig.59 A schematic diagram of a first structure of a display module provided in an embodiment of the present application;

[0073] Fig.60 A second structural schematic diagram of the display module provided in an embodiment of the present application.

[0074] Description of reference numerals:

[0075] 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P-type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, binding layer; 112, color conversion layer; 113, protective layer; 114, first dimming layer; 115, second dimming layer; 116, isolation material; 200, driving backplane; 201, driving substrate; 202, driving unit. DETAILED DESCRIPTION

[0076] In LED display products, three single-core monochrome single-sub-pixel chips are usually used to form a pixel unit. The size of a single chip in ultra-high-density display products represented by micro LED is relatively small, and the number of chips that make up the display product is relatively large. In the manufacturing process of display products, micro LED chips need to be grown on wafers, and then transferred to a specific substrate through mass transfer technology to complete the binding assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is difficult, the number of operations is numerous, and the operation alignment requirements on the substrate are high. As a result, the manufacturing process of micro LED display products is difficult, the yield is low, the production cycle is long, and the cost is high.

[0077] In related technologies, in LED display products, several chips are packaged together through the MIP (Micro LED in Package) packaging process to form an integrated chipset that can emit multiple wavelengths. The traditional MIP packaging process is suitable for LED display products with pixel sizes greater than 0.3 mm. Due to the limitations of existing mass transfer technology capabilities, the MIP packaging process requires that the single-core monochrome single-sub-pixel chip used must be larger, that is, the sub-pixel size is larger. A single chipset is usually an RGB pixel unit, and there are a large number of chips and chipsets used on the application side.

[0078] The light-emitting diode chip and its chipset, and display module provided by the present application are arranged by placing the light-emitting layer between the N-type electrode and the P-type electrode, and electrically conducting the two, so that the electrons provided by the N-type electrode and the holes provided by the P-type electrode are combined in the light-emitting layer, and the light-emitting material in the light-emitting layer is excited to emit light. The light-emitting layer includes at least one pixel subgroup, and the pixel subgroup includes at least two sub-pixels with different luminous wavelengths. In this way, the present application adopts a single-core dual-color multi-sub-pixel arrangement, that is, at least two sub-pixels are used to form a pixel subgroup, and an RGB full-color pixel unit is formed by the arrangement of the pixel subgroups, thereby forming an RGB full-color chipset. The present application can flexibly adjust the size of the light-emitting diode chip and the RGB full-color chipset, reduce the difficulty of the transfer operation in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming the process, yield and cost issues represented by mass transfer in ultra-high-density pixel display products.

[0079] Compared with the related art that integrates several chips together to form an integrated chipset that emits multiple wavelengths, the related art needs to overcome the process difficulties of integrating multiple chips, so the process is more difficult, the yield is lower, and the cost is higher. This application directly obtains dual-color multi-sub-pixels in a single light-emitting diode chip, which has a simpler process, less technical difficulty, and lower cost.

[0080] Furthermore, the LED chipset formed by the single-core dual-color multi-sub-pixel LED chip of the present application can flexibly adjust the size of the LED chip under the conditions of the same light-emitting area and the same pixel density (Pixels Per Inch, PPI for short) while ensuring a small sub-pixel size. At the same time, the number of LED chips is greatly reduced, thereby overcoming the problems of difficult preparation process, low product yield and high preparation cost, and helping to promote the mass production of mini LED and micro LED as soon as possible.

[0081] When the single-core dual-color multi-sub-pixel LED chip of the present application is used to form a full-color integrated chipset (for example, three 2*n combination chips form a chipset), n*2 pixel units can be obtained. When combined with the backplane, the chipset used is 1 / 2n of the traditional MIP package, which greatly reduces the preparation time, reduces the process and raw material costs, and greatly improves the yield. Furthermore, the pixel size applicable to the full-color integrated package of the present application can be flexibly adjusted and can be much smaller than the pixel size applicable to the traditional MIP process.

[0082] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0083] In this application, some nouns can be understood as follows:

[0084] Sub pixel (SP): A single blue light pixel, a single green light pixel, or a single red light pixel is called a sub pixel. In this patent, a sub pixel can also be a single arbitrary wavelength.

[0085] Pixel subgroup (PSG): a group of sub-pixels.

[0086] Pixel unit (PU for short): a unit that includes three primary colors: blue sub-pixel, green sub-pixel and red sub-pixel.

[0087] Single-core monochrome single-sub-pixel chip: A single light-emitting diode chip can only emit one wavelength of light and contains only one sub-pixel, such as one blue light sub-pixel, one green light sub-pixel, or one red light sub-pixel.

[0088] Single-core monochrome multi-sub-pixel chip: A single chip can only emit one wavelength of light, but contains more than or equal to 2 sub-pixels, such as 2 red sub-pixels, 3 red sub-pixels, or more red sub-pixels.

[0089] Single-core dual-color multi-sub-pixel chip; a single chip can emit 2 different wavelengths of light and contains greater than or equal to 2 sub-pixels, such as 1 red sub-pixel + 1 green sub-pixel, 2 red sub-pixels + 2 green sub-pixels, multiple blue sub-pixels + multiple red sub-pixels, multiple green sub-pixels + multiple blue sub-pixels, or multiple green sub-pixels + multiple red sub-pixels.

[0090] Light-emitting diode chip (C for short): a solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode.

[0091] Light-emitting diode chipset (Chip group, referred to as CG): consists of two or more single-core dual (single) color multi-sub-pixel chips, including one or more pixel units.

[0092] Display mini block (DMB) is a display device formed by electrically connecting a light-emitting diode chipset to a driver backplane.

[0093] In a first aspect, the present application provides a light emitting diode chip, referring to Figure 1-Figure 22 As shown, the light-emitting diode chip includes an N-type electrode, a P-type electrode and a light-emitting layer arranged between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; the light-emitting layer includes at least one pixel subgroup, and the pixel subgroup includes at least two sub-pixels; the at least two sub-pixels include a first sub-pixel with a first light-emitting wavelength and a second sub-pixel with a second light-emitting wavelength, and the first light-emitting wavelength is not equal to the second light-emitting wavelength.

[0094] It should be noted that an electric field is formed between the N-type electrode and the P-type electrode, and the light-emitting layer is disposed between the N-type electrode and the P-type electrode. It can be understood that the light-emitting layer is located in the electric field. Figure 2 , 4, 6, 8 and 10-15, in the thickness direction of the chip, the entire light-emitting layer or a portion of the light-emitting layer is located between the N-type electrode and the P-type electrode. The light-emitting layer is electrically connected to the N-type electrode and the P-type electrode, respectively, which may mean that the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode, or the light-emitting layer is electrically connected to the N-type electrode through the N-type semiconductor layer, and is electrically connected to the P-type electrode through the P-type semiconductor layer.

[0095] The light-emitting layer includes at least one pixel subgroup, which includes a first subpixel and a second subpixel, and the two subpixels have different light emission wavelengths. It is understandable that the second light emission wavelength can be greater than or less than the first light emission wavelength.

[0096] In some embodiments, the first sub-pixel is one of a red pixel (R), a green pixel (G), a blue pixel (B), and an ultraviolet pixel (UVA), and the second sub-pixel is another one of the red pixel, the green pixel, the blue pixel, and the ultraviolet pixel.

[0097] For example, the first sub-pixel is a red light pixel, and the second sub-pixel is a green light pixel (i.e., R+G). Alternatively, the first sub-pixel is a green light pixel, and the second sub-pixel is a red light pixel (i.e., G+R). Alternatively, the first sub-pixel is a red light pixel, and the second sub-pixel is a blue light pixel (i.e., R+B). Alternatively, the first sub-pixel is a blue light pixel, and the second sub-pixel is a red light pixel (i.e., B+R). Alternatively, the first sub-pixel is a blue light pixel, and the second sub-pixel is a green light pixel (i.e., B+G). Alternatively, the first sub-pixel is a green light pixel, and the second sub-pixel is a blue light pixel (i.e., G+B). Alternatively, the first sub-pixel is an ultraviolet light pixel, and the second sub-pixel is a blue light pixel (i.e., UVA+B). Fig.21 and Fig. 22 shown.

[0098] The embodiment of the present application is described below by taking the first sub-pixel as a green light pixel (G) and the second sub-pixel as a blue light pixel (B) as an example.

[0099] This application combines two sub-pixels with different luminous wavelengths into a pixel subgroup, and uses the pixel subgroup to form a light-emitting diode chip, that is, a single-core dual-color multi-sub-pixel arrangement. Compared with the related technology that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip and reduce the transfer difficulty and alignment difficulty in the mass transfer operation. In addition, it can effectively reduce the number of light-emitting diode chips required for display products with the same luminous area and the same pixel density, thereby reducing the complexity of the mass transfer operation and reducing the preparation cost. In this way, the product yield of ultra-high-density pixel display can also be improved.

[0100] In some embodiments, the pixel subgroup includes a plurality of sub-pixels, and the number of first sub-pixels and the number of second sub-pixels in the plurality of sub-pixels may be equal or unequal. Figure 1-6 For example, the first sub-pixel and the second sub-pixel may both be one. Alternatively, both may be two, three, or four. Fig.16 For example, four sub-pixels all belong to the same pixel subgroup, wherein the number of the first sub-pixel G can be one, and the number of the second sub-pixel B can be three. Fig.17 For example, four sub-pixels belong to the same pixel subgroup, wherein the number of first sub-pixels G may be three, and the number of second sub-pixels B may be one. The present application does not limit the number of first sub-pixels and second sub-pixels in the same pixel subgroup.

[0101] Exemplarily, the number of sub-pixels in the pixel subgroup may be a positive integer greater than or equal to 2, and may be an odd number greater than 2, i.e., 3, 5, or 7. Exemplarily, the number of sub-pixels in the pixel subgroup may also be an even number greater than or equal to 2, i.e., 2*N (see Fig.36 As shown), where N is a positive integer greater than or equal to 1. For example, the number of sub-pixels in the pixel subgroup may be 2*10, or 2*100, or 2*1000, etc.

[0102] In some embodiments, the shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. The shapes of different sub-pixels are the same or different. That is, the shapes of the first sub-pixel G and the second sub-pixel B can both be Figure 1 or Figure 3 The rectangle shown in .

[0103] In some embodiments, the shape of the LED chip can be any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. When a plurality of LED chips form a LED chip group, the shapes of different LED chips can be the same or different.

[0104] In some embodiments, the sizes of different sub-pixels are equal or different. The size of a sub-pixel affects its light-emitting area. That is, the light-emitting areas of different sub-pixels can be equal or different. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is relatively large, the size of the sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether the sub-pixels are shared between different pixel units (PUs). For example, referring to Fig.40As shown, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively in the process of forming pixel units PU1 and PU2, while sub-pixel (G) is not shared, but all belongs to pixel unit PU1. Therefore, the size of sub-pixel (B) and sub-pixel (R) is larger than that of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be guaranteed.

[0105] It should be pointed out that the above-mentioned "size" can be understood as the extension length of the sub-pixel in a certain extension direction, for example, it can be the length or width of a rectangular sub-pixel, the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0106] In some embodiments, the size of the pixel subgroup is greater than or equal to 50 microns. The size of the light-emitting diode chip composed of the pixel subgroup may also be greater than or equal to 50 microns. For example, it may be 50-100 microns, or 100-150 microns, or greater than 150 microns. Of course, in some embodiments, the size of the light-emitting diode chip may also be less than 50 microns. The light-emitting diode chip may have different sizes according to different usage scenarios.

[0107] In some embodiments, the size of the sub-pixel ranges from 0.001 to 200 microns. When the size of the sub-pixel is 0.001 microns to 0.1 microns, the sub-pixel size is nanometer-level, which is a nano LED (nano LED). In the preparation process of nano LED, the arrangement of the single-core dual-color multi-sub-pixel of the present application can be referred to, so as to help increase the size of a single chip of the nano LED containing multiple sub-pixels, so that the size of the single chip is close to or falls within the size range of the LED chip that can be operated by the current mass transfer process, thereby reducing the operational difficulty of the nano LED preparation process and improving its operability.

[0108] In other embodiments, for example, a LED chip with 2*2 sub-pixels combined is used in a large TV, the size of a single sub-pixel can be 50 microns, and the spacing between two adjacent sub-pixels is 10 microns. The length and width of the LED chip are both 110 microns, and its size can be calculated as 110*110 microns. LED chips of this size can use the mini LED packaging process.

[0109] The size of the LED chip and the size of the sub-pixel may vary depending on the usage scenario of the LED chip. Below, exemplary descriptions are given of the size of the LED chip and the size of the sub-pixel in different usage scenarios.

[0110] When the LED chip is applied to display products such as home televisions and desktop computers, when the pixel density is 50-150, the size (pitch) of a pixel unit composed of several sub-pixels in a plurality of LED chips can be 150-700 microns, the size (sub pitch) of the sub-pixel in the LED chip can be less than 250 microns, and the size of the LED chip can be greater than 100 microns.

[0111] When the LED chip is applied to display products such as laptops and tablet computers, when the pixel density is 150-250, the sub-pixel size can be less than 70 microns, the pixel unit size is 100-200 microns, and the LED chip size can be greater than 60 microns.

[0112] When the LED chip is applied to display products such as mobile phones and electronic watches, when the pixel density is greater than 300, the sub-pixel size can be less than 30 microns, the pixel unit size is less than 100 microns, and the LED chip size can be greater than 50 microns.

[0113] Based on this, the LED chip provided in the embodiment of the present application adopts a single-core, dual-color, multi-sub-pixel arrangement. The size of the sub-pixels and the size range of the LED chip are relatively large, which can be applied to different usage scenarios, thereby increasing the applicability of the LED chip.

[0114] Next, the number and arrangement of pixel subgroups of the light-emitting layer are described.

[0115] As a first achievable implementation method, refer to Figures 1 to 6 As shown, the light-emitting layer includes a pixel subgroup. The first subpixel is a green light pixel, and the first light emission wavelength is 546 nanometers, hereinafter referred to as the first subpixel G. The second subpixel is a blue light pixel, and the second light emission wavelength is 435 nanometers, hereinafter referred to as the second subpixel B. In other embodiments, the first subpixel may also be a blue light pixel, and the second subpixel may also be a green light pixel. Figures 1 to 6 As shown in FIG. 1 , the first sub-pixel G is located on the left side of the second sub-pixel B. In other embodiments, the first sub-pixel G is located on the right side of the second sub-pixel B.

[0116] Next, the arrangement of the first sub-pixel G and the second sub-pixel B is described.

[0117] As a first achievable arrangement, the first sub-pixel G and the second sub-pixel B are arranged side by side between the N-type electrode and the P-type electrode, the first sub-pixel G contacts the N-type electrode and the P-type electrode respectively, and the second sub-pixel B contacts the N-type electrode and the P-type electrode respectively. Since the first sub-pixel G and the second sub-pixel B contact the N-type electrode and the P-type electrode respectively, and the N-type electrode and the P-type electrode are in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven to emit light at the same time, that is, the light-emitting diode chip emits two kinds of light with different wavelengths at the same time, so that the first sub-pixel G and the second sub-pixel B can be driven at the same time.

[0118] Reference Figure 1 and Figure 2 As shown, the side surface of the first sub-pixel G and the side surface of the second sub-pixel B are in contact.

[0119] Reference Figures 3 to 6 As shown, there is an isolation structure between the side of the first sub-pixel G and the side of the second sub-pixel B. The isolation structure may include a channel (CN) and an isolation material disposed in the channel. In some embodiments, the isolation structure may also include only the channel, that is, the channel may not be filled with isolation material. The channel may isolate the first sub-pixel G and the second sub-pixel B in space. Fig. 9 As shown, the electrically insulating isolation material 116 filled in the channel CN ​​is, for example, silicon nitride or silicon oxide. In some embodiments, the electrically insulating isolation material 116 may also have a light-shielding effect, such as black photoresist, so that light mixing between the first sub-pixel G and the second sub-pixel B can be reduced or avoided, thereby improving the luminous effect of the pixel subgroup. In other embodiments, the isolation structure may also be an ion implantation layer, a structure having an electrical isolation effect and a light-blocking effect formed by an ion implantation process.

[0120] For the first sub-pixel G and the second sub-pixel B arranged side by side, independent driving can also be achieved. Specifically:

[0121] As the first achievable independent drive structure, refer to Figure 3 and Figure 4 As shown, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first sub-pixel G is in contact with the first P-type electrode, and the second sub-pixel B is in contact with the second P-type electrode; a side of the first sub-pixel G facing away from the first P-type electrode and a side of the second sub-pixel B facing away from the second P-type electrode are both in contact with the N-type electrode.

[0122] When the first P-type electrode, the second P-type electrode and the N-type electrode are in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven independently to emit light of two different wavelengths.

[0123] As a second possible independent drive structure, refer to Figure 5 and Figure 6 As shown, the N-type electrode includes a first N-type electrode N1 and a second N-type electrode N2 that are separate from each other, the first sub-pixel G is in contact with the first N-type electrode N1, and the second sub-pixel B is in contact with the second N-type electrode N2; a side of the first sub-pixel G away from the first N-type electrode N1 and a side of the second sub-pixel B away from the second N-type electrode N2 are both in contact with the P-type electrode.

[0124] When the first N-type electrode N1, the second N-type electrode N2, and the P-type electrode are in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven independently to emit light of two different wavelengths.

[0125] Reference Fig.14 and Fig.15 In a sub-pixel group having a channel, when the N-type electrode includes a first N-type electrode N1 and a second N-type electrode N2 that are separate from each other, at least part of the channel extends into the P-type electrode. When the P-type electrode includes a first P-type electrode P1 and a second P-type electrode P2 that are separate from each other, at least part of the channel extends into the N-type electrode. The channel extends into the N-type electrode or the P-type electrode, which can improve the isolation effect of the channel on the first sub-pixel G and the second sub-pixel B. It should be noted that when at least part of the channel extends into the P-type electrode, the channel may be located only in a partial area of ​​the P-type electrode on the side close to the light-emitting layer, and does not penetrate the P-type electrode along the thickness direction of the P-type electrode. The situation where at least part of the channel extends into the N-type electrode is similar and will not be repeated.

[0126] As a second possible arrangement, refer to Figures 7 to 9 As shown, the first sub-pixel G and the second sub-pixel B are stacked and arranged between the N-type electrode and the P-type electrode, and the first light emission wavelength is greater than the second light emission wavelength. The first sub-pixel G is arranged on the P-type electrode, the second sub-pixel B is arranged on the side of the first sub-pixel G away from the P-type electrode, and the N-type electrode is arranged on the side of the second sub-pixel B away from the first sub-pixel G;

[0127] The first sub-pixel G contacts the first region of the second sub-pixel B, and a portion of the P-type electrode is disposed in the same layer as the first sub-pixel G and contacts the second region of the second sub-pixel B.

[0128] It should be noted that Figure 7 The first sub-pixel G and the second sub-pixel B are stacked and share an N-type electrode and a P-type electrode. Figure 1The same. When the N-type electrode and the P-type electrode are in the power-on state, the holes provided by the P-type electrode can only migrate to the sub-pixels adjacent to the P-type electrode, that is, the holes can migrate to the first sub-pixel G and the second area of ​​the second sub-pixel B, but will not migrate through the first sub-pixel G to the first area of ​​the second sub-pixel B. The electrons provided by the N-type electrode can migrate to the first sub-pixel G and the second sub-pixel B. Based on this, the electrons provided by the N-type electrode and the holes provided by the P-type electrode combine in the first sub-pixel G to excite the first sub-pixel G to emit green light, and can also combine in the second area of ​​the second sub-pixel B to excite the second area of ​​the second sub-pixel B to emit blue light, while the first area of ​​the second sub-pixel B will not be excited to emit light due to the lack of holes.

[0129] It should be noted that the thickness of the first sub-pixel G needs to be greater than the diffusion length of the holes. Alternatively, a hole blocking layer may be provided between the first sub-pixel G and the first region of the second sub-pixel B to block the holes from migrating to the first region of the second sub-pixel B. The material of the hole blocking layer may be silicon-doped gallium nitride. The sum of the thickness of the hole blocking layer and the first sub-pixel G needs to be greater than the diffusion length of the holes.

[0130] Reference Figure 7 As shown, the side of the first region of the second subpixel B contacts the side of the second region of the second subpixel B. At this time, the first subpixel G and the second subpixel B share the N-type electrode and the P-type electrode, so that the first subpixel G and the second subpixel B are driven simultaneously.

[0131] Reference Figure 8 and Fig. 9 As shown, an isolation structure is provided between the side surface of the first region of the second subpixel B and the side surface of the second region of the second subpixel B, and the isolation structure extends between the first subpixel G and a portion of the P-type electrode disposed in the same layer.

[0132] Optionally, refer to Figure 8 , the P-type electrode includes a first P-type electrode P1 and a second P-type electrode P2 which are separate from each other, the first sub-pixel G is in contact with the first P-type electrode P1 on one side away from the second sub-pixel B, and the second region of the second sub-pixel B is in contact with the second P-type electrode P2 on one side away from the N-type electrode; the first region of the second sub-pixel B and the second region of the second sub-pixel B are both in contact with the N-type electrode on one side away from the P-type electrode. At this time, the N-type electrode is shared by the first sub-pixel G and the second sub-pixel B. When the N-type electrode is in a powered-on state, and the first P-type electrode P1 and the second P-type electrode P2 are respectively in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven independently. Figure 8 The arrow marked with G indicates that in the light emitting diode chip, the area corresponding to the first sub-pixel G can emit green light from the side of the first P-type electrode P1. Figure 8The arrow marked with B indicates that in the LED chip, the area corresponding to the second area of ​​the second sub-pixel B can emit blue light from one side of the first P-type electrode P2. The LED chip is a front-mounted structure.

[0133] Optionally, refer to Fig. 9 , the N-type electrode includes a first N-type electrode N1 and a second N-type electrode N2 which are separate from each other, the surface of the first sub-pixel G which is away from the second sub-pixel B contacts the P-type electrode; the surface of the first region of the second sub-pixel B which is close to the N-type electrode contacts the first N-type electrode N1, and the surface of the second region of the second sub-pixel B which is close to the N-type electrode contacts the second N-type electrode N2. At this time, the P-type electrode is shared by the first sub-pixel G and the second sub-pixel B. When the P-type electrode is in the power-on state, and the first N-type electrode N1 and the second N-type electrode N2 are respectively in the power-on state, the first sub-pixel G and the second sub-pixel B can be driven independently. Fig. 9 The arrow marked with G indicates that in the light emitting diode chip, the area corresponding to the first sub-pixel G can emit green light from the side of the first N-type electrode N1. Fig. 9 The arrow marked with B indicates that in the LED chip, the area corresponding to the second area of ​​the second sub-pixel B can emit blue light from one side of the second N-type electrode N2. The LED chip is a flip-chip structure.

[0134] It should be noted that in the following embodiments of the present application, the light emitting direction of the light emitting diode chip can refer to Figure 8 The structure shown is formal and Fig. 9 The flip-chip structure shown in FIG.

[0135] It should be noted that in the arrangement of this embodiment, when the N-type electrode is shared, the isolation structure can also extend to a portion of the thickness of the N-type electrode, and when the P-type electrode is shared, the isolation structure can also extend to a portion of the thickness of the P-type electrode. In this way, the isolation effect of the isolation structure on the first sub-pixel G and the second sub-pixel B can be improved.

[0136] As a third possible arrangement, refer to Figures 10 to 12 As shown, the light-emitting diode chip provided in the embodiment of the present application further includes a dimming layer, and the dimming layer includes a first dimming layer CF1 and a second dimming layer CF2. The first dimming layer CF1, the first area of ​​the first sub-pixel G, and the first area of ​​the second sub-pixel B are correspondingly arranged, and the second dimming layer CF2, the second area of ​​the first sub-pixel G, and the second area of ​​the second sub-pixel B are correspondingly arranged.

[0137] Optionally, the dimming layer includes a filter or a Bragg reflector (or a distributed Bragg reflector, DBR for short). Both the filter and the Bragg reflector can filter out the wavelength of light passing through the dimming layer, thereby emitting light with different wavelengths. Among them, the filtering wavelengths of the first dimming layer CF1 and the second dimming layer CF2 are different. In this way, the light emitting diode chip can emit light with two different wavelengths. Taking the Bragg reflector as an example, it can be an alternating stack of two materials, aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials, titanium oxide and silicon oxide. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and the present application does not limit it.

[0138] Specifically, the first dimming layer CF1 filters out the light emitted by the second sub-pixel B, that is, only the light of the first emission wavelength passes through the first dimming layer CF1, and the second dimming layer CF2 filters out the light emitted by the first sub-pixel G, that is, only the light of the second emission wavelength passes through the second dimming layer CF2.

[0139] The first sub-pixel G and the second sub-pixel B are stacked and arranged between the N-type electrode and the P-type electrode. The first sub-pixel G contacts the P-type electrode, the second sub-pixel B contacts the side of the first sub-pixel G away from the P-type electrode, and the N-type electrode contacts the side of the second sub-pixel B away from the first sub-pixel G.

[0140] When the N-type electrode and the P-type electrode are in a powered-on state, the electrons provided by the N-type electrode and the holes provided by the P-type electrons will combine at the positions of the first sub-pixel G and the second sub-pixel B, respectively stimulating light of the first emission wavelength and the second emission wavelength.

[0141] Optionally, the first dimming layer CF1 and the second dimming layer CF2 are located on the side of the P-type electrode away from the N-type electrode. When the light of the first emission wavelength and the light of the second emission wavelength are emitted toward the location of the P-type electrode, they can pass through the first dimming layer CF1 and the second dimming layer CF2, and after being filtered by both, the light of the first emission wavelength is emitted in the area corresponding to the first dimming layer CF1, and the light of the second emission wavelength is emitted in the area corresponding to the second dimming layer CF2.

[0142] Optionally, the first dimming layer CF1 and the second dimming layer CF2 are located on the side of the N-type electrode away from the P-type electrode. When the light of the first emission wavelength and the light of the second emission wavelength are emitted toward the direction where the N-type electrode is located, they can pass through the first dimming layer CF1 and the second dimming layer CF2, and after being filtered by both, the light of the first emission wavelength is emitted in the area corresponding to the first dimming layer CF1, and the light of the second emission wavelength is emitted in the area corresponding to the second dimming layer CF2.

[0143] Reference Fig.10 As shown, the side of the first dimming layer CF1 is in contact with the side of the second dimming layer CF2. The side of the first region of the first subpixel G is in contact with the side of the second region of the first subpixel G, and the side of the first region of the second subpixel B is in contact with the side of the second region of the second subpixel B. That is, the first region and the second region of the first subpixel G can form a complete layered structure. The first region and the second region of the second subpixel B can also form a complete layered structure. The first subpixel G and the second subpixel B share an N-type electrode and a P-type electrode to achieve simultaneous driving of the two.

[0144] Reference Fig.11 and Fig.12 As shown, a first isolation structure (a first channel CN1 is shown in the figure) is provided between the side surface of the first dimming layer CF1 and the side surface of the second dimming layer CF2.

[0145] A second isolation structure (the second channel CN2 is shown in the figure) is provided between the side of the first region of the first subpixel G and the side of the first region of the first subpixel G, and between the side of the first region of the second subpixel B and the side of the first region of the second subpixel B; the first isolation structure and the second isolation structure correspond, and the first channel CN1 and the second channel CN2 correspond.

[0146] Optionally, refer to Fig.11 As shown, the P-type electrode includes a first P-type electrode P1 and a second P-type electrode P2 which are separate from each other, the first region of the second sub-pixel B contacts the first P-type electrode P1, and the second region of the second sub-pixel B contacts the second P-type electrode P2; the first region of the first sub-pixel G and the second region of the first sub-pixel G both contact the N-type electrode. At this time, the N-type electrode is shared by the first sub-pixel G and the second sub-pixel B. When the N-type electrode is in a powered-on state, and the first P-type electrode P1 and the second P-type electrode P2 are respectively in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven independently.

[0147] Optionally, refer to Fig.12 As shown, the N-type electrode includes a first N-type electrode N1 and a second N-type electrode N2 which are separate from each other, the first area of ​​the first sub-pixel G contacts the first N-type electrode N1, and the second area of ​​the first sub-pixel G contacts the second N-type electrode N2; the first area of ​​the second sub-pixel B and the second area of ​​the second sub-pixel B both contact the P-type electrode. At this time, the P-type electrode is shared by the first sub-pixel G and the second sub-pixel B. When the P-type electrode is in a powered-on state, and the first N-type electrode N1 and the second N-type electrode N2 are respectively in a powered-on state, the first sub-pixel G and the second sub-pixel B can be driven independently.

[0148] It should be noted that in the arrangement of this embodiment, when the N-type electrode is shared, the isolation structure can also extend to a portion of the thickness of the N-type electrode, and when the P-type electrode is shared, the isolation structure can also extend to a portion of the thickness of the P-type electrode. In this way, the isolation effect of the isolation structure on the first sub-pixel G and the second sub-pixel B can be improved.

[0149] In some embodiments, reference Fig.13 As shown, the first sub-pixel G and the second sub-pixel B may also be a multi-layer structure, and the multiple layers of the first sub-pixel G and the multiple layers of the second sub-pixel B are alternately stacked in sequence. Fig.13 As shown in FIG. 1 , the first layer is the first sub-pixel G, the second layer is the second sub-pixel B, the third layer is the first sub-pixel G, and the fourth layer is the second sub-pixel B. In other embodiments, the number of the multi-layer first sub-pixel G and the multi-layer second sub-pixel B can also be 3 layers, 4 layers or more layers respectively. Figures 10 to 12 In the example shown in FIG. 1 , the single-layer thickness of the multiple layers of first sub-pixels G and the multiple layers of second sub-pixels B are relatively small, and the sum of the total thickness of the multiple layers of first sub-pixels G and the multiple layers of second sub-pixels B is less than the diffusion length of holes and electrons. In this way, holes and electrons can be uniformly diffused to each layer of first sub-pixels G and each layer of second sub-pixels B, thereby achieving simultaneous light emission of multiple layers of first sub-pixels G and multiple layers of second sub-pixels B, which helps to improve the light-emitting effect.

[0150] As a second feasible implementation, the light-emitting layer includes at least two pixel subgroups, at least two pixel subgroups are arranged in sequence along a first direction, and a first subpixel G and a second subpixel B are arranged in sequence along a second direction; wherein the first direction and the second direction intersect with each other; and the first light-emitting wavelength is greater than the second light-emitting wavelength.

[0151] Reference Figures 18 to 20 As shown, the light-emitting layer may include two pixel subgroups. In other embodiments, the light-emitting layer may also include three, four, five or more pixel subgroups. Taking two pixel subgroups as an example, both pixel subgroups include a first subpixel G and a second subpixel B. The first direction is the direction shown by x in the figure, and the second direction is the direction shown by y in the figure.

[0152] Among them, the pixel subgroup includes a first pixel subgroup and a second pixel subgroup, the first subpixel G of the first pixel subgroup and the first subpixel G of the second pixel subgroup have the same emission wavelength, and the second subpixel B of the first pixel subgroup and the second subpixel B of the second pixel subgroup have the same emission wavelength. Figures 18 to 20 In each of the two rows of sub-pixels, two sub-pixels in the first row form a first pixel sub-group, and two sub-pixels in the second row form a second pixel sub-group.

[0153] Optionally, refer to Fig.18 As shown, along the first direction, the first sub-pixel G of the first pixel sub-group corresponds to the first sub-pixel G of the second pixel sub-group, and the second sub-pixel B of the first pixel sub-group corresponds to the second sub-pixel B of the second pixel sub-group.

[0154] Optionally, refer to Fig.19 As shown, the first sub-pixel G of the first pixel sub-group corresponds to the second sub-pixel B of the second pixel sub-group, and the second sub-pixel B of the first pixel sub-group corresponds to the first sub-pixel G of the second pixel sub-group.

[0155] In the embodiment of the present application, the driving modes of the two pixel subgroups may include simultaneous driving and independent driving. The different arrangement structures of the two driving modes are described in detail below.

[0156] Optionally, the light emitting diode chip includes an N-type electrode and a P-type electrode, and all sub-pixels in the two pixel subgroups are in contact with the N-type electrode and the P-type electrode, respectively, so as to achieve simultaneous driving of multiple sub-pixels.

[0157] Optionally, the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as that of the sub-pixels; one side of a sub-pixel facing away from the P-type electrode contacts one sub-N-type electrode; and one side of the sub-pixel facing away from the N-type electrode contacts the P-type electrode. In this way, when the multiple N-type electrodes are respectively in a powered-on state and the P-type electrode is in a powered-on state, multiple sub-pixels can be driven independently.

[0158] Optionally, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as that of the sub-pixels; one side of a sub-pixel facing away from the N-type electrode contacts one sub-P-type electrode; and one side of the sub-pixel facing away from the P-type electrode contacts the N-type electrode. In this way, when the multiple P-type electrodes are respectively in a powered-on state and the N-type electrode is in a powered-on state, multiple sub-pixels can be driven independently. Fig.18 and Fig.19 As shown in the figure, it includes four sub-P-type electrodes, namely sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21 and sub-P-type electrode P22. The four sub-P-type electrodes are respectively connected to four sub-pixels, and the four sub-pixels are all connected to the N-type electrode.

[0159] In some embodiments, when the size of the overall light-emitting diode chip is large and the conductivity of a single electrode is not high, if all sub-pixels share the same electrode, such as a shared P-type electrode or a shared N-type electrode, the sub-pixels in some areas will have lower luminous brightness and the overall light-emitting diode chip will have an uneven luminous effect. Therefore, the present application divides all sub-pixels of the entire light-emitting diode chip into multiple areas, and sets the sub-pixels in the same area to share electrodes. In this way, the sub-pixels in the same area share one electrode, which can ensure the uniformity of the luminous effect of the sub-pixels in multiple areas and the overall light-emitting diode chip compared to the sub-pixels in all areas sharing the same electrode.

[0160] Exemplarily, the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of sub-pixels; the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is less than the number of sub-pixels; one side of a sub-pixel away from the P-type electrode contacts one sub-N-type electrode, and one side of a part of the sub-pixels away from the N-type electrode contacts the same sub-P-type electrode. That is, on the basis of independent driving of multiple sub-pixels, multiple sub-pixels in a part of the area can share one sub-P-type electrode.

[0161] Another exemplary example, referring to Fig. 20 As shown, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of sub-pixels; the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is less than the number of sub-pixels; one side of a sub-pixel facing away from the N-type electrode contacts one sub-P-type electrode, and one side of a part of the sub-pixels facing away from the P-type electrode contacts the same sub-N-type electrode. Fig. 20 As shown in the figure, it includes four sub-P-type electrodes and two sub-N-type electrodes, which are sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21 and sub-P-type electrode P22, and sub-N-type electrode N1 and sub-N-type electrode N2. The first sub-pixel of the first pixel subgroup contacts the sub-P-type electrode P11, and the second sub-pixel contacts the sub-P-type electrode P21, and both of them contact the sub-N-type electrode N1. The first sub-pixel of the second pixel subgroup contacts the sub-P-type electrode P22, and the second sub-pixel contacts the sub-P-type electrode P12, and both of them contact the sub-N-type electrode N2. In this way, all sub-pixels of the first pixel subgroup can share one sub-N-type electrode, and all sub-pixels of the second pixel subgroup can share another sub-N-type electrode, thereby ensuring the uniformity of light emission of the overall light-emitting diode chip.

[0162] In some embodiments, reference Figures 23 to 25 As shown, the light emitting diode chip can also be a monochrome multi-sub-pixel chip. That is, the light emitting layer includes a plurality of monochrome sub-pixels. For example, the light emitting layer of the light emitting diode chip C1 can include four sub-pixels B ( Fig.23), or the light-emitting layer of the light-emitting diode chip C2 includes four sub-pixels G( Fig.24 ), or the light-emitting layer of the light-emitting diode chip C3 includes four sub-pixels R ( Fig.25 ). In other embodiments, the number of monochromatic sub-pixels of the light-emitting layer can be adjusted to 2, 3, 5 or more. Combining multiple monochromatic sub-pixels to form a light-emitting diode chip can also flexibly adjust the size of the light-emitting diode chip.

[0163] The above describes in detail the structure and arrangement of the N-type electrode, the P-type electrode and the light-emitting layer in the light-emitting diode chip. The following describes in detail other structures and arrangements of the light-emitting diode chip.

[0164] Reference Fig.26 As shown, the light-emitting diode chip provided in the embodiment of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107 and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, the light-emitting layer is arranged on the side of the N-type semiconductor layer 103 away from the buffer layer 101, and the P-type semiconductor layer 105 is arranged on the side of the light-emitting layer away from the buffer layer 101; the current spreading layer 106 is in contact with the side of the P-type semiconductor layer 105 away from the buffer layer 101, the N-type electrode 102 is in contact with the N-type semiconductor layer 103, and the P-type electrode 104 is in contact with the P-type semiconductor layer 105 and the current spreading layer 106; the first insulating layer 108 is arranged on the side of the current spreading layer 106 away from the buffer layer 101. In this way, a light-emitting diode chip with a thin film flip-chip structure can be formed. The light-emitting layer includes a pixel subgroup, and the first subpixel sp1 and the second subpixel sp2 of the pixel subgroup are arranged side by side.

[0165] Optionally, the reflective layer 107 is disposed on a side of the buffer layer 101 away from the light-emitting layer, so that the light emitting direction of the light-emitting diode chip is away from the buffer layer 101. Fig.26 As shown, the reflective layer 107 is disposed on the side of the first insulating layer 108 away from the buffer layer 101, and a second insulating layer 109 is also disposed on the side of the reflective layer 107 away from the buffer layer 101. In this way, the light emitting direction of the LED chip is toward the direction of the buffer layer 101, that is, the downward arrow direction shown in the figure.

[0166] The material of the buffer layer 101 may be one or more of gallium nitride, aluminum gallium nitride and aluminum indium gallium nitride, and the thickness of the buffer layer 101 may be 10-40 nanometers. The material of the N-type semiconductor layer 103 may be N-type doped gallium nitride, and the material of the P-type semiconductor layer 105 may be P-type doped gallium nitride. The material of the current spreading layer 106 may be a transparent conductive material (indium tin oxide, ITO) or silver, etc., which can improve the distribution ability of the P-type electrode and make the holes as evenly distributed as possible in the area where the P-type semiconductor layer 105 is located. The material of the first insulating layer 108 may be silicon oxide or silicon nitride.

[0167] Reference Fig. 27 and Fig.28 As shown, based on the above thin film light emitting diode chip, the light emitting diode chip further includes a substrate 100, which is arranged on the side of the buffer layer 101 away from the light emitting layer. The material of the substrate 100 can be a composite of one or more of sapphire, gallium nitride, aluminum nitride, silicon and silicon carbide.

[0168] Reference Fig. 27 As shown, when the reflective layer 107 is disposed on the side of the buffer layer 101 away from the light-emitting layer, the reflective layer 107 is disposed on the side of the substrate 100 away from the buffer layer 101 . Fig. 27 The light emitting direction is the upward direction indicated by the arrow in the figure, forming a light emitting diode chip with a positive structure. Fig.28 The light emitting direction is the downward direction indicated by the arrow in the figure, forming a light emitting diode chip with a flip-chip structure.

[0169] Reference Fig.29 As shown, the light-emitting diode chip may also include a bonding substrate 110, a binding layer 111, an N-type semiconductor layer 103, a P-type semiconductor layer 105 and a reflective layer 107; the bonding substrate 110 and the binding layer 111 are sequentially arranged on the P-type electrode 104, the P-type semiconductor layer 105 is arranged on the side of the binding layer 111 away from the bonding substrate 110, and is in contact with the binding layer 111; the light-emitting layer is arranged on the side of the P-type semiconductor layer 105 away from the bonding substrate 110, the N-type semiconductor layer 103 is arranged on the side of the light-emitting layer away from the bonding substrate 110, and the N-type electrode 102 contacts the side of the N-type semiconductor layer 103 away from the bonding substrate 110; the reflective layer 107 is arranged on the side of the P-type semiconductor layer 105 close to the bonding substrate 110. The light-emitting direction of the light-emitting diode chip can be the upward direction indicated by the arrow in the figure. A light-emitting diode chip with a vertical structure is formed.

[0170] In a second aspect, an embodiment of the present application provides a method for preparing a light emitting diode chip, which can be used to prepare the light emitting diode chip mentioned above.

[0171] As the first preparation method of light-emitting diode chips, refer to Fig.30 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are arranged side by side, there is no isolation structure between the two, and they can be driven simultaneously. Specifically, the preparation method includes:

[0172] Forming a substrate 100 ( Fig.30 (a)); a buffer layer 101, an N-type semiconductor layer 103 and a first sub-pixel SP1 are sequentially formed on a substrate 100 by an epitaxial growth process ( Fig.30 (b)); removing a portion of the first sub-pixel SP1 through a patterning process to expose a portion of the top surface of the N-type semiconductor layer 103 ( Fig.30 (c)); forming a protective layer 113 covering the first sub-pixel SP1 and the N-type semiconductor layer 103 ( Fig.30 (d)); removing the protective layer 113 covering the N-type semiconductor layer 103 through a patterning process, and retaining the protective layer 113 covering the first sub-pixel SP1 ( Fig.30 (e)); forming a second sub-pixel SP2 by an epitaxial growth process ( Fig.30 (f)); removing the protective layer 113 ( Fig.30 (g)), the first sub-pixel SP1 and the second sub-pixel SP2 are arranged side by side, and the top surfaces are flush; forming a P-type semiconductor layer 105 ( Fig.30 (h)). The substrate 100 and the protective layer 113 may be formed by deposition. The material of the protective layer 113 may be metal, inorganic material or organic material that meets the requirements of high temperature resistance and resistance to other chemical substances in the process, and may be silicon oxide or silicon nitride, and its thickness may be 50-300 nanometers.

[0173] As the second preparation method of the light-emitting diode chip, continue to refer to Fig.30 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are arranged side by side, an isolation structure is formed between the two, and simultaneous driving and independent driving are satisfied. Specifically, the preparation method includes:

[0174] Based on the first manufacturing method described above, a channel ( Fig.30 (i)) (The isolation material filled in the trench is not shown in the figure).

[0175] As the third method for preparing light-emitting diode chips, refer to Fig.31 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are stacked and arranged, and no isolation structure is formed between the two, and they can be driven simultaneously. Specifically, the preparation method includes:

[0176] Forming a substrate 100 ( Fig.31(a)); a buffer layer 101, an N-type semiconductor layer 103 and a first sub-pixel SP1 are sequentially formed on a substrate 100 by an epitaxial growth process ( Fig.31 (b)); forming a protective layer 113 on the top surface of a portion of the first sub-pixel SP1 ( Fig.31 (c)); forming a second sub-pixel SP2 covering the first sub-pixel SP1 and the protective layer 113 ( Fig.31 (d)); removing the protective layer 113 ( Fig.31 (e)); forming a P-type semiconductor layer 105 covering the first sub-pixel SP1 and the second sub-pixel SP2 ( Fig.31 (f)).

[0177] As the fourth method for preparing light-emitting diode chips, continue to refer to Fig.31 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are stacked and arranged, an isolation structure is formed between the two, and simultaneous driving and independent driving are satisfied. Specifically, the preparation method includes:

[0178] Based on the third manufacturing method described above, a channel ( Fig.31 (g)) (The isolation material filled in the trench is not shown in the figure).

[0179] As the fifth method for preparing light-emitting diode chips, refer to Fig.32 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are stacked and arranged, and there is no isolation structure between the two, and they can be driven simultaneously, and the light-emitting diode chip is a normal structure. Specifically, the preparation method includes:

[0180] Forming a substrate 100 ( Fig.32 (a)); a buffer layer 101, an N-type semiconductor layer 103, a first sub-pixel SP1, a second sub-pixel SP2 and a P-type semiconductor layer 105 are sequentially formed on a substrate 100 by an epitaxial growth process ( Fig.32 (b)); forming a step in the N-type semiconductor layer 103 by an etching process, and removing part of the first sub-pixel SP1, part of the second sub-pixel SP2 and part of the P-type semiconductor layer 105 ( Fig.32 (c)) A current spreading layer 106 is formed on the top surface of the P-type semiconductor layer 105 ( Fig.32 (d)); forming a first insulating layer 108, and patterning the first insulating layer 108 ( Fig.32 (e)); forming a first dimming layer 114 on a portion of the first insulating layer 108 ( Fig.32 (f)) ; forming a second dimming layer 115 ( Fig.32(g)) ; forming a P-type electrode 104 and an N-type electrode 102 ( Fig.32 (h)).

[0181] As the sixth method for preparing a light-emitting diode chip, refer to Fig.33 As shown, it can be used to prepare a structure in which a first sub-pixel and a second sub-pixel are stacked and arranged, an isolation structure is formed between the two, and simultaneous driving and independent driving are satisfied, and the light-emitting diode chip is a front-mounted structure. Specifically, the preparation method includes:

[0182] Forming a substrate 100 ( Fig.33 (a)); a buffer layer 101, an N-type semiconductor layer 103, a first sub-pixel SP1, a second sub-pixel SP2 and a P-type semiconductor layer 105 are sequentially formed on a substrate 100 by an epitaxial growth process ( Fig.33 (b)); a step is formed in the N-type semiconductor layer 103 by an etching process, and a portion of the first sub-pixel SP1, a portion of the second sub-pixel SP2 and a portion of the P-type semiconductor layer 105 are removed, and a channel ( Fig.33 (c)) (not shown in the figure, the isolation material is filled in the trench); a current spreading layer 106 is formed on the top surface of the P-type semiconductor layer 105 ( Fig.33 (d)); forming a first insulating layer 108, and patterning the first insulating layer 108 ( Fig.33 (e)) ; forming a first dimming layer 114 and a second dimming layer 115 ( Fig.33 (f)) ; forming an N-type electrode 102 and a P-type electrode 104 ( Fig.33 (g)); forming a reflective layer 107 on the bottom surface of the substrate 100 ( Fig.33 (h)).

[0183] In a third aspect, an embodiment of the present application provides a light-emitting diode chip group, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array; two adjacent light-emitting diode chips include a first light-emitting diode chip and a second light-emitting diode chip, and a portion of the sub-pixels of the first light-emitting diode chip and a portion of the sub-pixels of the second light-emitting diode chip together constitute a pixel unit. It should be noted that a portion of the sub-pixels in the first light-emitting diode chip and the second light-emitting diode chip constituting the pixel unit may be all or part of the sub-pixels in the same pixel subgroup. Optionally, the light-emitting wavelengths of the two sub-pixels of the first light-emitting diode chip and the one sub-pixel of the second light-emitting diode chip are different. In this way, a pixel unit with a plurality of light-emitting wavelengths can be formed.

[0184] In the following, the different light emitting diode chips are arranged differently to form a pixel unit, and the dual-color multi-sub-pixel light emitting diode chips constitute a chipset in this embodiment.

[0185] As a first feasible implementation, the entire area of ​​two sub-pixels of the first light-emitting diode chip and the entire area of ​​one sub-pixel of the second light-emitting diode chip together constitute a pixel unit. The starting sub-pixel can be any one, such as R, B, or G, and the arrangement order of sub-pixels in the pixel unit can be changed arbitrarily.

[0186] For example, refer to Fig.34 As shown, the first LED chip includes two pixel subgroups, namely, two pixel subgroups in the first column, the pixel subgroup in the first row includes the first subpixel B and the second subpixel G, and the pixel subgroup in the second row includes the third subpixel B and the fourth subpixel G. The second LED chip includes two pixel subgroups, namely, two pixel subgroups in the second column, the pixel subgroup in the first row includes the first subpixel R and the second subpixel B, and the pixel subgroup in the second row includes the third subpixel R and the fourth subpixel B.

[0187] In the above example, the first LED chip and the second LED chip form a pixel unit, and the first sub-pixel B and the second sub-pixel G in the first row of the first LED chip and the first sub-pixel R in the first row of the second LED chip together form a pixel unit PU1. According to this arrangement, the first LED chip and the second LED chip also form a pixel unit PU2.

[0188] The light emitting diode chip set may further include a third light emitting diode chip, and further reference is made to Fig.34 As shown, the third LED chip includes two pixel subgroups, namely, two pixel subgroups in the third column. The pixel subgroup in the first row includes the first subpixel G and the second subpixel R, and the pixel subgroup in the second row includes the third subpixel G and the fourth subpixel R.

[0189] The second LED chip and the third LED chip form a pixel unit, and the second sub-pixel B in the first row of the second LED chip and the first sub-pixel G and the second sub-pixel R in the first row of the third LED chip together form a pixel unit PU3. According to this arrangement, the second LED chip and the third LED chip also form a pixel unit PU4.

[0190] Reference Fig.35 and Fig.36 As shown, in the above arrangement, the light emitting diode chip includes three pixel subgroups ( Fig.35 ), or four pixel subgroups (not shown), or five pixel subgroups ( Fig.36 Five pixel subgroups are drawn, and the subsequent ellipsis indicates more pixel subgroups), and even more pixel subgroups can form a pixel unit.

[0191] The pixel unit PU1, pixel unit PU2, pixel unit PU3 and pixel unit PU4 together form a chip group CG1. According to the above arrangement, a chip group CG2 can be formed. Figure 34 to Figure 36 Two chipsets are shown, namely chipset CG1 and chipset CG2. The arrangement of chipset CG1 and chipset CG2 can be the same, and the arrangement of pixel units formed can also be the same. In other embodiments, the arrangement of chipset CG1 and chipset CG2 can also be different, and the arrangement of pixel units formed can also be different.

[0192] In some embodiments, the arrangement of sub-pixels in the first LED chip, the second LED chip, and the third LED chip may be different from the above embodiments. Embodiments of the arrangement of different sub-pixels in the first LED chip, the second LED chip, and the third LED chip are given below.

[0193] Reference Fig.37 As shown, in some embodiments, in the first LED chip of the first column, the pixel subgroup of the first row includes the first subpixel G and the second subpixel R. The pixel subgroup of the second row includes the first subpixel G and the second subpixel R. In the second LED chip of the second column, the pixel subgroup of the first row includes the first subpixel B and the second subpixel G, and the pixel subgroup of the second row includes the first subpixel B and the second subpixel G. In the third LED chip of the third column, the pixel subgroup of the first row includes the first subpixel R and the second subpixel B, and the pixel subgroup of the second row includes the first subpixel R and the second subpixel B. In this way, the first subpixel G and the second subpixel R of the pixel subgroup of the first row of the first LED chip and the first subpixel B of the pixel subgroup of the first row of the second LED chip together form a pixel unit PU1. In this way, pixel unit PU2, pixel unit PU3 and pixel unit PU4 can be formed. The subpixels and pixel units of chip group CG1 and chip group CG2 are arranged in the same manner.

[0194] Reference Fig.38As shown, in some embodiments, in the first LED chip of the first column, the pixel subgroup of the first row includes the first subpixel R and the second subpixel B. The pixel subgroup of the second row includes the first subpixel R and the second subpixel B. In the second LED chip of the second column, the pixel subgroup of the first row includes the first subpixel G and the second subpixel R, and the pixel subgroup of the second row includes the first subpixel G and the second subpixel R. In the third LED chip of the third column, the pixel subgroup of the first row includes the first subpixel B and the second subpixel G, and the pixel subgroup of the second row includes the first subpixel B and the second subpixel G. In this way, the first subpixel R and the second subpixel B of the pixel subgroup of the first row of the first LED chip and the first subpixel G of the pixel subgroup of the first row of the second LED chip together form a pixel unit PU1. In this way, pixel unit PU2, pixel unit PU3 and pixel unit PU4 can be formed. The subpixels and pixel units of chip group CG1 and chip group CG2 are arranged in the same manner.

[0195] In some embodiments, sub-pixels between different chipsets may also form a pixel unit. Fig.39 As shown, the chip group CG1 includes three pixel subgroups, and the subpixels in the three pixel subgroups are respectively the first subpixel B and the second subpixel G of the first pixel subgroup, the third subpixel R and the fourth subpixel B of the second pixel subgroup, and the fifth subpixel G and the sixth subpixel R of the third pixel subgroup. The chip group CG2 includes multiple pixel subgroups, and the subpixels in the three pixel subgroups are respectively the first subpixel B and the second subpixel G of the first pixel subgroup, the third subpixel R and the fourth subpixel B of the second pixel subgroup, and the fifth subpixel G and the sixth subpixel R of the third pixel subgroup. The chip group CG1 and the chip group CG2 can be arranged in two rows and staggered with each other (that is, along the arrangement direction of the chip group CG1 and the chip group CG2, the subpixels in the chip group CG1 and the chip group CG2 are staggered with each other). The subpixels in the chipset CG1 and the chipset CG2 can form a plurality of pixel units, specifically: the first subpixel B of the chipset CG1, and the second subpixel G and the third subpixel R of the chipset CG2 together form a pixel unit PU1. The second subpixel G and the third subpixel R of the chipset CG1 and the fourth subpixel B of the chipset CG2 together form a pixel unit PU2. The fourth subpixel B of the chipset CG1 and the fifth subpixel G and the sixth subpixel R of the chipset CG2 together form a pixel unit PU3.

[0196] As a second achievable implementation, partial areas of two sub-pixels of the first light-emitting diode chip and partial areas of one sub-pixel of the second light-emitting diode chip together form a pixel unit. Fig.40As shown, the first LED chip in the first column includes a pixel subgroup, the pixel subgroup includes a first subpixel B and a second subpixel G, and the size of the first subpixel B is larger than the size of the second subpixel G. The second LED chip in the second column includes a pixel subgroup, the pixel subgroup includes a first subpixel R and a second subpixel G, and the size of the first subpixel R is larger than the size of the second subpixel G. The partial area of ​​the first subpixel B of the first LED chip, the entire area of ​​the second subpixel G, and the partial area of ​​the first subpixel R of the second LED chip together constitute a pixel unit PU1.

[0197] The third LED chip of the third column includes a pixel subgroup, which includes a first subpixel B and a second subpixel G. The size of the first subpixel B is larger than the size of the second subpixel G. A partial area of ​​the first subpixel R of the second LED chip, the entire area of ​​the second subpixel G, and a partial area of ​​the first subpixel B of the three LED cores together constitute a pixel unit PU2.

[0198] The first LED chip and the second LED chip together form a chipset group CG1. In the above arrangement, the third LED chip and the fourth third LED chip of the fourth column can form a chipset group CG12. A partial area of ​​the first sub-pixel B of the third LED chip, the entire area of ​​the second sub-pixel G, and a partial area of ​​the first sub-pixel B of the fourth LED chip together form a pixel unit PU3.

[0199] In the above embodiment, the sub-pixels shared are sub-pixel B and sub-pixel R. In other embodiments, the sub-pixels shared by the pixel unit are different. The following is an embodiment of the arrangement of chip groups that share different sub-pixels.

[0200] Reference Fig.41 As shown, the first LED chip of the first column includes a pixel subgroup, the pixel subgroup includes a first subpixel B and a second subpixel G, and the size of the first subpixel B is smaller than the size of the second subpixel G. The second LED chip of the second column includes a pixel subgroup, the pixel subgroup includes a first subpixel B and a second subpixel R, and the size of the first subpixel B is smaller than the size of the second subpixel R. The partial area of ​​the first subpixel G of the first LED chip, the entire area of ​​the first subpixel B of the second LED chip, and the partial area of ​​the second subpixel R together constitute the pixel unit PU1. In this way, the pixel units PU2 and PU3 can be formed. In this embodiment, the subpixels G and R are shared.

[0201] Reference Fig.42As shown, the first LED chip of the first column includes a pixel subgroup, the pixel subgroup includes a first subpixel B and a second subpixel G, and the size of the first subpixel B is smaller than the size of the second subpixel G. The second LED chip of the second column includes a pixel subgroup, the pixel subgroup includes a first subpixel R and a second subpixel B, and the size of the first subpixel R is smaller than the size of the second subpixel R. The partial area of ​​the first subpixel G of the first LED chip, the entire area of ​​the first subpixel R of the second LED chip, and the partial area of ​​the second subpixel R together constitute the pixel unit PU1. In this way, the pixel units PU2 and PU3 can be formed. In this embodiment, the subpixels G and B are shared.

[0202] As a third achievable implementation, among at least two sub-pixels of the first LED chip and at least two sub-pixels of the second LED chip, a portion of the sub-pixels have the same light-emitting wavelength; and, at least two sub-pixels of the first LED chip and at least two sub-pixels of the second LED chip together constitute a pixel unit.

[0203] Reference Fig.43 As shown, the first LED chip C1 in the first column includes a plurality of pixel subgroups, the pixel subgroups in the first row include a first subpixel R and a second subpixel B, and the second LED chip C2 in the second column includes a plurality of pixel subgroups, the pixel subgroups in the first row include a first subpixel G and a second subpixel R. The first subpixel R and the second subpixel B of the first LED chip C1, and the first subpixel G and the second subpixel R of the second LED chip C2 together form a pixel unit PU. The number of subpixels in the pixel unit is greater than 3, and includes subpixels of three different light-emitting wavelengths. In this arrangement, the pixel subgroups in the second row of the first LED chip C1 and the pixel subgroups in the second row of the second LED chip C2 can also form another pixel unit.

[0204] Fig.43 The pixel unit shown includes two sub-pixels R, one sub-pixel G and one sub-pixel B. In other embodiments, the pixel unit may also include two sub-pixels R, two sub-pixels B and one sub-pixel G, or the pixel unit may also include 5 sub-pixels, such as three sub-pixels R, one sub-pixel B and one sub-pixel G, or the pixel unit may also include 6, 7, 8 or more sub-pixels. The first light-emitting diode chip C1 and the second light-emitting diode chip C2 together constitute a chipset group CG.

[0205] Based on the different luminous efficiencies of sub-pixels with different luminous wavelengths, the above arrangement can be used to adjust the uniformity of light of different wavelengths in a pixel unit, ensure the consistency of light output, and improve the light output effect of the light-emitting diode chipset. In addition, when there are multiple sub-pixels, for example, two sub-pixels R, and one sub-pixel R is damaged, another sub-pixel R can be used to output light instead.

[0206] Reference Fig.44 As shown, the first LED chip C1 may include a pixel subgroup including a first subpixel G and a second subpixel B, and the second LED chip C2 may include a pixel subgroup including a first subpixel B and a second subpixel R. The pixel subgroup of the first LED chip C1 and the pixel subgroup of the second LED chip C2 together form a pixel unit including two subpixels B, one subpixel G, and one subpixel R.

[0207] Reference Fig.45 As shown, the first LED chip C1 may include a pixel subgroup including a first subpixel G and a second subpixel B, and the second LED chip C2 may include a pixel subgroup including a first subpixel G and a second subpixel R. The pixel subgroup of the first LED chip C1 and the pixel subgroup of the second LED chip C2 together form a pixel unit including two subpixels G, one subpixel B and one subpixel R.

[0208] Reference Figures 34 to 38 As shown, the shapes of different light emitting diode chips can be the same and regular.

[0209] Reference Figures 46 to 50 As shown, in the LED chip set provided in this embodiment, the first LED chip C1 and the second LED chip C2 can also be of special shape, the first LED chip C1 has a convex area, and the second LED chip C2 has a concave area. The convex area can be a cube, a cone, a hemisphere or other irregular shapes, and the shapes of the convex area and the concave area are adapted and fit together. The number of the convex area and the concave area can be 1, 2 or more, and the number of the two can be equal.

[0210] It should be noted that Fig.46For example, the first LED chip C1 and the second LED chip C2 are both step-shaped, and the protruding area A2 of the step of the first LED chip C1 is relatively spliced ​​with the recessed area A1 of the step of the second LED chip C2, and the splicing is performed in this way. In this way, the first LED chip C1, the second LED chip C2 and the third LED chip C3 are spliced. Among them, the size of the sub-pixels in the first LED chip C1 is the same. In the present application, the protruding area and the recessed area are aligned and spliced ​​with each other, which can form a structure similar to a "mortise and tenon structure", thereby facilitating the self-alignment assembly of different LED chips, reducing the difficulty of alignment, and improving the preparation efficiency and yield.

[0211] Of course, the shape of the light emitting diode chip can also be convex or concave ( Fig.47 As shown); or, in a stepped LED chip, different sub-pixels have different sizes ( Fig.48 as shown); or, the light-emitting diode chip has a jagged edge ( Fig.49 Alternatively, the light-emitting diode chip has a curved edge ( Fig.50 shown).

[0212] Reference Fig.51 As shown, the LED chip group includes a first LED chip C1, a second LED chip C2 and a third LED chip C3 which are arranged adjacent to each other in sequence. The first LED chip C1, the second LED chip C2 and the third LED chip C3 each include a pixel subgroup.

[0213] The first sub-pixel B and the second sub-pixel G of the first LED chip C1 (the pixel sub-group of the first row and the first column) and the first sub-pixel R of the second LED chip C2 (the pixel sub-group of the first row and the second column) emit light at different wavelengths and together constitute a first pixel unit; the second sub-pixel B of the second LED chip C2 and the first sub-pixel G and the second sub-pixel R of the third LED chip C3 (the pixel sub-group of the first row and the third column) emit light at different wavelengths and together constitute a second pixel unit. The first LED chip C1, the second LED chip C2 and the third LED chip C3 together constitute a chipset CG1.

[0214] The plurality of light emitting diode chips form a plurality of chipsets arranged in an array. The plurality of chipsets may further include chipset CG2, chipset CG3 and chipset CG4.

[0215] Among them, refer to Fig.51As shown, along the second direction y, in the chip group CG1, the sum of the size of the first sub-pixel B of the first LED chip and the spacing between the first sub-pixel B of the first LED chip and the second sub-pixel G of the first LED chip is the first size. The size of the first sub-pixel B of the first LED chip is a, the spacing between the first sub-pixel B of the first LED chip and the second sub-pixel G of the first LED chip is b, the first size = a + b, and the first size is the sub-pixel size of the first sub-pixel B (Sub pitch).

[0216] The sum of the size of the second sub-pixel G of the first LED chip and the spacing between the second sub-pixel G of the first LED chip and the first sub-pixel R of the second LED chip is the second size. The size of the second sub-pixel G of the first LED chip is c, the spacing between the second sub-pixel G of the first LED chip and the first sub-pixel R of the second LED chip is d, the second size=c+d, and the second size is the sub-pixel size of the second sub-pixel G.

[0217] The sum of the size of the first sub-pixel R of the second LED chip and the spacing between the first sub-pixel R of the second LED chip and the second sub-pixel B of the second LED chip is the third size. The size of the first sub-pixel R of the second LED chip is e, the spacing between the first sub-pixel R of the second LED chip and the second sub-pixel B of the second LED chip is f, the third size=e+f, and the third size is the sub-pixel size of the first sub-pixel R.

[0218] The sum of the size of the second sub-pixel B of the second LED chip and the spacing between the second sub-pixel B of the second LED chip and the first sub-pixel G of the third LED chip is the fourth size. The size of the second sub-pixel B of the second LED chip is a, the spacing between the second sub-pixel B of the second LED chip and the first sub-pixel G of the third LED chip is g, the fourth size=a+g, and the fourth size is the sub-pixel size of the second sub-pixel B.

[0219] The sum of the size of the first sub-pixel G of the third LED chip and the spacing between the first sub-pixel G of the third LED chip and the second sub-pixel R of the third LED chip is the fifth size. The size of the first sub-pixel G of the third LED chip is c, the spacing between the first sub-pixel G of the third LED chip and the second sub-pixel R of the third LED chip is h, the fifth size=c+h, and the fifth size is the sub-pixel size of the first sub-pixel G.

[0220] The sum of the spacing between the first sub-pixel B of the first LED chip and the edge of the chipset CG1, the size of the second sub-pixel R of the third LED chip, the spacing between the second sub-pixel R of the third LED chip and the edge of the chipset CG1, and the spacing between the adjacent chipset CG1 and chipset CG2 is the sixth size.

[0221] The spacing between the first sub-pixel B of the first LED chip and the edge of the chipset CG1 is k, the size of the second sub-pixel R of the third LED chip is e, the spacing between the second sub-pixel R of the third LED chip and the edge of the chipset CG1 is i, and the spacing between the adjacent chipsets CG1 and CG2 is l. The sixth size = k+e+i+l.

[0222] Optionally, the first size, the second size, the third size, the fourth size, the fifth size, and the sixth size are all equal; the sum of the first size, the second size, and the third size is equal to the sum of the fourth size, the fifth size, and the sixth size. Among them, the sum of the first size, the second size, and the third size can be the pixel size (Pitch) of a pixel unit composed of the first sub-pixel B of the first LED chip, the second sub-pixel G of the first LED chip, and the first sub-pixel R of the second LED chip. Similarly, the sum of the fourth size, the fifth size, and the sixth size can all be the pixel size of a pixel unit composed of the second sub-pixel B of the second LED chip, the first sub-pixel G of the third LED chip, and the second sub-pixel R of the third LED chip. Of course, in other embodiments, the first size, the second size, the third size, the fourth size, the fifth size, and the sixth size may be different.

[0223] Continue to refer to Fig.51 Along the first direction x, the size of the first sub-pixel B of the first LED chip in the chip group CG1 is m. The spacing between the first sub-pixel B of the first LED chip in the chip group CG1 and the first sub-pixel B of the first LED chip in the chip group CG3 is n.

[0224] The first sub-pixel B, the second sub-pixel G, and the first sub-pixel R of the first LED chip of the chip group CG1 may form a pixel unit. The sum of m and n may be the pixel size of the pixel unit along the first direction x. The sum of a, b, c, d, e, and f may be the pixel size of the pixel unit along the second direction y. The sum of m and n may be equal to or different from the sum of a, b, c, d, e, and f.

[0225] In the embodiment of the present application, a plurality of LED chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array. Taking an example where a LED chip includes a pixel subgroup, a pixel subgroup includes two sub-pixels, and a plurality of LED chips form a LED chip group, in the composed pixel unit, the number of sub-pixels in the pixel unit may be different, which is described in detail below.

[0226] Reference Fig.52 and Fig.53 As shown, the LED chip group CG1 and the LED chip group CG2 each include an LED chip C1, an LED chip C2 and an LED chip C3.

[0227] The pixel unit formed includes an odd number of sub-pixels. For example, refer to Fig.52 As shown in FIG. 1 , the pixel unit PU1, the pixel unit PU2, the pixel unit PU3 and the pixel unit PU4 are formed, and each pixel unit has three sub-pixels. Fig.53 As shown, the pixel unit PU1 and the pixel unit PU2 are formed, and the number of sub-pixels in each pixel unit is 5. In other embodiments, the number of sub-pixels in a pixel unit may also be 7, 9, 11 or more odd numbers.

[0228] In each LED chip, the distance between two adjacent sub-pixels may be d1. The distance between adjacent chip groups may be d2. The distance between adjacent pixel units may be d3. The distance between two adjacent LED chips may be d4. When the number of sub-pixels in a pixel unit is an odd number, d1, d2, d3 and d4 are all equal, so that the light uniformity of each LED chip can be ensured.

[0229] Reference Fig.54 and Fig.55 As shown, the LED chip group CG1 and the LED chip group CG2 also include an LED chip C1, an LED chip C2 and an LED chip C3.

[0230] The pixel unit formed includes an even number of sub-pixels. For example, refer to Fig.54 As shown, the pixel unit PU1, the pixel unit PU2 and the pixel unit PU3 are formed, and each pixel unit has 4 sub-pixels. Fig.55 As shown, the pixel unit PU1 and the pixel unit PU2 are formed, and the number of sub-pixels in each pixel unit is 6. In other embodiments, the number of sub-pixels in the pixel unit may also be 8, 10 or more even numbers.

[0231] When the number of sub-pixels in a pixel unit is an even number, d1, d2, d3 and d4 may all be equal, or each of them may be unequal. That is, d1 may not be equal to d2, d3 or d4; d2 may not be equal to d3 or d4; d3 may not be equal to d4. Among them, d3 may be determined by the PPI of the full-color display screen prepared by the light-emitting diode chipset. The flexible adjustment of d3 can realize efficient layout of various applications from watches to large-size TVs.

[0232] In this way, d1 can be smaller than d3, and the spacing between sub-pixels in the LED chip can be flexibly adjusted, thereby adjusting the arrangement area of ​​the LED chip and avoiding waste of the arrangement area. In addition, d2 can be larger than d1, which can facilitate the arrangement between the LED chips and facilitate assembly. Of course, when d1, d2, d3 and d4 are equal, the arrangement regularity of each sub-pixel, each LED chip, each LED chip group and each pixel unit can be effectively improved, and the uniformity of light output can be improved.

[0233] Reference Fig.56 As shown, in some embodiments, the light-emitting diode chipset may further include a color conversion layer 112, which is disposed on the light-emitting side of a portion of the light-emitting diode chips and is disposed corresponding to at least a portion of the sub-pixel. The orthographic projection of the color conversion layer 112 on the surface where the corresponding sub-pixel is located may cover all areas of a single sub-pixel, or may only cover a portion of the area of ​​a single sub-pixel. The material of the color conversion layer 112 may be a quantum dot material, a phosphor material, etc. The use of the color conversion layer 112 may adjust the light-emitting wavelength of the light-emitting diode chip and enrich the types of its light-emitting wavelength.

[0234] Taking the LED chip of the upright structure as an example, the light emission wavelengths of the first sub-pixel SP1, the second sub-pixel SP2 and the color conversion layer 112 are different. In this way, the color conversion layer 112 is arranged on the light emission side of the second sub-pixel SP2 and is opposite to the second sub-pixel SP2 in a partial area, so that part of the light emission of the second sub-pixel SP2 can be converted into a light of a third light emission wavelength in addition to the light of the first light emission wavelength of the first sub-pixel SP1 and the light of the second light emission wavelength of the second sub-pixel SP2. Therefore, the LED chip can emit light of the first light emission wavelength, the second light emission wavelength and the third light emission wavelength. Fig.56 The light emitting direction is the upward direction indicated by the arrow in the figure.

[0235] Reference Fig.57 and Fig.58 As shown, in some embodiments, a dual-color LED chip can be combined with a single-color LED chip to form an RGB full-color chipset. Fig.57As shown, the LED chip C1 includes two sub-pixels (i.e., sub-pixel B and sub-pixel G) with different light emission wavelengths, that is, a dual-color LED chip. The LED chip C2 includes a sub-pixel R. The two sub-pixels of the LED chip C1 and the one sub-pixel of the LED chip C2 can form an RGB full-color pixel unit. In this embodiment, the two sub-pixels of the LED chip C1 and the one sub-pixel of the LED chip C2 can be equal in size.

[0236] Reference Fig.58 As shown, in some other embodiments, the sizes of the two sub-pixels of the LED chip C1 and the one sub-pixel of the LED chip C2 may be different. For example, the size of the sub-pixel R is larger than the size of the sub-pixel G and the sub-pixel B.

[0237] In a fourth aspect, an embodiment of the present application provides a display module, which includes a driving backplane and the above-mentioned light-emitting diode chipset, wherein the light-emitting diode chipset is disposed on the driving backplane and electrically connected to the driving backplane.

[0238] The driving backplane may be a TFT (Thin Film Transistor, thin film field effect transistor) driving backplane, or a CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) driving backplane.

[0239] As a first possible implementation method, refer to Fig.59 As shown, there are multiple LED chip groups, and the multiple LED chip groups are arranged in an array on the driving backplane 200. The driving backplane 200 can provide driving current for the multiple LED chip groups, thereby driving the multiple LED chip groups to emit light. Fig.59 It is shown that the LED chipset CG1 and the LED chipset CG2 are arranged on the driving backplane 200. In some embodiments, there are 3, 4 or more LED chipsets, and the multiple LED chipsets are arranged in an array.

[0240] The LED chip group CG1 and the LED chip group CG2 each include an LED chip C1, an LED chip C2, and an LED chip C3. Each LED chip includes a pixel subgroup, and the pixel subgroup includes two sub-pixels. In some embodiments, the number of LED chips in the LED chip group, the number of pixel subgroups and sub-pixels in the LED chip can be adjusted, and this embodiment does not limit this.

[0241] As a second possible implementation method, refer to Fig.60As shown, the driving backplane 200 includes a driving substrate 201 and a plurality of driving units 202. One driving unit 202 is electrically connected to one LED chipset, and the plurality of driving units 202 are electrically connected to the driving substrate 201. The driving unit 202 and the driving substrate 201 may also be TFT and CMOS.

[0242] A driving unit 202 and a light-emitting diode chipset can form a micro display module. Fig.60 2 shows a micro display module DBM1 and a micro display module DBM2, both of which are electrically connected to a driving substrate 201. The driving substrate 201 can provide a driving current for a driving unit 202 in the micro display module, thereby driving the light-emitting diode chipset to emit light through the driving unit 202. In some embodiments, the number of micro display modules can be 3, 4, 5 or more, and this embodiment does not limit the specific value of the number.

[0243] Fig.60 It is shown that the LED chip group CG1 and the LED chip group CG2 are electrically connected to two different driving units 202 respectively, and the two driving units 202 are electrically connected to the driving substrate 201. The LED chip group CG1 and the LED chip group CG2 each include an LED chip C1, an LED chip C2, and an LED chip C3. Each LED chip includes a pixel subgroup, and the pixel subgroup includes two sub-pixels. In this embodiment, the number of LED chip groups, the number of LED chips in the LED chip group, and the number of pixel subgroups and sub-pixels in the LED chip can all be adjusted, and this embodiment is also not limited to this.

[0244] In a fifth aspect, an embodiment of the present application provides a full-color display screen, which can be manufactured by encapsulating the above-mentioned display module.

[0245] In a sixth aspect, an embodiment of the present application provides an electronic device, which includes the above-mentioned full-color display screen. The electronic device can be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality) or a VR device (Virtual Reality), etc. When the light-emitting diode chip of the electronic device includes ultraviolet light pixels, the electronic device can also be an ultraviolet curing lamp or an ultraviolet detection lamp, etc.

[0246] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0247] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0248] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light emitting diode chip, characterized in that: The invention comprises an N-type electrode, a P-type electrode and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; the light-emitting layer comprises at least one pixel subgroup, and the pixel subgroup comprises at least two sub-pixels; The at least two sub-pixels include a first sub-pixel having a first light-emitting wavelength and a second sub-pixel having a second light-emitting wavelength, and the first light-emitting wavelength is different from the second light-emitting wavelength.

2. The light emitting diode chip according to claim 1, characterized in that: The light emitting layer includes one of the pixel subgroups.

3. The light emitting diode chip according to claim 2, characterized in that: The first sub-pixel and the second sub-pixel are arranged side by side between the N-type electrode and the P-type electrode, the first sub-pixel is in contact with the N-type electrode and the P-type electrode respectively, and the second sub-pixel is in contact with the N-type electrode and the P-type electrode respectively.

4. The light emitting diode chip according to claim 3, characterized in that: A side surface of the first sub-pixel contacts a side surface of the second sub-pixel.

5. The light emitting diode chip according to claim 3, characterized in that: An isolation structure is provided between a side surface of the first sub-pixel and a side surface of the second sub-pixel; The N-type electrode comprises a first N-type electrode and a second N-type electrode which are separate from each other, the first sub-pixel contacts the first N-type electrode, and the second sub-pixel contacts the second N-type electrode; a side of the first sub-pixel facing away from the first N-type electrode and a side of the second sub-pixel facing away from the second N-type electrode are both in contact with the P-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first sub-pixel is in contact with the first P-type electrode, and the second sub-pixel is in contact with the second P-type electrode; a side of the first sub-pixel facing away from the first P-type electrode and a side of the second sub-pixel facing away from the second P-type electrode are both in contact with the N-type electrode.

6. The light emitting diode chip according to claim 5, characterized in that: The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer; When the N-type electrode includes a first N-type electrode and a second N-type electrode separated from each other, at least a portion of the isolation structure extends into the P-type electrode; When the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, at least a portion of the isolation structure extends into the N-type electrode.

7. The light emitting diode chip according to claim 2, characterized in that: The first sub-pixel and the second sub-pixel are stacked and arranged between the N-type electrode and the P-type electrode, and the first light emission wavelength is greater than the second light emission wavelength; The first sub-pixel is disposed on the P-type electrode, the second sub-pixel is disposed on a side of the first sub-pixel away from the P-type electrode, and the N-type electrode is disposed on a side of the second sub-pixel away from the first sub-pixel; The first sub-pixel contacts a first region of the second sub-pixel, and a portion of the P-type electrode is disposed in the same layer as the first sub-pixel and contacts a second region of the second sub-pixel.

8. The light emitting diode chip according to claim 7, characterized in that: A side surface of the first region of the second sub-pixel contacts a side surface of the second region of the second sub-pixel.

9. The light emitting diode chip according to claim 7, characterized in that: An isolation structure is provided between a side surface of the first region of the second sub-pixel and a side surface of the second region of the second sub-pixel, and the isolation structure extends between the first sub-pixel and a portion of the P-type electrode disposed in the same layer; The P-type electrode comprises a first P-type electrode and a second P-type electrode which are separate from each other, a side of the first sub-pixel facing away from the second sub-pixel contacts the first P-type electrode, a side of the second region of the second sub-pixel facing away from the N-type electrode contacts the second P-type electrode; a side of the first region of the second sub-pixel and a side of the second region of the second sub-pixel facing away from the P-type electrode both contact the N-type electrode; Alternatively, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, and the surface of the first sub-pixel facing away from the second sub-pixel contacts the P-type electrode; the surface of the first region of the second sub-pixel close to the N-type electrode contacts the first N-type electrode, and the surface of the second region of the second sub-pixel close to the N-type electrode contacts the second N-type electrode.

10. The light emitting diode chip according to claim 2, characterized in that: Also includes a dimming layer, the dimming layer includes a first dimming layer and a second dimming layer; The first sub-pixel and the second sub-pixel are stacked and arranged between the N-type electrode and the P-type electrode, the first sub-pixel contacts the P-type electrode, the second sub-pixel contacts a side of the first sub-pixel away from the P-type electrode, and the N-type electrode contacts a side of the second sub-pixel away from the first sub-pixel; The first dimming layer and the second dimming layer are located on a side of the P-type electrode away from the N-type electrode, or the first dimming layer and the second dimming layer are located on a side of the N-type electrode away from the P-type electrode; The first dimming layer, the first region of the first sub-pixel and the first region of the second sub-pixel are correspondingly arranged, and the second dimming layer, the second region of the first sub-pixel and the second region of the second sub-pixel are correspondingly arranged.

11. The light emitting diode chip according to claim 10, characterized in that: The side surface of the first dimming layer is in contact with the side surface of the second dimming layer; A side surface of the first region of the first sub-pixel contacts a side surface of the second region of the first sub-pixel, and a side surface of the first region of the second sub-pixel contacts a side surface of the second region of the second sub-pixel.

12. The light emitting diode chip according to claim 10, characterized in that: A first isolation structure is provided between the side surface of the first dimming layer and the side surface of the second dimming layer; A second isolation structure is provided between a side surface of the first region of the first sub-pixel and a side surface of the first region of the first sub-pixel, and between a side surface of the first region of the second sub-pixel and a side surface of the first region of the second sub-pixel; the first isolation structure corresponds to the second isolation structure; The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first area of ​​the first sub-pixel contacts the first N-type electrode, the second area of ​​the first sub-pixel contacts the second N-type electrode; the first area of ​​the second sub-pixel and the second area of ​​the second sub-pixel both contact the P-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first area of ​​the second sub-pixel contacts the first P-type electrode, and the second area of ​​the second sub-pixel contacts the second P-type electrode; the first area of ​​the first sub-pixel and the second area of ​​the first sub-pixel both contact the N-type electrode.

13. The light emitting diode chip according to claim 10, characterized in that: The dimming layer includes a filter or a Bragg reflection layer, and the first dimming layer and the second dimming layer have different filtering wavelengths.

14. The light emitting diode chip according to claim 2, characterized in that: The pixel subgroup includes a plurality of sub-pixels, and among the plurality of sub-pixels, the number of the first sub-pixels and the number of the second sub-pixels are equal to or different from each other.

15. The light emitting diode chip according to claim 1, characterized in that: The light-emitting layer comprises at least two pixel subgroups, the at least two pixel subgroups are arranged in sequence along a first direction, and the first subpixels and the second subpixels are arranged in sequence along a second direction; wherein the first direction and the second direction intersect each other; The first light emission wavelength is greater than the second light emission wavelength.

16. The light emitting diode chip according to claim 15, characterized in that: The pixel subgroups include a first pixel subgroup and a second pixel subgroup, the first subpixel of the first pixel subgroup and the first subpixel of the second pixel subgroup have the same light emission wavelength, and the second subpixel of the first pixel subgroup and the second subpixel of the second pixel subgroup have the same light emission wavelength; Along the first direction, the first subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup; or, the first subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup.

17. The light emitting diode chip according to claim 15, characterized in that: The N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; one side of a sub-pixel facing away from the P-type electrode contacts one sub-N-type electrode; A side of the sub-pixel facing away from the N-type electrode is in contact with the P-type electrode; Alternatively, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; one side of the sub-pixel facing away from the N-type electrode contacts one sub-P-type electrode; and one side of the sub-pixel facing away from the P-type electrode contacts the N-type electrode.

18. The light emitting diode chip according to claim 15, characterized in that: The N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is less than the number of the sub-pixels; one side of one sub-pixel away from the P-type electrode contacts one sub-N-type electrode, and one side of a part of the sub-pixels away from the N-type electrode contacts the same sub-P-type electrode; Alternatively, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is less than the number of the sub-pixels; one side of one sub-pixel facing away from the N-type electrode contacts one sub-P-type electrode, and a part of the sub-pixels contact one side of the P-type electrode facing away from the P-type electrode contact the same sub-N-type electrode.

19. The light emitting diode chip according to any one of claims 1 to 18, characterized in that: The size of the light emitting diode chip is greater than or equal to 50 microns; And / or, the shape of the light-emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; and / or, the sub-pixel has a size ranging from 0.001 to 200 micrometers; And / or, the sub-pixel has a shape of any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; And / or, the shapes of different sub-pixels are the same or different; And / or, sizes of different sub-pixels are equal or different.

20. The light emitting diode chip according to any one of claims 1 to 18, characterized in that: The first sub-pixel is one of a red pixel, a green pixel, a blue pixel, and an ultraviolet pixel, and the second sub-pixel is another one of a red pixel, a green pixel, a blue pixel, and an ultraviolet pixel.

21. The light emitting diode chip according to any one of claims 1 to 18, characterized in that: It also includes a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer is in contact with a side of the P-type semiconductor layer away from the buffer layer, the N-type electrode is in contact with the N-type semiconductor layer, and the P-type electrode is in contact with the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

22. The light emitting diode chip according to claim 21, characterized in that: It also includes a substrate, which is arranged on a side of the buffer layer away from the light-emitting layer; When the reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the reflective layer is disposed on a side of the substrate away from the buffer layer.

23. The light emitting diode chip according to any one of claims 1 to 18, characterized in that: Also includes a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light emitting layer is arranged on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is arranged on a side of the light emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate.

24. A light emitting diode chipset, characterized in that: comprising a plurality of light emitting diode chips as claimed in any one of claims 1 to 23, wherein the plurality of light emitting diode chips are arranged in an array; The two adjacent LED chips include a first LED chip and a second LED chip, and a part of the sub-pixels of the first LED chip and a part of the sub-pixels of the second LED chip together form a pixel unit.

25. The light emitting diode chipset according to claim 24, characterized in that: The light emitting wavelengths of the two sub-pixels of the first light emitting diode chip and the light emitting wavelengths of one sub-pixel of the second light emitting diode chip are different.

26. The light emitting diode chipset according to claim 25, characterized in that: The entire area of ​​the two sub-pixels of the first LED chip and the entire area of ​​one sub-pixel of the second LED chip together form one pixel unit.

27. The light emitting diode chipset according to claim 25, characterized in that: Partial areas of two sub-pixels of the first LED chip and partial areas of one sub-pixel of the second LED chip together form one pixel unit.

28. The light emitting diode chipset according to claim 24, characterized in that: Among the at least two sub-pixels of the first LED chip and the at least two sub-pixels of the second LED chip, some of the sub-pixels have the same light emission wavelength; Furthermore, at least two of the sub-pixels of the first LED chip and at least two of the sub-pixels of the second LED chip together form one pixel unit.

29. The light emitting diode chipset according to any one of claims 24 to 28, characterized in that: The first LED chip and the second LED chip are both of special shapes, the first LED chip has a protruding area, and the second LED chip has a concave area; The protruding area and the recessed area are matched in shape and fit together.

30. The light emitting diode chipset according to claim 24, characterized in that: It also includes a third light-emitting diode chip, wherein the first light-emitting diode chip, the second light-emitting diode chip and the third light-emitting diode chip are arranged adjacent to each other in sequence; The first sub-pixel and the second sub-pixel of the first LED chip and the first sub-pixel of the second LED chip have different light emission wavelengths and together constitute a first pixel unit; The second sub-pixel of the second LED core, the first sub-pixel and the second sub-pixel of the third LED chip have different light emission wavelengths and together form a second pixel unit; The first LED chip, the second LED chip and the third LED chip together form a chipset; Wherein, the plurality of light emitting diode chips form a plurality of chip groups arranged in an array.

31. The light emitting diode chipset according to claim 24, characterized in that: The plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; When the pixel unit includes an odd number of sub-pixels, d1, d2, d3 and d4 are all equal; When the pixel unit includes an even number of the sub-pixels, d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are not equal to each other.

32. The light emitting diode chip set according to any one of claims 24 to 28, characterized in that: It also includes a color conversion layer, which is arranged on the light-emitting side of a portion of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel area.

33. A display module, characterized in that: It comprises a driving backplane and a light-emitting diode chipset as described in any one of claims 24-32, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

34. The display module according to claim 33, characterized in that: There are multiple light emitting diode chip groups; A plurality of the light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one of the driving units is electrically connected to one of the light emitting diode chipsets, and the plurality of driving units are electrically connected to the driving substrate.

Images