Overshoot suppression module, LED control circuit and driving system

Abstract

The invention provides an overshoot suppression module, an LED control circuit and a driving system, and the module comprises a first pull-down unit, one end of which is connected to a grid electrode of a power switch tube, and the other end of which is grounded; when current overshoot occurs at the power-on moment, the grid electrode of the power switch tube is pulled down so as to restrain the current overshoot; wherein the first pull-down unit comprises a delay circuit and a first NMOS pull-down tube; the time delay circuit generates a first pull-down control signal of a first preset duration when being powered on; the drain electrode of the first NMOS pull-down tube is connected with the grid electrode of the power switch tube, the source electrode of the first NMOS pull-down tube is grounded, the grid electrode of the first NMOS pull-down tube is connected with the output end of the time delay circuit, and the first pull-down control signal controls the first NMOS pull-down tube to be switched on within a first preset duration after power-on. According to the invention, a pull-down path is provided, the grid leakage current is discharged at the instant of quick power-on of the power supply, the grid of the power switch tube is prevented from being raised to the breakover voltage, the output instant large current is reduced or inhibited, and meanwhile, the damage to internal devices of a chip caused by the overlarge grid leakage current is also avoided.

Description

Technical Field

[0001] The present invention relates to the field of LED driving, and in particular to an overshoot suppression module, an LED control circuit and a driving system. Background Art

[0002] The linear LED control circuit is a common control circuit. The commonly used method of driving large current is to add a controller to an external drive power MOS. The instability of the power supply will cause reliability problems for peripheral applications and devices. When the power is quickly powered on, the gate of the power MOS will be instantly coupled and the voltage will be raised due to the influence of the large gate-drain parasitic capacitance of the power MOS, thereby turning on the power MOS tube, resulting in a large overshoot current in the output current of the LED. This overshoot current will not only damage peripheral devices (such as LED lights), but may also damage the chip instantly due to overcurrent or overvoltage problems. With the higher requirements for chips in peripheral applications such as car lights, it is expected to suppress or eliminate this overshoot current.

[0003] like Figure 1 As shown, it is a schematic diagram of a linear constant current LED control circuit 1. The gate of the power device PowerNMOS is connected to the output terminal GATE of the power device gate controller 11, and the source terminal of the power device PowerNMOS is connected to the external sampling resistor RCS to the ground, and is also connected to the sampling input terminal CS of the power device gate controller 11. The drain terminal OUT of the power device PowerNMOS is connected to the output load, such as an LED lamp. The positive phase terminal of the output load is connected to the high voltage power supply VIN. The power device gate controller 11 includes two parts: a low dropout regulator 111 and an operational amplifier 112.

[0004] The working process of the linear constant current LED control circuit 1 at the moment of power-on is as follows: when the high voltage power supply VIN quickly rises from 0V to the required voltage within the △T time, since the output is not connected to any device that inhibits the change of the output current (such as an inductor, etc.), the negative end of the load LED lamp, that is, the OUT end of the power device PowerNMOS, also quickly rises to the voltage value of VIN-VLED, that is, VOUT=VIN-VLED, and affected by the parasitic capacitance Cgd between the gate and drain of the power device PowerNMOS, a current ICgd will be generated from the OUT end of the power device PowerNMOS to the gate GATE of the power device PowerNMOS. When the parasitic capacitance Cgd of the power device PowerNMOS is small, the current can be released quickly; but when the capacitance Cgd is large, because the current cannot obtain a fast release path, it will be coupled to the gate GATE of the power device PowerNMOS and raise the gate voltage VGATE, so that the gate voltage VGATE is higher than the threshold voltage Vth of the power device PowerNMOS, and then the power device PowerNMOS is turned on, so that it instantly appears a large current Ipulse similar to a power supply to ground short circuit.

[0005] In order to avoid the overshoot current, the overshoot is suppressed in the circuit by current limiting resistors Rlimit1 and Rlimit2. The current limiting resistor Rlimit1 acts as a gate resistor to reduce the current on the gate to prevent the internal devices of the power device gate controller 11 from being damaged due to overvoltage; the current limiting resistor Rlimit2 reduces the instantaneous short-circuit current by connecting a resistor in series with the high-voltage power supply VIN. Both current limiting resistors have limitations. Among them, the current limiting resistor Rlimit1 slows down the response speed of the operational amplifier 112, especially when the operational amplifier 112 is turned on or off with a pulse width modulation PWM signal, which will affect the final pulse width modulation PWM loop output current accuracy; while the current limiting resistor Rlimit2 increases the cost of peripheral applications.

[0006] Therefore, how to suppress the overshoot current without affecting the output current accuracy and increasing the cost has become one of the problems that technical personnel in this field need to solve urgently.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an overshoot suppression module, an LED control circuit and a drive system, which are used to solve the problems that the overshoot suppression scheme in the prior art affects the control accuracy of the output current and increases the cost.

[0009] In order to achieve the above-mentioned object and other related objects, the present invention provides an overshoot suppression module for suppressing the overshoot current of an LED, wherein the overshoot suppression module at least comprises:

[0010] A first pull-down unit, one end of which is connected to the gate of a power switch tube for adjusting the output current of the LED, and the other end of which is grounded; when a current overshoot occurs at the moment of power-on, the gate of the power switch tube is pulled down to suppress the current overshoot;

[0011] Among them, the first pull-down unit includes a delay circuit and a first NMOS pull-down tube; the delay circuit generates a first pull-down control signal of a first preset duration when powered on; the drain of the first NMOS pull-down tube is connected to the gate of the power switch tube, the source is grounded, and the gate is connected to the output end of the delay circuit, and the first pull-down control signal controls the first NMOS pull-down tube to be turned on within the first preset duration after power-on.

[0012] Optionally, the delay circuit includes a current source, a first capacitor, a first NMOS transistor, a Schmitt trigger, a first PMOS transistor and a second NMOS transistor;

[0013] The input end of the current source is connected to the working voltage, and the output end is grounded via the first NMOS tube; the gate of the first NMOS tube receives an enable signal;

[0014] The upper plate of the first capacitor is connected to the output end of the current source, and the lower plate is grounded; the input end of the Schmitt trigger is connected to the upper plate of the first capacitor;

[0015] The gates of the first PMOS tube and the second NMOS tube are connected to the output end of the Schmitt trigger; the source of the first PMOS tube is connected to the working voltage, and the drain is connected to the drain of the second NMOS tube and outputs the first pull-down control signal; the source of the second NMOS tube is grounded.

[0016] More optionally, the delay circuit further includes a first resistor, one end of which is connected to the drain of the first PMOS tube, and the other end of which is connected to the drain of the second NMOS tube and outputs the first pull-down control signal.

[0017] More optionally, the overshoot suppression module also includes a second resistor and a clamping unit; one end of the second resistor is connected to the drain of the power switch tube, and the other end is grounded via the clamping unit; the connection node between the second resistor and the clamping unit is connected to the gate of the first NMOS pull-down tube.

[0018] More optionally, the clamping unit includes a voltage regulator tube, a cathode of the voltage regulator tube is connected to the second resistor, and an anode is grounded; or, the clamping unit includes at least two NMOS tubes connected in series, wherein the gate and drain of each NMOS tube are connected together.

[0019] More optionally, the overshoot suppression module further includes a second pull-down unit, which detects the gate voltage of the power switch tube and pulls down the gate potential of the power switch tube when an overshoot is detected; the second pull-down unit includes a gate control circuit and a second NMOS pull-down tube;

[0020] The gate control circuit is connected to the gate of the power switch tube, and generates a second pull-down control signal of a second preset duration when the gate voltage of the power switch tube becomes high instantly;

[0021] The drain of the second NMOS pull-down tube is connected to the gate of the power switch tube, the source is grounded, and the gate is connected to the output end of the gate control circuit. The second pull-down control signal controls the second NMOS pull-down tube to be turned on within a second preset time after power-on.

[0022] More optionally, the gate control circuit includes a third resistor, a second capacitor, a second PMOS transistor, a third NMOS transistor, a fourth resistor and a fifth resistor;

[0023] One end of the third resistor is connected to the gate of the power switch tube, and the other end is connected to the upper plate of the second capacitor; the lower plate of the second capacitor is grounded;

[0024] One end of the fourth resistor is connected to the gate of the power switch tube, and the other end is connected to the source of the second PMOS tube;

[0025] The gates of the second PMOS tube and the third NMOS tube are connected to the upper plate of the second capacitor, the drain of the second PMOS tube is connected to the drain of the third NMOS tube and outputs the second pull-down control signal, and the source of the third NMOS tube is grounded;

[0026] One end of the fifth resistor is connected to the drains of the second PMOS transistor and the third NMOS transistor, and the other end is grounded.

[0027] More optionally, a first current limiting resistor is further connected in series between the second pull-down unit and the gate of the power switch tube.

[0028] More optionally, the equivalent on-resistance of the first pull-down tube and / or the second pull-down tube satisfies:

[0029]

[0030] Among them, R equal is the equivalent on-resistance, V th is the threshold voltage of the power switch tube, C gd is the parasitic capacitance between the drain and gate of the power switch tube; ΔT is the charging time of the parasitic capacitance when powered on; V out is the drain voltage of the gate of the power switch tube.

[0031] Optionally, the overshoot suppression module further includes a third pull-down unit, and the third pull-down unit includes a first operational amplifier and a PMOS clamp tube;

[0032] The first operational amplifier obtains a sampling voltage of the LED output current, and generates a third pull-down control signal when the sampling voltage is greater than or equal to a reference voltage;

[0033] The source of the PMOS clamp tube is connected to the gate of the power switch tube, the drain is grounded, and the gate is connected to the output end of the first operational amplifier. When the third pull-down control signal is valid, the PMOS clamp tube is controlled to be turned on.

[0034] More optionally, a second current limiting resistor is connected in series between the third pull-down unit and the gate of the power switch tube.

[0035] To achieve the above-mentioned object and other related objects, the present invention further provides an LED control circuit, wherein the LED control circuit at least comprises:

[0036] A low voltage regulator, a second operational amplifier and the above-mentioned overshoot suppression module;

[0037] The low voltage regulator is connected to an external first high voltage power supply, converts the first high voltage power supply into a low voltage working voltage, and supplies power to the second operational amplifier and the overshoot suppression module;

[0038] The second operational amplifier receives the sampling voltage and the reference voltage of the LED output current, and is used to generate a gate control signal of the power switch tube;

[0039] The overshoot suppression module is connected to the gate of the power switch tube to provide a discharge path.

[0040] To achieve the above-mentioned object and other related objects, the present invention further provides an LED driving system, the LED driving system at least comprising:

[0041] A first high-voltage power supply, a second high-voltage power supply, an LED load, a power switch tube, a sampling resistor and the above-mentioned LED control circuit;

[0042] The first high-voltage power supply is connected to the LED control circuit, and the second high-voltage power supply is connected to the positive electrode of the LED load; the drain of the power switch tube is connected to the negative electrode of the LED load, the gate is connected to the output end of the LED control circuit, and the source is grounded via the sampling resistor and provides a sampling voltage for the LED control circuit;

[0043] The first high-voltage power supply and the second high-voltage power supply are the same power supply or different power supplies.

[0044] As described above, the overshoot suppression module, LED control circuit and driving system of the present invention have the following beneficial effects:

[0045] The overshoot suppression module, LED control circuit and drive system of the present invention provide a pull-down path to ensure that the gate leakage current is discharged at the moment of rapid power-on of the power supply, so as to prevent the gate of the power switch tube from being raised to its conduction voltage, reduce or suppress the instantaneous large current of the output, and avoid the overshoot of the output nearly short-circuited due to the conduction of the power switch tube, without affecting the control accuracy of the LED output current and increasing the peripheral application cost; at the same time, it also prevents excessive gate leakage current from flowing to the internal low-voltage power supply, causing damage to the internal devices of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Shown is a structural schematic diagram of a linear constant current LED control circuit.

[0047] Figure 2 It is a schematic structural diagram of the overshoot suppression module of the present invention.

[0048] Figure 3 Shown is a schematic structural diagram of the delay circuit of the present invention.

[0049] Figure 4 It is a schematic structural diagram of the clamping unit of the present invention.

[0050] Figure 5 Shown is a schematic structural diagram of the gate control circuit of the present invention.

[0051] Figure 6 Shown is a schematic structural diagram of the LED control circuit and drive system of the present invention.

[0052] Component number description

[0053] 1 Linear constant current LED control circuit

[0054] 11 Power Device Gate Controller

[0055] 111 Low Dropout Regulator

[0056] 112 Operational Amplifier

[0057] 2 LED control circuit

[0058] 21 Overshoot suppression module

[0059] 21a First pull-down unit

[0060] 21b Second pull-down unit

[0061] 21c Third pull-down unit

[0062] 211 Delay Circuit

[0063] 212 Clamping Unit

[0064] 213 Gate Control Circuit

[0065] 214 First Op Amp

[0066] 22 Low voltage regulator

[0067] 23 Second op amp DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] See also Figure 2 to Figure 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0070] like Figure 2 As shown, the present invention provides an overshoot suppression module 21 for suppressing the overshoot current of an LED, and the overshoot suppression module 21 comprises:

[0071] The first pull-down unit 21a has one end connected to the gate GATE of the power switch tube for adjusting the LED output current and the other end grounded; when a current overshoot occurs at the moment of power-on, the gate GATE of the power switch tube is pulled down to suppress the current overshoot;

[0072] Among them, the first pull-down unit 21a includes a delay circuit 211 and a first NMOS pull-down tube PDN1; the delay circuit 211 generates a first pull-down control signal NCTRL1 of a first preset duration when powered on; the drain of the first NMOS pull-down tube PDN1 is connected to the gate GATE of the power switch tube, the source is grounded, and the gate is connected to the output end of the delay circuit 211, and the first pull-down control signal NCTRL1 controls the first NMOS pull-down tube PDN1 to be turned on within the first preset duration after power-on.

[0073] Specifically, the delay circuit 211 generates the first pull-down control signal NCTRL1 at the moment of power-on. The first pull-down control signal NCTRL1 is at a high level within the first preset time length Tdelay of power-on to turn on the first NMOS pull-down tube PDN1, thereby suppressing the overshoot current at the moment of power-on. The first preset time length Tdelay is related to the time length of the overshoot current. Generally, after the overshoot current ends, the first pull-down control signal NCTRL1 jumps to a low level. In actual applications, it can be set according to needs to suppress the overshoot current at the moment of power-on. Figure 3As shown, in this embodiment, the delay circuit 211 includes a current source IB, a first capacitor C1, a first NMOS transistor MN1, a Schmitt trigger SM, a first PMOS transistor MP1 and a second NMOS transistor MN2. The input end of the current source IB is connected to the working voltage VDD, and the output end is grounded via the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 receives an enable signal EN. The upper plate of the first capacitor C1 is connected to the output end of the current source IB, and the lower plate is grounded. The input end of the Schmitt trigger SM is connected to the upper plate of the first capacitor C1. The gates of the first PMOS transistor MP1 and the second NMOS transistor MN2 are connected to the output end of the Schmitt trigger SM. The source of the first PMOS transistor MP1 is connected to the working voltage VDD, and the drain is connected to the drain of the second NMOS transistor MN2 and outputs the first pull-down control signal NCTRL1; the source of the second NMOS transistor MN2 is grounded. As another example, the delay circuit 211 further includes a first resistor R1 , one end of which is connected to the drain of the first PMOS transistor MP1 , and the other end of which is connected to the drain of the second NMOS transistor MN2 and outputs the first pull-down control signal NCTRL1 . When the LED load is powered on, the enable signal EN jumps to a low level, the current source IB charges the first capacitor C1, and the voltage on the first capacitor C1 gradually increases; when the voltage on the first capacitor C1 is less than the flip voltage of the Schmitt trigger SM, the Schmitt trigger SM outputs a low level signal, the first PMOS tube MP1 is turned on, the second NMOS tube MN2 is turned off, and the first pull-down control signal NCTRL1 is kept at a high level to turn on the first NMOS pull-down tube PDN1 (the current flowing through the first NMOS pull-down tube PDN1 is Ipd1); after the first preset time length Tdelay from the start of power-on, the voltage on the first capacitor C1 is greater than the flip voltage of the Schmitt trigger SM, the Schmitt trigger SM outputs a high level signal, the first PMOS tube MP1 is turned off, the second NMOS tube MN2 is turned on, and the first pull-down control signal NCTRL1 jumps to a low level to turn off the first NMOS pull-down tube PDN1, and the overshoot current is suppressed at this time. Any circuit structure that can generate a first pull-down control signal that turns on the first NMOS pull-down transistor PDN1 and maintains a first preset duration when powered on is applicable to the present invention, and is not limited to this embodiment.

[0074] Specifically, in order to ensure that most of the large current at the moment of turning on is absorbed by the first NMOS pull-down tube PDN1, in this embodiment, the equivalent on-resistance of the first NMOS pull-down tube PDN1 is further limited. gd, when powered on, the parasitic capacitance C gd The charging time is △T (for example, 1us fast power-on), then the current flowing to the gate GATE of the power switch tube instantly is (V out =I*R=Vth, the equivalent on-resistance R of the pull-down tube is calculated. equal satisfy: In this embodiment, the desired equivalent on-resistance is obtained by setting the width-to-length ratio of the first NMOS pull-down tube PDN1. The larger the width-to-length ratio of the first NMOS pull-down tube PDN1, the smaller the corresponding equivalent on-resistance, which will not be elaborated here.

[0075] like Figure 2 As shown, as another implementation of the present invention, the overshoot suppression module 21 also includes a second resistor R2 and a clamping unit 212. One end of the second resistor R2 is connected to the drain OUT of the power switch tube, and the other end is grounded via the clamping unit 212. The connection node between the second resistor R2 and the clamping unit 212 is connected to the gate of the first NMOS pull-down tube PDN1. The second resistor R2 and the clamping unit 212 detect whether the drain OUT of the power switch tube generates an overshoot current, and generate a turn-on control signal for the first NMOS pull-down tube PDN1 when the overshoot current is detected; the voltage on the clamping unit 212 can be set according to actual application needs, and can ensure that the first NMOS pull-down tube PDN1 is turned on without damaging the first NMOS pull-down tube PDN1. As an example, the clamping unit 212 includes a voltage regulator tube ZD1, the cathode of which is connected to the second resistor R2, and the anode is grounded. As another example, as Figure 4As shown, the clamping unit 212 includes at least two NMOS tubes connected in series, wherein the gate and drain of each NMOS tube are connected together. In this example, three NMOS tubes are set, and the threshold voltage Vthn of each NMOS tube is about 2V, thereby obtaining a voltage of about 3*Vthn=6V. In actual use, the number of devices connected in series can be set according to the voltage requirements on the clamping unit 212. The second resistor R2 and the clamping unit 212 provide a high-level voltage to the gate of the first NMOS pull-down tube PDN1 only when the control circuit where the overshoot suppression module 21 is located is not powered. When the control circuit where the overshoot suppression module 21 is located is powered, after the delay time of the first preset time length Tdelay, the output signal of the delay circuit 211 will be pulled low, and the first NMOS pull-down tube PDN1 will be turned off.

[0076] It should be noted that when the second resistor R2 and the clamping unit 212 are set, the first resistor R1 needs to be set in the delay circuit 211. At this time, the second resistor R2 is also connected in series between the first pull-down control signal NCTRL1 and the drain OUT of the power switch tube. When the voltage of the drain OUT of the power switch tube becomes high instantly, the potential of the first pull-down control signal NCTRL1 will be raised through the second resistor R2 (high-voltage resistor), and then the operating voltage VDD (low-voltage power supply inside the control circuit) will be raised through the parasitic diode of the first PMOS tube MP1, thereby causing malfunction inside the control circuit, so it is necessary to be isolated through the first resistor R1.

[0077] like Figure 2 As shown, as another implementation of the present invention, the overshoot suppression module 21 also includes a second pull-down unit 21b, which detects the gate voltage of the power switch tube and pulls down the gate potential of the power switch tube when an overshoot is detected. The second pull-down unit 21b includes a gate control circuit 213 and a second NMOS pull-down tube PDN2. The gate control circuit 213 is connected to the gate of the power switch tube, and generates a second pull-down control signal NCTRL2 of a second preset duration when the gate voltage of the power switch tube becomes high due to the overshoot current. The drain of the second NMOS pull-down tube PDN2 is connected to the gate GATE of the power switch tube, the source is grounded, and the gate is connected to the output end of the gate control circuit 213. The second pull-down control signal NCTRL2 controls the second NMOS pull-down tube PDN2 to be turned on within the second preset duration after power-on.

[0078] Specifically, in this embodiment, the gate control circuit 213 includes a third resistor R3, a second capacitor C2, a second PMOS transistor MP2, a third NMOS transistor MN3, a fourth resistor R4 and a fifth resistor R5. One end of the third resistor R3 is connected to the gate GATE of the power switch tube, and the other end is connected to the upper plate of the second capacitor C2. The lower plate of the second capacitor C2 is grounded. One end of the fourth resistor R4 is connected to the gate GATE of the power switch tube, and the other end is connected to the source of the second PMOS transistor MP2. The gates of the second PMOS transistor MP2 and the third NMOS transistor MN3 are connected to the upper plate of the second capacitor C2, and the drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3 and outputs the second pull-down control signal NCTRL2. The source of the third NMOS transistor MN3 is grounded. One end of the fifth resistor R5 is connected to the drains of the second PMOS transistor MP2 and the third NMOS transistor MN3, and the other end is grounded. The gate control circuit 213 detects whether the drain OUT of the power switch tube generates an overshoot current based on the gate voltage of the power switch tube, and turns on the second NMOS pull-down tube PDN2 to release the overshoot current Icgd when the overshoot is detected. When the drain OUT of the power switch tube overshoots, the voltage of the gate GATE of the power switch tube also suddenly increases due to coupling. At this time, due to the existence of the second capacitor C2, the gate voltages of the second PMOS tube MP2 and the third NMOS tube MN3 are low level, the second PMOS tube MP2 is turned on, and the third NMOS tube MN3 is turned off, so that the gate potential of the second NMOS pull-down tube PDN2 is also raised, and the second NMOS pull-down tube PDN2 is turned on (the current flowing through the second NMOS pull-down tube PDN2 is Ipd2), thereby releasing the overshoot current Icgd, and preventing the voltage of the gate GATE of the power switch tube from becoming high. The size of the second capacitor C2 is related to the second preset time length, and the second capacitor C2 and the second preset time length can be set as needed; as an example, the second preset time length is less than the first preset time length. Any circuit structure that can generate a second pull-down control signal that turns on the second NMOS pull-down tube PDN2 and maintains the second preset time length when an overshoot is detected is applicable to the present invention, and is not limited to this embodiment.

[0079] Specifically, in this embodiment, the equivalent on-resistance of the second NMOS pull-down tube PDN2 can satisfy the same relationship as the first NMOS pull-down tube PDN1 to improve the effect of overshoot suppression. In actual use, the equivalent on-resistance of the second NMOS pull-down tube PDN2 can also be greater than that of the first NMOS pull-down tube PDN1, as long as the effect of overshoot suppression can be achieved.

[0080] like Figure 2 As shown, as another implementation of the present invention, the overshoot suppression module 21 also includes a third pull-down unit 21c, and the third pull-down unit 21c determines whether an overshoot current is generated based on the sampling voltage VCS of the LED output current, and provides a discharge path for the gate GATE of the power switch tube when the overshoot current is generated. The third pull-down unit 21c includes a first operational amplifier 214 and a PMOS clamp tube CLP; the first operational amplifier 214 obtains the sampling voltage VCS of the LED output current, and generates a third pull-down control signal when the sampling voltage VCS is greater than or equal to the reference voltage VREF1; as an example, the non-inverting input terminal of the first operational amplifier 214 is connected to the reference voltage VREF1, and the inverting input terminal is connected to the sampling voltage VCS, and the third pull-down control signal is output. In actual use, the relationship between the input terminal polarity and the corresponding input signal can be set as needed, and the logic of the present invention can be satisfied. The source of the PMOS clamp tube CLP is connected to the gate GATE of the power switch tube, the drain is grounded, and the gate is connected to the output end of the first operational amplifier 214. When the third pull-down control signal is valid (the low level is valid in this embodiment), the PMOS clamp tube CLP is controlled to be turned on (the current flowing through the PMOS clamp tube CLP is Ipd3).

[0081] like Figure 2 As shown, as another implementation of the present invention, a first current limiting resistor is also connected in series between the second pull-down unit 21b and the gate GATE of the power switch tube; a second current limiting resistor is also connected in series between the third pull-down unit 21c and the gate GATE of the power switch tube. It should be noted that the first current limiting resistor and the second current limiting resistor can be added to the circuit or omitted, and are not limited to this embodiment. In this example, the first current limiting resistor and the second current limiting resistor are implemented using the same current limiting resistor Rlimit.

[0082] like Figure 2 to Figure 5As shown, when the control circuit where the overshoot suppression module 21 is located shares the same high-voltage power supply with the LED load, or the control circuit where the overshoot suppression module 21 is located is powered on at the same time as the LED load, if the high-voltage power supply rises rapidly, the overshoot current is suppressed based on the first pull-down unit 21a. During operation, if the high-voltage power supply of the LED load changes suddenly, the operational amplifier that generates the gate control signal of the power switch tube will not be adjusted in time, and the drain OUT of the power switch tube will also produce an overshoot; at this time, the overshoot current is suppressed based on the second pull-down unit 21b and the third pull-down unit 21c. In the process of the high-voltage power supply of the LED load being powered on slowly, if the operational amplifier that generates the gate control signal of the power switch tube is not adjusted in time, the overshoot current is suppressed based on the third pull-down unit 21c. When the control circuit where the overshoot suppression module 21 is located is connected to different power supplies from the LED load, and the control circuit where the overshoot suppression module 21 is located is not powered on, if an overshoot current is generated during the power-on process of the LED load, the overshoot current is suppressed based on the second resistor R2 and the clamping unit 212. This embodiment provides three discharge paths (a first pull-down unit, a second pull-down unit, and a third pull-down unit) for the overshoot current Icgd. In actual use, any one of the discharge paths, a combination of any two discharge paths, or three discharge paths can be configured as needed, and this embodiment is not limited thereto.

[0083] like Figure 6 As shown, the present invention further provides an LED control circuit 2, and the LED control circuit 2 at least includes:

[0084] An overshoot suppression module 21 , a low voltage regulator 22 and a second operational amplifier 23 .

[0085] like Figure 6 As shown, the low voltage regulator 22 is connected to an external first high voltage power supply, converts the first high voltage power supply into a low voltage working voltage VDD, and supplies power to the second operational amplifier 23 and the overshoot suppression module 21 .

[0086] like Figure 6 As shown, the second operational amplifier 23 receives the sampling voltage VCS of the LED output current and the reference voltage VREF2, and is used to generate a gate control signal of the power switch tube to achieve constant current output.

[0087] Specifically, as an example, the reference voltage VREF1 is higher than the base voltage VREF2, and the reference voltage VREF1 can be set to be 10% to 20% higher than the base voltage VREF2.

[0088] like Figure 6As shown, the overshoot suppression module 21 is connected to the gate GATE of the power switch tube to provide a discharge path. The circuit structure and working principle of the overshoot suppression module 21 are as mentioned above and will not be described in detail here.

[0089] Specifically, in this embodiment, the overshoot suppression module 21 and the second operational amplifier 23 in the LED control circuit 2 are both composed of low-voltage devices.

[0090] like Figure 6 As shown, the present invention also provides an LED driving system, the LED driving system comprising:

[0091] A first high-voltage power supply, a second high-voltage power supply, an LED load, a power switch tube Q, a sampling resistor RCS and the LED control circuit 2.

[0092] The first high-voltage power supply is connected to the LED control circuit 2, and the second high-voltage power supply is connected to the positive electrode of the LED load. The drain of the power switch tube Q is connected to the negative electrode of the LED load, the gate is connected to the output end of the LED control circuit 2, and the source is grounded via the sampling resistor Rcs and provides a sampling voltage for the LED control circuit 2. The first high-voltage power supply and the second high-voltage power supply are the same power supply or different power supplies. In this embodiment, the first high-voltage power supply and the second high-voltage power supply are the same power supply VIN.

[0093] like Figure 6 As shown, the present invention can also prevent excessive gate leakage current Ileak from flowing to the internal low-voltage power supply (VDD) through the overshoot module 21, thereby damaging the internal devices of the chip.

[0094] In summary, the present invention provides an overshoot suppression module, an LED control circuit and a driving system, comprising: a first pull-down unit, one end of which is connected to the gate of a power switch tube for adjusting the output current of an LED, and the other end is grounded; when a current overshoot occurs at the moment of power-on, the gate of the power switch tube is pulled down to suppress the current overshoot; wherein the first pull-down unit comprises a delay circuit and a first NMOS pull-down tube; the delay circuit generates a first pull-down control signal of a first preset duration at power-on; the drain of the first NMOS pull-down tube is connected to the gate of the power switch tube, the source is grounded, and the gate is connected to the output end of the delay circuit, and the first pull-down control signal controls the first NMOS pull-down tube to be turned on within the first preset duration after power-on. The overshoot suppression module, the LED control circuit and the driving system of the present invention provide a pull-down path to ensure that the gate leakage current is discharged at the moment of rapid power-on of the power supply, so as to prevent the gate of the power switch tube from being raised to its conduction voltage, reduce or suppress the output instantaneous large current, and also prevent excessive gate leakage current from flowing to the internal low-voltage power supply, causing damage to the internal components of the chip. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An overshoot suppression module, used to suppress the overshoot current of an LED, characterized in that: The overshoot suppression module at least includes: A first pull-down unit, one end of which is connected to the gate of a power switch tube for adjusting the output current of the LED, and the other end of which is grounded; When a current overshoot occurs at the moment of power-on, the gate of the power switch tube is pulled down to suppress the current overshoot; Among them, the first pull-down unit includes a delay circuit and a first NMOS pull-down tube; the delay circuit generates a first pull-down control signal of a first preset duration when powered on; the drain of the first NMOS pull-down tube is connected to the gate of the power switch tube, the source is grounded, and the gate is connected to the output end of the delay circuit, and the first pull-down control signal controls the first NMOS pull-down tube to be turned on within the first preset duration after power-on.

2. The overshoot suppression module according to claim 1, characterized in that: The delay circuit includes a current source, a first capacitor, a first NMOS transistor, a Schmitt trigger, a first PMOS transistor and a second NMOS transistor; The input end of the current source is connected to the working voltage, and the output end is grounded via the first NMOS tube; the gate of the first NMOS tube receives an enable signal; The upper plate of the first capacitor is connected to the output end of the current source, and the lower plate is grounded; the input end of the Schmitt trigger is connected to the upper plate of the first capacitor; The gates of the first PMOS tube and the second NMOS tube are connected to the output end of the Schmitt trigger; the source of the first PMOS tube is connected to the working voltage, and the drain is connected to the drain of the second NMOS tube and outputs the first pull-down control signal; the source of the second NMOS tube is grounded.

3. The overshoot suppression module according to claim 2, characterized in that: The delay circuit also includes a first resistor, one end of which is connected to the drain of the first PMOS tube, and the other end of which is connected to the drain of the second NMOS tube and outputs the first pull-down control signal.

4. The overshoot suppression module according to claim 1 or 3, characterized in that: The overshoot suppression module also includes a second resistor and a clamping unit; one end of the second resistor is connected to the drain of the power switch tube, and the other end is grounded via the clamping unit; the connection node between the second resistor and the clamping unit is connected to the gate of the first NMOS pull-down tube.

5. The overshoot suppression module according to claim 4, characterized in that: The clamping unit includes a voltage regulator tube, a cathode of the voltage regulator tube is connected to the second resistor, and an anode of the voltage regulator tube is grounded; or, the clamping unit includes at least two NMOS tubes connected in series, wherein the gate and drain of each NMOS tube are connected together.

6. The overshoot suppression module according to any one of claims 1 to 3, characterized in that: The overshoot suppression module further includes a second pull-down unit, which detects the gate voltage of the power switch tube and pulls down the gate potential of the power switch tube when an overshoot is detected; the second pull-down unit includes a gate control circuit and a second NMOS pull-down tube; The gate control circuit is connected to the gate of the power switch tube, and generates a second pull-down control signal of a second preset duration when the gate voltage of the power switch tube becomes high instantly; The drain of the second NMOS pull-down tube is connected to the gate of the power switch tube, the source is grounded, and the gate is connected to the output end of the gate control circuit. The second pull-down control signal controls the second NMOS pull-down tube to be turned on within a second preset time after power-on.

7. The overshoot suppression module according to claim 6, characterized in that: The gate control circuit includes a third resistor, a second capacitor, a second PMOS transistor, a third NMOS transistor, a fourth resistor and a fifth resistor; One end of the third resistor is connected to the gate of the power switch tube, and the other end is connected to the upper plate of the second capacitor; the lower plate of the second capacitor is grounded; One end of the fourth resistor is connected to the gate of the power switch tube, and the other end is connected to the source of the second PMOS tube; The gates of the second PMOS tube and the third NMOS tube are connected to the upper plate of the second capacitor, the drain of the second PMOS tube is connected to the drain of the third NMOS tube and outputs the second pull-down control signal, and the source of the third NMOS tube is grounded; One end of the fifth resistor is connected to the drains of the second PMOS transistor and the third NMOS transistor, and the other end is grounded.

8. The overshoot suppression module according to claim 6, characterized in that: A first current limiting resistor is also connected in series between the second pull-down unit and the gate of the power switch tube.

9. The overshoot suppression module according to claim 6, characterized in that: The equivalent on-resistance of the first pull-down tube and / or the second pull-down tube satisfies: Among them, R equal is the equivalent on-resistance, V th is the threshold voltage of the power switch tube, C gd is the parasitic capacitance between the drain and gate of the power switch tube; ΔT is the charging time of the parasitic capacitance when powered on; V out is the drain voltage of the gate of the power switch tube.

10. The overshoot suppression module according to claim 1, characterized in that: The overshoot suppression module further includes a third pull-down unit, and the third pull-down unit includes a first operational amplifier and a PMOS clamp tube; The first operational amplifier obtains a sampling voltage of the LED output current, and generates a third pull-down control signal when the sampling voltage is greater than or equal to a reference voltage; The source of the PMOS clamp tube is connected to the gate of the power switch tube, the drain is grounded, and the gate is connected to the output end of the first operational amplifier. When the third pull-down control signal is valid, the PMOS clamp tube is controlled to be turned on.

11. The overshoot suppression module according to claim 10, characterized in that: A second current limiting resistor is also connected in series between the third pull-down unit and the gate of the power switch tube.

12. An LED control circuit, characterized in that: The LED control circuit at least includes: A low voltage regulator, a second operational amplifier and an overshoot suppression module as claimed in any one of claims 1 to 11; The low voltage regulator is connected to an external first high voltage power supply, converts the first high voltage power supply into a low voltage working voltage, and supplies power to the second operational amplifier and the overshoot suppression module; The second operational amplifier receives the sampling voltage and the reference voltage of the LED output current, and is used to generate a gate control signal of the power switch tube; The overshoot suppression module is connected to the gate of the power switch tube to provide a discharge path.

13. An LED driving system, characterized in that: The LED driving system at least comprises: A first high-voltage power supply, a second high-voltage power supply, an LED load, a power switch tube, a sampling resistor, and an LED control circuit as claimed in claim 12; The first high-voltage power supply is connected to the LED control circuit, and the second high-voltage power supply is connected to the positive electrode of the LED load; the drain of the power switch tube is connected to the negative electrode of the LED load, the gate is connected to the output end of the LED control circuit, and the source is grounded via the sampling resistor and provides a sampling voltage for the LED control circuit; The first high-voltage power supply and the second high-voltage power supply are the same power supply or different power supplies.

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