FPGA-based SSD controller prototype verification method and device

Abstract

The invention provides an SSD controller prototype verification method and device based on an FPGA, and the method comprises the steps: carrying out the module division of an RTL code of an SSD controller, and obtaining a plurality of RTL submodules; the method comprises the following steps: deploying a plurality of RTL sub-modules on a plurality of FPGAs (Field Programmable Gate Array) respectively, wherein the plurality of RTL sub-modules communicate with one another through physical connection among Serdes ports of the FPGAs; deploying corresponding preset test parameters and communication port logic according to the test scheme; and starting a system-level test to obtain a test result. According to the method, prototype verification of a large SSD controller chip can be supported, data interaction among multiple interconnected FPGAs is completed through a Serdes port, a user can select a synchronous / asynchronous data transmission scheme according to an actual verification background on the premise that the reliability and efficiency of data transmission are improved, and the data transmission efficiency is improved. The performance of the SSD controller chip in a real working scene is obtained through verification performance analysis, and on the basis of the advantages, the method can efficiently and accurately discover potential problems in the chip research and development process before chip tape-out, and the chip tape-out quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design verification, and in particular to an FPGA-based SSD controller prototype verification method and device. Background Art

[0002] FPGA prototype verification is a key process before chip tape-out, which can facilitate the early development of firmware by software to verify the reliability of chip functions. More importantly, it can help verification personnel identify the normal working scenarios of the chip in advance and understand the true working performance of the chip.

[0003] Since traditional single FPGAs cannot meet the deployment of the prototype verification platform for large SSD controllers, the RTL of the SSD controller usually needs to be split into multiple modules and deployed on different FPGAs respectively to form an SSD controller prototype verification environment. However, at the same time, data transmission between different FPGA boards has become crucial. The disadvantage of using FPGA IO interconnection is that the IO resources are limited, and the parallelism is relatively large, which is not conducive to timing convergence. The real-time performance of data transmission cannot be guaranteed, and the bandwidth also cannot reach the expected value, so the true working state of the chip cannot be simulated and the performance cannot be correctly evaluated.

[0004] There is an urgent need for a new verification method. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an FPGA-based SSD controller prototype verification method and device that are simple and flexible in implementation process, have high data transmission efficiency, and are conducive to the deployment of a large SSD controller prototype verification platform.

[0006] To solve the above technical problem, the technical solution adopted by the present invention is: an FPGA-based SSD controller prototype verification method, including:

[0007] S100. Divide the RTL code of the SSD controller into multiple RTL sub-modules;

[0008] S200. Deploy the multiple RTL sub-modules on multiple FPGAs respectively, and the multiple RTL sub-modules communicate through the physical connection between the Serdes ports of the FPGAs;

[0009] S300. Deploy the corresponding preset test parameters and communication port logics according to the test plan;

[0010] S400. Start the system-level test and obtain the test results.

[0011] Further, in step S100, the total resources of each RTL sub-module do not exceed the maximum resources available on the corresponding FPGA.

[0012] Further, in step S100, module division is performed as a whole according to sub_system or functional modules.

[0013] Further, in step S300, it also includes dividing signal groups based on clocks and bus signals and respectively deploying them on the Serdes lanes of each FPGA.

[0014] Further, the test parameters include synchronization scheme test parameters. In the synchronization scheme test parameters, the relationship between the working clock frequency of the FPGA and the grouped parallel data bit width is: where Serdes_Refclk is the reference clock for board-level Serdes transmission, and Data_Width is the grouped parallel data bit width.

[0015] Further, the test parameters include asynchronous scheme test parameters. In the asynchronous scheme test parameters, the relationship between the working clock frequency of the FPGA and the grouped parallel data bit width is: , where Serdes_Linerate is the line rate of the Serdes port, Data_encode_ut i l izat ion is the proportion of the effective data bandwidth calculated by the encoding algorithm, and N is a constant corresponding to the data bit width.

[0016] Further, the value relationship of N is:

[0017] where Data_Width is the grouped parallel data bit width, and Others represents other scenarios where Date_width does not satisfy Data_Width <= 80 and (Data_Width - 16) % 64 = 0.

[0018] The present invention also relates to an FPGA-based SSD controller prototype verification device, including: a division module for dividing the RTL code of the SSD controller to obtain multiple RTL sub-modules;

[0019] a deployment module for respectively deploying multiple RTL sub-modules on multiple FPGAs, where the multiple RTL sub-modules communicate through physical connections between the Serdes ports of the FPGAs, and deploying preset test parameters and communication port logics according to the test scheme;

[0020] an acquisition module for acquiring test results.

[0021] The present invention also relates to an electronic device, including:

[0022] one or more processors;

[0023] A storage device for storing one or more programs;

[0024] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described above.

[0025] The present invention also relates to a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the method described above is implemented.

[0026] The beneficial effects of the present invention are as follows: A prototype verification method for an SSD controller based on FPGA is provided. This method can support the prototype verification of large SSD controller chips, complete data interaction between multiple interconnected FPGAs through Serdes ports. On the premise of improving the reliability and efficiency of data transmission, users can select synchronous / asynchronous data transmission schemes according to the actual verification background, and obtain the performance of the SSD controller chip in the real working scenario through verification performance analysis. Based on the above advantages, this verification method can efficiently and accurately discover potential problems in the chip R & D process before chip tape-out, and improve the chip tape-out quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other objects, features, and advantages of the present disclosure will become more apparent. The following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is an application environment diagram of the prototype verification method for an SSD controller based on FPGA of the present invention;

[0029] Figure 2 It is a flowchart of the prototype verification method for an SSD controller based on FPGA of the present invention;

[0030] Figure 3 It is a block diagram of the prototype verification device for an SSD controller based on FPGA of the present invention;

[0031] Figure 4 It is a block diagram of an electronic device of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] Since traditional single - chip FPGAs cannot meet the deployment requirements of the prototype verification platform for large - scale SSD controllers, it is usually necessary to split the RTL of the SSD controller into multiple modules and deploy them on different FPGAs respectively to form a prototype verification environment for the SSD controller. However, at the same time, data transmission between different FPGA boards has become crucial. The disadvantage of using FPGA IO interconnection is that the IO resources are limited, and the parallelism is relatively large, which is not conducive to timing convergence. The real - time performance of data transmission cannot be guaranteed, and the bandwidth cannot reach the expected value, so the real working state of the chip cannot be simulated, and the performance cannot be correctly evaluated.

[0034] Based on this, the present invention provides an FPGA - based prototype verification method for SSD controllers, which can be applied to Figure 1 the application environment shown in the figure. The verification platform in this application environment includes a system motherboard and multiple FPGAs. The system motherboard is respectively connected to each FPGA, and each FPGA is connected through a high - speed Serdes port. The system motherboard is used to provide the chip main clock, the Serdes transmission reference clock, and the Serdes channel enable signal for each FPGA respectively, so that multiple FPGAs can perform high - speed data interaction through the Serdes port to verify the performance of the SSD controller chip in the real working scenario obtained from performance analysis.

[0035] Please refer to Figure 2 , in one embodiment, an FPGA - based prototype verification method for SSD controllers includes:

[0036] S100. Divide the RTL code of the SSD controller into multiple RTL sub - modules;

[0037] The RTL code of the SSD controller is divided into modules as a whole according to sub - system or functional modules to ensure the functional integrity of each RTL sub - module.

[0038] Among them, the total resources of each RTL sub - module do not exceed the maximum resources available for the corresponding FPGA.

[0039] The LUT, BRAM, and PLL resources of a single sub - RTL module divided should not exceed the maximum resources corresponding to a single FPGA to ensure that the FPGA can fully implement all the functions of an RTL sub - module.

[0040] S200. Deploy multiple RTL sub - modules on multiple FPGAs respectively, and the multiple RTL sub - modules communicate through the physical connection between the Serdes ports of the FPGAs;

[0041] The RTL sub-modules on each FPGA can communicate through the Serdes ports of the FPGA, so as to simulate an SSD controller by using multiple FPGAs.

[0042] S300. Deploy the corresponding preset test parameters and communication port logic according to the test plan;

[0043] Based on the clock, divide the bus signals into signal groups and deploy them on the Serdes lanes of each FPGA respectively.

[0044] S400. Start the system-level test and obtain the test results.

[0045] In this embodiment, the SSD (Solid State Disk) controller chip occupies a large amount of resources and has strong requirements for the real-time performance of data transmission. The traditional FPGA (Field-Programmable Gate Array) prototype verification platform and the multi-FPGA prototype verification platform using parallel IO interconnection are limited by their IO resources. When deploying a high-performance SSD controller chip on the FPGA platform for prototype verification, the data transmission efficiency is low and the real working scenario of the chip cannot be simulated.

[0046] Therefore, the RTL (Register Transfer Level) code of the SSD controller is divided according to modules and split into multiple RTL sub-modules. Each RTL sub-module can implement a part of the functions of the SSD controller. The multiple RTL sub-modules are respectively deployed into multiple FPGAs, and then the multiple FPGAs are connected through Serdes ports. The Serdes ports are used to complete the signal transmission between multiple FPGAs. The original low-speed parallel data between different systems is converted into high-speed serial data through the Serdes ports for transmission. While ensuring the data transmission quality, it also reduces the number of IO used and improves the transmission efficiency, thus simulating the complete functions of the SSD controller. During the test process, according to the test requirements, select the test plan, and the corresponding preset test parameters and communication port logic can be deployed. Under the condition of meeting the prototype verification conditions of a large SSD controller chip, special scenarios such as backpressure in the data interaction of each Sub_system of the original chip are realized, which can be closer to the real working state of the chip, facilitating the verification personnel to understand the actual working performance of the chip, discovering potential bugs of the chip in advance, achieving the purpose of prototype verification of the SSD controller chip, and improving the chip tape-out quality.

[0047] Before the verification starts, multiple parallel data inside the FPGA are grouped. The grouped parallel data are converted from parallel to serial through a parallel-to-serial conversion to obtain serial data, and the serial data are sent to the downstream FPGA using a high-speed Serdes port. The downstream FPGA converts the received serial data from serial to parallel to obtain the required parallel data, thus completing real-time data interaction.

[0048] Among them, the main considerations for parallel data grouping are as follows:

[0049] 1) The data signals to be transmitted belong to the same clock domain;

[0050] 2) The data to be transmitted may or may not belong to a standard transmission protocol. The standard transmission protocols include, but are not limited to, AXI bus transmission protocol, APB bus transmission protocol, etc.

[0051] The advantage of this data grouping is that it can transmit different types of cross-chip signals together, with high design flexibility. The Serdes port adopted has a large transmission rate bandwidth and high efficiency, and can also reflect the real working scenarios such as backpressure and flow control between each group of interfaces inside the chip on the premise of meeting data real-time and reliability.

[0052] In one embodiment, the test parameters include synchronization scheme test parameters. In the synchronization scheme test parameters, the relationship between the working clock frequency of the FPGA and the bit width of the grouped parallel data is: where Serdes_Refclk is the reference clock for board-level Serdes transmission, and Data_Width is the bit width of the grouped parallel data.

[0053] Since there is a fixed frequency ratio relationship between the ASIC clock and the FPGA platform clock, the ASIC clock can be frequency-reduced in a ratio manner for the SSD controller. The ASIC clock frequency is reduced by a certain ratio to complete the deployment of the FPGA verification platform. Based on the consideration of the system clock, the frequency reduction ratio at different clock frequencies is determined. Usually, the system frequency on the FPGA after frequency reduction should be controlled between 1 MHz and 40 MHz, and the frequency reduction ratio is obtained using the multiple relationship between the FPGA system frequency and the ASIC frequency.

[0054] Performing data transmission with the synchronization scheme is beneficial to analyzing the performance of the real chip. The real performance of the chip and the platform verification performance are inversely proportional to the frequency reduction ratio.

[0055] The grouped parallel data can complete data transmission within one clock cycle, with strong data real-time performance, which is beneficial to data transmission delay analysis.

[0056] In the synchronization scheme, the relationship between the working clock frequency of the FPGA after frequency reduction and the bit width of the grouped parallel data is:

[0057] Among them, Serdes_Refclk is the reference clock for board-level Serdes transmission, and Data_Width is the parallel data bit width after grouping.

[0058] In one embodiment, the test parameters include asynchronous scheme test parameters. In the asynchronous scheme test parameters, the relationship between the working clock frequency of the FPGA and the grouped parallel data bit width is: , where Serdes_Linerate is the line rate of the Serdes port, Data_encode_ut i l izat ion is the proportion of the effective data bandwidth calculated by the encoding algorithm, N is a constant corresponding to the data bit width, and the value relationship of N is:

[0059] Among them, Data_Width is the parallel data bit width after grouping, and Others represents other scenarios where Date_width does not satisfy Data_Width <= 80 and (Data_Width - 16)%64 = 0.

[0060] For data transmission using the asynchronous scheme, there is an additional clock cycle overhead, and the relationship with the performance of the real chip is uncertain. However, it has an active flow control function for the data stream, the data transmission is faster, the software test time overhead can be reduced, and the test efficiency can be improved.

[0061] In the asynchronous scheme, the relationship between the working clock frequency of the FPGA after frequency reduction and the grouped parallel data bit width is:

[0062] where Serdes_Linerate is the line rate of the Serdes port, Data_encode_ut i l izat ion is the proportion of the effective data bandwidth calculated by the encoding algorithm, N is a constant corresponding to the data bit width, and the value relationship of N is:

[0063] Among them, Data_Width is the parallel data bit width after grouping, and Others represents other scenarios where Date_width does not satisfy Data_Width <= 80 and (Data_Width - 16)%64 = 0.

[0064] As can be seen from the above description, the beneficial effects of the present invention are as follows: A method for prototype verification of an SSD controller based on FPGA is provided. This method can support the prototype verification of large SSD controller chips, complete data interaction between multiple interconnected FPGAs through Serdes ports. On the premise of improving the reliability and efficiency of data transmission, users can select synchronous / asynchronous data transmission schemes according to the actual verification background, and obtain the performance of the SSD controller chip in the real working scenario through verification performance analysis. Based on the above advantages, this verification method can efficiently and accurately discover potential problems in the chip R & D process before chip tape-out, and improve the chip tape-out quality.

[0065] The following is an apparatus embodiment of the present invention, which can be used to execute the method embodiment of the present invention. For details not disclosed in the apparatus embodiment of the present invention, please refer to the method embodiment of the present invention.

[0066] Please refer to Figure 3 , this embodiment discloses an apparatus for prototype verification of an SSD controller based on FPGA, including: a partitioning module, configured to partition the RTL code of the SSD controller to obtain multiple RTL sub-modules;

[0067] a deployment module, configured to deploy multiple RTL sub-modules on multiple FPGAs respectively, and the multiple RTL sub-modules communicate through physical connections between the Serdes ports of the FPGAs, and deploy preset test parameters and communication port logics according to the test scheme;

[0068] an acquisition module, configured to acquire test results.

[0069] The apparatus provided according to the embodiment of the present invention can support the prototype verification of large SSD controller chips, complete data interaction between multiple interconnected FPGAs through Serdes ports. On the premise of improving the reliability and efficiency of data transmission, users can select synchronous / asynchronous data transmission schemes according to the actual verification background, and obtain the performance of the SSD controller chip in the real working scenario through verification performance analysis. Based on the above advantages, this verification apparatus can efficiently and accurately discover potential problems in the chip R & D process before chip tape-out, and improve the chip tape-out quality.

[0070] The implementation of the method provided by the embodiment of the present invention in the application environment will be described below.

[0071] Please refer to Figure 1, the verification platform of the application environment is a transmission scheme for cross-chip interconnection of two FPGAs. In this transmission scheme, the system motherboard provides the chip main clock, Serdes transmission reference clock, chip reset signal, and Serdes channel enable signal to cross-chip interconnection FPGA1 and FPGA2 respectively. The platform monitors the status of cross-chip FPGA Serdes Link and CRC, etc. using the LocalBus bus. Among them, SSD controller chip module A is deployed in FPGA1, and SSD controller chip module B is deployed in FPGA2. For data transmission, first, the parallel data of SSD controller chip module A is grouped, and then the data is converted at the interface inside FPGA1, that is, the parallel data and the corresponding CRC check field are formed into a standard data frame structure and then passed into the Serdes transmission module of FPGA1. This is implemented using the mature Xilinx Aurora 64 / 66b IP inside this platform. After the parallel data is converted into high-speed serial data by the Serdes transmission module of FPGA1, it is sent to the Serdes receiving module of FPGA2 through a cable. When the data reaches the Serdes receiving module of FPGA2, after the high-speed serial data is converted into parallel data by the Serdes receiving module of FPGA2, the CRC check field is checked according to the parallel data frame information in the interface conversion module. After the check is correct, the valid data is transmitted to SSD controller chip module B, and thus a data transmission is completed.

[0072] Figure 4 is a block diagram of an electronic device shown according to an exemplary embodiment.

[0073] The following refers to Figure 4 to describe the electronic device according to this embodiment of the present invention. Figure 4 The electronic device shown is only an example and should not bring any restrictions to the functions and usage scope of the embodiments of the present invention.

[0074] As Figure 4 shown, the electronic device is presented in the form of a general computing device. The components of the electronic device may include but are not limited to: at least one processing unit, at least one storage unit, a bus connecting different system components (including the storage unit and the processing unit), a display unit, etc.

[0075] Among them, the storage unit stores program code, and the program code can be executed by the processing unit, so that the processing unit executes the steps according to various exemplary embodiments of the present invention described in the above-mentioned part of the FPGA-based SSD controller prototype verification method in this specification. For example, the processing unit can execute the steps as Figure 2 shown.

[0076] The storage unit may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) and / or a cache storage unit, and may further include a read-only storage unit (ROM).

[0077] The storage unit may also include a program / utilities having a set (at least one) of program modules. Such program modules include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment.

[0078] The bus may represent one or more of several types of bus structures, including a storage unit bus or storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of a variety of bus structures.

[0079] The electronic device may also communicate with one or more external devices (such as a keyboard, a pointing device, a Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device, and / or may communicate with any device that enables the electronic device to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication may be through an input / output (I / O) interface. Also, the electronic device may communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter. The network adapter may communicate with other modules of the electronic device through the bus. It should be understood that, although not shown in the figures, other hardware and / or software modules may be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0080] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which may be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiments of the present invention.

[0081] A computer-readable medium, a program product for implementing the above method according to an embodiment of the present invention, which may be a portable compact disc read-only memory (CD-ROM) and includes program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0082] The program product may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but not be limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the readable storage medium (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0083] The computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, in which the readable program code is carried. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the above.

[0084] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., by using an Internet service provider to connect through the Internet).

[0085] The above computer-readable medium stores one or more programs, which, when executed by the device, cause the computer-readable medium to implement the following functions:

[0086] S100. Divide the RTL code of the SSD controller into multiple RTL sub-modules;

[0087] S200. Deploy the multiple RTL sub-modules on multiple FPGAs respectively, and the multiple RTL sub-modules communicate with each other through the physical connection between the Serdes ports of the FPGAs;

[0088] S300. Deploy the preset test parameters and communication port logics according to the test scheme;

[0089] S400. Start the system-level test and obtain the test results.

[0090] Those skilled in the art can understand that the above modules can be distributed in the device according to the description of the embodiments, or can be correspondingly changed and distributed in one or more devices that are uniquely different from this embodiment. The modules and / or units and / or sub-units of the above embodiments can be combined into one module and / or unit and / or sub-unit, or can be further split into multiple modules and / or units and / or sub-units and / or sub-modules.

[0091] From the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described here can be implemented by software, or can be implemented by the way of software combined with necessary hardware. Therefore, the technical solution according to the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on the network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present invention.

[0092] The above specifically shows and describes the exemplary embodiments of the present invention. It should be understood that the present invention is not limited to the detailed structures, settings or implementation methods described here; on the contrary, the present invention is intended to cover various modifications and equivalent settings included in the spirit and scope of the appended claims.

[0093] In addition, the structures, ratios, sizes, etc. shown in this specification and the accompanying drawings are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the technical effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope of implementation of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

Claims

1. A SSD controller prototype verification method based on FPGA, comprising: S100, dividing the RTL code of the SSD controller into modules to obtain multiple RTL sub-modules; S200, deploying multiple RTL sub-modules on multiple FPGAs respectively, and communicating between the multiple RTL sub-modules through physical connections between Serdes ports of the FPGAs; S300, deploying corresponding preset test parameters and communication port logic according to the test plan; S400: Start system-level testing and obtain test results.

2. The method according to claim 1, characterized in that: In step S100 , the total amount of resources of each RTL sub-module does not exceed the maximum resources that the corresponding FPGA can provide.

3. The method according to claim 1, characterized in that: In step S100, the module division is performed as a whole according to sub_system or functional module.

4. The method according to claim 1, characterized in that: In step S300, it also includes dividing the signal groups based on the clock and bus signals and deploying them on the Serdes lanes of each FPGA respectively.

5. The method according to claim 1, characterized in that: The test parameters include synchronization scheme test parameters, in which the relationship between the working clock frequency of the FPGA and the bit width of the grouped parallel data is: Among them, Serdes_Refclk is the reference clock of board-level Serdes transmission, and Data_Width is the bit width of the grouped parallel data.

6. The method according to claim 1, characterized in that: The test parameters include asynchronous scheme test parameters, in which the relationship between the working clock frequency of the FPGA and the bit width of the grouped parallel data is: , where Serdes_Linerate is the line rate of the Serdes port, Data_encode_utilization is the effective data bandwidth ratio calculated by the encoding algorithm, and N is the constant corresponding to the data bit width.

7. The method according to claim 6, characterized in that: The value relationship of N is: Wherein, Data_Width is the bit width of the grouped parallel data, and Others represents other scenarios where Data_width does not satisfy Data_Width<=80 and (Data_Width-16)%64=0.

8. An FPGA-based SSD controller prototype verification device, characterized in that: include: A partitioning module is used to partition the RTL code of the SSD controller into modules to obtain multiple RTL sub-modules; A deployment module is used to deploy multiple RTL sub-modules on multiple FPGAs respectively, and the multiple RTL sub-modules communicate with each other through physical connections between Serdes ports of FPGAs, and to deploy preset test parameters and communication port logic according to the test plan; The acquisition module is used to obtain the test results.

9. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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