Clock signal generation circuit, wired communication transceiver, and electronic device

Abstract

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and particularly to a clock signal generation circuit, a wired communication transceiver, and an electronic device. Background Art

[0002] With the continuous development of digital communication technology, in fields such as data centers, base stations, and heterogeneous chip integration, the application of wired communication transceivers has gradually increased. In practical applications, wired communication transceivers can adopt different digital modulation methods to improve the transmission rate and bandwidth efficiency, such as NRZ, PAM4, PAM6, etc. These high-order modulation methods can transmit more bits under the same bandwidth, significantly improving the data transmission rate, but also posing higher requirements on the performance of high-speed transceivers for wired communication interfaces.

[0003] In view of this, the design of a high-speed, low-phase-noise multi-phase clock generation and distribution circuit has become crucial. Through high-precision clock signals, the sampling rate and signal-to-noise ratio of analog-to-digital converters can be effectively improved, thereby effectively expanding the system scale and transmission rate of wired transceivers, and thus supporting the continuous improvement of the working rate of transceivers applied to wired communication interfaces (such as Ethernet, OTN, etc.). However, the multi-phase clock circuits used in existing systems still have problems such as relatively high phase noise and difficulty in further expanding to high frequencies.

[0004] Therefore, how to generate high-frequency multi-phase clock signals with low phase noise and high phase accuracy has become a technical problem that the industry urgently needs to solve at present. Summary of the Invention

[0005] The present invention provides a clock signal generation circuit, a wired communication transceiver, and an electronic device, which solve the technical problem of how to generate high-frequency multi-phase clock signals with low phase noise and high phase accuracy.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a clock signal generation circuit, including:

[0007] A frequency discriminator and phase discriminator module, configured to output a first DC voltage based on a reference clock signal and a feedback clock signal, where the first DC voltage includes phase difference information and frequency difference information of the reference clock signal and the feedback clock signal;

[0008] A pulse generator, configured to generate a narrow pulse signal based on the first DC voltage and the reference clock signal, and the frequency of the narrow pulse signal is the same as the frequency of the reference clock signal, and the narrow pulse signal is used to perform frequency locking and phase locking on a cross-coupled ring oscillator;

[0009] The cross-coupled ring oscillator includes N second-order ring oscillators and a cross-coupling loop. The cross-coupling loop is coupled to 4 output nodes of the N second-order ring oscillators respectively based on the phase sequence. One output node of the N second-order ring oscillators also receives the narrow pulse signal. The frequency control terminal of each second-order ring oscillator receives the first DC voltage, where N is an integer greater than or equal to 1;

[0010] Wherein, each second-order ring oscillator is used to output 4 high-frequency clock signals with equal phase intervals. The cross-coupling loop is used to perform synchronous coupling processing and phase sequence adjustment processing on each second-order ring oscillator;

[0011] The frequency divider is used to divide the frequency of any one of the high-frequency clock signals and output a feedback clock signal.

[0012] Optionally, the cross-coupling loop includes N coupling units connected end to end;

[0013] The output ends of the N coupling units are coupled to the output nodes of the second-order ring oscillators in sequence according to the phase sequence. The coupling unit is used for voltage-current conversion and signal amplification;

[0014] Each coupling unit is used to output a corresponding coupling current to the corresponding output node, so that the cross-coupled ring oscillator outputs N oscillating clock signals with equal phase intervals. The N oscillating clock signals with equal phase intervals are evenly divided into 4 groups of oscillating clock signals according to the phase sequence, and the oscillating clock signals in each group of oscillating clock signals come from different second-order ring oscillators.

[0015] Optionally, the coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

[0016] Optionally, the second-order ring oscillator includes 2 identical delay units; where:

[0017] The first output end of the first delay unit is coupled to the first input end of the second delay unit, and the second output end of the first delay unit is coupled to the second input end of the second delay unit;

[0018] The first output end of the second delay unit is coupled to the second input end of the first delay unit, and the second output end of the second delay unit is coupled to the first input end of the first delay unit;

[0019] Wherein, the first output end and the second output end of the delay unit also receive corresponding coupling currents.

[0020] Optionally, the delay unit includes:

[0021] A positive main inverter, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal;

[0022] An inverting main inverter, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal;

[0023] A first cross-coupled inverter, coupled between the first output terminal and the second output terminal;

[0024] Wherein, the first output terminal and the second output terminal of the delay unit also respectively receive 2 coupling currents corresponding to the delay unit.

[0025] Optionally, the delay unit further includes a power supply voltage adjustment module and a current adjustment module. Both the power supply voltage adjustment module and the current adjustment module are coupled between the first node and the power supply voltage. The control terminal of the power supply voltage adjustment module receives a power supply voltage adjustment signal, and the control terminal of the current adjustment module receives the first DC voltage;

[0026] The power supply voltage adjustment module is configured to control the power supply voltages of the positive main inverter and the inverting main inverter based on the power supply voltage adjustment signal, and adjust the delay magnitudes of the positive main inverter and the inverting main inverter to adjust the free oscillation frequency of the delay unit;

[0027] The current adjustment module is configured to control the magnitude of the current flowing through the delay unit based on the first DC voltage to adjust the free oscillation frequency of the delay unit.

[0028] Optionally, the frequency discriminator and phase detector module includes: a frequency discriminator and phase detector, a first low-pass filter, a second low-pass filter, and a subtractor;

[0029] The first input terminal of the frequency discriminator and phase detector receives the reference clock signal, its second input terminal receives the feedback clock signal, its first output terminal is coupled to the positive input terminal of the subtractor through the first low-pass filter, its first output terminal is coupled to the negative input terminal of the subtractor through the second low-pass filter, and the output terminal of the subtractor outputs the first DC voltage.

[0030] Optionally, the frequency discriminator and phase detector includes a first D flip-flop, a second D flip-flop, and a first AND gate unit;

[0031] The clock input terminal of the first D flip-flop receives the reference clock signal, its data input terminal receives the power supply voltage, its output terminal is coupled to the first input terminal of the first AND gate unit, its reset terminal is coupled to the output terminal of the first AND gate unit, and the output terminal of the first D flip-flop is also coupled to the positive-phase input terminal of the subtractor through the first low-pass filter;

[0032] The clock input terminal of the second D flip-flop receives the feedback clock signal, its data input terminal is grounded, its output terminal is coupled to the second input terminal of the first AND gate unit, its reset terminal is coupled to the output terminal of the first AND gate unit, and the output terminal of the second D flip-flop is also coupled to the inverting input terminal of the subtractor through the second low-pass filter.

[0033] Optionally, the pulse generator includes M buffer units and a second AND gate unit. Each buffer unit includes a buffer and a PMOS transistor, where M is an integer greater than or equal to 2;

[0034] The bias voltage terminal of each buffer receives the power supply voltage through the corresponding PMOS transistor, and the gates of the PMOS transistors all receive the first DC voltage;

[0035] The input terminal of the first buffer receives the reference clock signal, the output terminal of the i-th buffer and the output terminal of the M-th buffer are respectively coupled to the first input terminal and the second input terminal of the second AND gate unit, and the output terminal of the second AND gate unit outputs the narrow pulse signal, where i is an integer and 1 ≤ i < M.

[0036] Optionally, the frequency divider is coupled to any output node. The frequency divider includes a third D flip-flop, a fourth D flip-flop, an OR gate unit, a third AND gate unit, and a second buffer;

[0037] The clock input terminal of the third D flip-flop receives the high-frequency clock signal, its data input terminal is respectively coupled to the first input terminal of the third AND gate unit and the input terminal of the second buffer, the output terminal of the third D flip-flop is coupled to the first input terminal of the OR gate unit, the second input terminal of the OR gate unit receives an external control signal, the output terminal of the OR gate unit is coupled to the second input terminal of the third AND gate unit, the output terminal of the third AND gate unit is coupled to the data input terminal of the fourth D flip-flop, the clock input terminal of the fourth D flip-flop receives the high-frequency clock signal, its output terminal is coupled to the input terminal of the second buffer, and the output terminal of the second buffer outputs the feedback clock signal.

[0038] Optionally, the clock signal generating circuit further includes a crystal oscillator;

[0039] The crystal oscillator is respectively coupled to the frequency discriminator and phase detector module and the pulse generator, and the crystal oscillator is used to output the reference clock signal.

[0040] Optionally, the clock signal generation circuit further includes a phase interpolator;

[0041] The input end of the phase interpolator receives 2N pairs of different differential clock signal pairs, and its control end receives an interpolation control signal. Each pair of differential clock signal pairs includes two high-frequency clock signals with a phase difference of 180°. The interpolation control signal includes target phase information;

[0042] The phase interpolator is configured to: based on the interpolation control signal, select two pairs of differential clock signal pairs for signal weighting processing, and output a first differential phase signal and a second differential phase signal, and the phase of the first differential phase signal and / or the phase of the second differential phase signal are the same as the target phase information.

[0043] Optionally, the phase interpolator includes: a first voltage-current conversion unit, a second voltage-current conversion unit, 2N differential phase interpolation units, and 2N weight adjustment units. The interpolation control signal includes 2N interpolation control sub-signals;

[0044] The first end of each differential phase interpolation unit is coupled to the first voltage-current conversion unit through a second node, the second end of each differential phase interpolation unit is coupled to the second voltage-current conversion unit through a third node, the third end of each differential phase interpolation unit is grounded through a corresponding weight adjustment unit, and the control end of each weight adjustment unit receives a corresponding interpolation control sub-signal. The first voltage-current conversion unit and the second voltage-current conversion unit are both coupled to the power supply voltage. The second node therein is used to output the first differential phase signal, and the third node is used to output the second differential phase signal;

[0045] Wherein, the input end of each differential phase interpolation unit receives a corresponding differential clock signal pair, and the differential clock signal pairs received by the input ends of each differential phase interpolation unit are different.

[0046] Optionally, the differential phase interpolation unit includes a first NMOS transistor and a second NMOS transistor;

[0047] The drain of the first NMOS transistor is coupled to the second node, the drain of the second NMOS transistor is coupled to the third node, and the sources of the first NMOS transistor and the second NMOS transistor are both grounded through corresponding weight adjustment units; the gates of the first NMOS transistor and the second NMOS transistor are respectively used to receive two high-frequency clock signals in a corresponding differential clock signal pair.

[0048] According to a second aspect of the present invention, an embodiment of the present invention provides a wired communication transceiver, including a clock signal generation circuit as described in any one of the first aspects of the present invention.

[0049] According to a third aspect of the present invention, an embodiment of the present invention provides an electronic device, including a clock signal generation circuit as described in any one of the first aspects of the present invention.

[0050] Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

[0051] In the clock signal generation circuit, wired communication transceiver, and electronic device of the technical solution of the present invention, the circuit outputs a first DC voltage including phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a frequency discriminator and phase detector module. The pulse generator generates a narrow pulse signal based on the DC voltage and the reference clock signal. The oscillation frequencies of the secondary ring oscillators in the cross-coupled ring oscillator are controlled by the first DC voltage. The cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on the secondary ring oscillators. One output node in the cross-coupled ring oscillator receives the narrow pulse signal, and frequency and phase locking are completed through injection locking. The frequency divider is used to perform frequency division processing on any high-frequency clock signal and output a feedback clock signal. Thus, the present invention can generate a high-frequency multi-phase clock signal with low phase noise and high phase accuracy using a low-frequency reference clock signal.

[0052] Furthermore, the clock signal generation circuit of the technical solution of the present invention further includes a phase interpolator. Since the phase interpolator can utilize 2N pairs of different differential clock signal pairs, it can not only output a first differential phase signal and a second differential phase signal with higher frequencies, but also has good linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0054] Figure 1 is a schematic structural diagram of a clock signal generation circuit provided by an embodiment of the present invention;

[0055] Figure 2 is a schematic structural diagram of a frequency discriminator and phase detector module provided by an embodiment of the present invention;

[0056] Figure 3 is a schematic structural diagram of a pulse generator provided by an embodiment of the present invention;

[0057] Figure 4 is Figure 3 the working timing diagram;

[0058] Figure 5 is the structural schematic diagram of a cross-coupled ring oscillator provided by an embodiment of the present invention;

[0059] Figure 6 is the structural schematic diagram of a delay unit provided by an embodiment of the present invention;

[0060] Figure 7 is the structural schematic diagram of a frequency divider provided by an embodiment of the present invention;

[0061] Figure 8 is the structural schematic diagram of a clock signal generation circuit provided by another embodiment of the present invention;

[0062] Figure 9 is the structural schematic diagram of a phase interpolator provided by an embodiment of the present invention;

[0063] Figure 10 is Figure 9 the working effect diagram;

[0064] Figure 11 is Figure 9 the linearity effect diagram;

[0065] Figure 12 The structural schematic diagram of a controllable current source provided by an embodiment of the present invention. Specific embodiments

[0066] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0067] In the specification, claims and the above-mentioned drawings of the present invention, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0068] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be described in some embodiments.

[0069] As described in the background art, it is difficult for the prior art to generate high-frequency multi-phase clock signals with low phase noise and high phase accuracy. The following will be described in detail.

[0070] Specifically, the domestic and foreign industrial and academic communities are actively exploring various multi-phase clock generation and distribution schemes to meet the requirements of clock accuracy and frequency expansion for high-speed data transmission.

[0071] For example, in 2019, NVIDIA Corporation proposed a coupled ring oscillator scheme based on an embedded phase interpolator, which can cover the 13-25 GHz frequency band and realizes the efficient generation of multi-phase clocks to a certain extent.

[0072] In 2022, Intel Corporation's clock generation scheme based on a traditional phase-locked loop (PLL), frequency divider and phase interpolator successfully achieved a data transmission rate of 224 Gb / s and was applied to high-speed wired transceivers for Serdes interfaces.

[0073] It can be seen that the current multi-phase low-noise clock generation technology generally adopts the following two schemes:

[0074] One way is the scheme of a polyphase filter, which uses an array of filters to distribute the input clock signal into multiple phase outputs.

[0075] However, in order to achieve high-precision multi-phase clock generation, the filter usually needs to adopt a high-order design. When processing high-frequency signals, more filters need to be added to the circuit. These filters not only need to have strong bandwidth and suppression characteristics, but each filter also needs to be designed independently.

[0076] This design not only increases the complexity of the circuit, but also multiple parallel filters will occupy a large amount of chip area, limiting the system integration and cost-effectiveness. Moreover, the performance of the polyphase filter is easily affected by temperature and process variations, making the stability and accuracy of the system unstable.

[0077] Another approach is through a scheme that combines a phase-locked loop (PLL), a frequency divider, and a phase interpolator. In this scheme, the PLL is used to compare the phase of the output signal with the reference signal to adjust the output frequency of the voltage-controlled oscillator (VCO), so that the output signal is synchronized with the reference signal.

[0078] The frequency divider is used to reduce the clock signal output by the PLL to the required frequency.

[0079] The phase interpolator is used to combine multiple input clock signals to generate a higher-precision phase output. This method enables the clock resolution to reach a finer granularity and is suitable for high-precision clock distribution and data sampling.

[0080] However, in this scheme, due to the fact that the phase noise, parasitic effects, and nonlinear problems of the VCO become more significant at high frequencies, the design difficulty of the wideband voltage-controlled oscillator (VCO) and PLL increases significantly as the frequency rises.

[0081] Moreover, the linearity of the phase interpolator is greatly affected by the number of input clock phases. Therefore, the scheme based on the PLL, frequency divider, and phase interpolator is difficult to extend to higher frequencies.

[0082] To solve the above problems, an embodiment of the present invention provides a clock signal generation circuit. The circuit outputs a first DC voltage including the phase difference information and frequency difference information of the reference clock signal and the feedback clock signal through a frequency discriminator and phase discriminator module. The pulse generator generates a narrow pulse signal based on this DC voltage and the reference clock signal. The oscillation frequencies of the secondary ring oscillators in the cross-coupled ring oscillator are controlled by the first DC voltage. The cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross-coupled ring oscillator receives the narrow pulse signal and completes frequency and phase locking through injection locking. The frequency divider is used to perform frequency division processing on any high-frequency clock signal and output a feedback clock signal. Thus, the present invention can generate a high-frequency multi-phase clock signal with low phase noise and high phase accuracy using a low-frequency reference clock signal.

[0083] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the accompanying drawings.

[0084] Figure 1This is the clock signal generation circuit according to an embodiment of the present invention, including:

[0085] A frequency discriminator and phase discriminator module 1, configured to output a first DC voltage V REF based on a reference clock signal CLK DIV and a feedback clock signal CLK ctrl , where the first DC voltage V ctrl includes phase difference information and frequency difference information of the reference clock signal CLK REF and the feedback clock signal CLK; DIV

[0086] A pulse generator 2, configured to generate a narrow pulse signal CLK ctrl based on the first DC voltage V REF and the reference clock signal CLK pulse , and the frequency of the narrow pulse signal CLK pulse is the same as the frequency of the reference clock signal CLK REF , and the narrow pulse signal CLK pulse is used to perform frequency locking and phase locking on the cross-coupled ring oscillator;

[0087] The cross-coupled ring oscillator 3 includes N second-order ring oscillators 32 and a cross-coupling loop 31. The cross-coupling loop 31 is coupled to 4 output nodes of the N second-order ring oscillators 32 based on the phase sequence. One output node of the N second-order ring oscillators 32 also receives the narrow pulse signal CLK pulse , and the frequency control terminal of each second-order ring oscillator 32 receives the first DC voltage V ctrl , where N is an integer greater than or equal to 1;

[0088] Among them, each second-order ring oscillator 32 is configured to output 4 high-frequency clock signals with equal phase intervals, and the cross-coupling loop 31 is used to perform synchronous coupling processing and phase sequence adjustment processing on each second-order ring oscillator 32;

[0089] Among them, each second-order ring oscillator 32 is configured to output 4 high-frequency clock signals with equal phase intervals, and the cross-coupling loop 31 is used to perform synchronous coupling processing and phase sequence adjustment processing on each second-order ring oscillator 32.

[0090] A frequency divider 4, configured to perform frequency division processing on any one of the high-frequency clock signals and output a feedback clock signal CLK DIV .

[0091] Among them, the above output node can also be understood as the input node of the corresponding second-order ring oscillator 32, and the present invention does not limit this.

[0092] It can be seen that the frequency discriminator and phase discriminator module 1 and the frequency divider 4 of the present invention constitute a frequency-locked loop. As an example, this frequency-locked loop can be an integer frequency-locked loop. Of course, the present invention does not limit this, and it can also be a fractional frequency-locked and phase-locked loop. Those skilled in the art can select appropriate output frequencies and reference frequencies according to needs.

[0093] Since the cross-coupled ring oscillator 3 decouples the output frequency and the number of output phases at the design level, and at the same time expands the operating frequency band and the number of phases of the output clock, the present invention can utilize the low-frequency reference clock signal CLK REF to generate a high-frequency multi-phase clock signal with low phase noise and high phase accuracy.

[0094] In a preferred embodiment, the clock signal generating circuit further includes a crystal oscillator ( Figure 1 not shown in the figure);

[0095] The crystal oscillator is respectively coupled to the frequency discriminator and phase discriminator module 1 and the pulse generator 2, and the crystal oscillator is used to output the reference clock signal CLK REF .

[0096] It can be seen that the crystal oscillator can provide a low-frequency and high-precision reference clock signal CLK for the circuit of the present invention REF .

[0097] Now, the working principle of the Figure 1 shown circuit will be described.

[0098] Figure 1 In the example of , the oscillating clock signal from the cross-coupled ring oscillator 3 is input into the frequency divider 4. This oscillating clock signal is a high-frequency signal generated by the free oscillation of the ring oscillator, and its frequency is much greater than the frequency of the reference clock signal CLK REF . In order to be able to utilize the reference clock signal CLK REF to lock the phase and frequency of the oscillating clock signal, it is necessary to first divide the frequency of the oscillating clock signal. The frequency of the feedback clock signal CLK DIV after frequency division may still be greater than the frequency of the reference clock signal CLK REF , but the phase difference between the two can be more easily captured by the frequency discriminator and phase discriminator module 1, thereby generating a first DC voltage V ctrl that controls the frequency of the cross-coupled ring oscillator 3, and finally enabling the cross-coupled ring oscillator 3 to output the high-frequency clock signal.

[0099] When the feedback clock signal CLK DIV from the frequency divider 4 has too fast a frequency, resulting in the feedback clock signal CLK DIV and the reference clock signal CLK REFWhen the phase difference becomes larger, the first DC voltage V ctrl will decrease to reduce the oscillation frequency of the cross-coupled oscillator (equivalent to a negative feedback process), thereby achieving frequency and phase locking. When the frequency of the feedback clock signal CLK DIV is too slow, the process is reversed.

[0100] It should be understood that in the embodiments of the present invention, the result of frequency locking is not that the frequency of the high-frequency clock signal or the frequency of the feedback clock signal CLK DIV is locked to be equal to the frequency of the reference clock signal CLK REF Rather, by making the feedback clock signal CLK DIV and the reference clock signal CLK REF There is a constant phase difference between the signals to ensure that the frequency of the high-frequency clock signal remains locked and the phase difference does not change with time.

[0101] It can be seen that the output frequency of the cross-coupled ring oscillator 3 in the present invention is jointly determined by its own free oscillation frequency, the frequency locking loop, and the pulse generator 2.

[0102] Now, the clock signal generation circuit of the present invention will be further elaborated.

[0103] In one implementation, please refer to Figure 2 , the frequency discriminator and phase discriminator module 1 includes: a frequency discriminator and phase discriminator 11, a first low-pass filter 12, a second low-pass filter 13, and a subtractor 14;

[0104] The first input terminal of the frequency discriminator and phase discriminator 11 receives the reference clock signal CLK REF , its second input terminal receives the feedback clock signal CLK DIV , its first output terminal is coupled to the positive-phase input terminal of the subtractor 14 through the first low-pass filter 12, its first output terminal is coupled to the inverting input terminal of the subtractor 14 through the second low-pass filter 13, and the output terminal of the subtractor 14 outputs the first DC voltage V ctrl .

[0105] In a specific implementation, please refer to Figure 2 , the frequency discriminator and phase discriminator 11 includes a first D flip-flop 111, a second D flip-flop 112, and a first AND gate unit 113;

[0106] The clock input terminal of the first D flip-flop 111 receives the reference clock signal CLK REF, its data input terminal receives the power supply voltage, its output terminal is coupled to the first input terminal of the first AND gate unit 113, its reset terminal is coupled to the output terminal of the first AND gate unit 113, and the output terminal of the first D flip-flop 111 is also coupled to the positive-phase input terminal of the subtractor 14 through the first low-pass filter 12;

[0107] The clock input terminal of the second D flip-flop 112 receives the feedback clock signal CLK DIV , its data input terminal is grounded, its output terminal is coupled to the second input terminal of the first AND gate unit 113, its reset terminal is coupled to the output terminal of the first AND gate unit 113, and the output terminal of the second D flip-flop 112 is also coupled to the inverting input terminal of the subtractor 14 through the second low-pass filter 13.

[0108] It can be seen that the frequency discriminator and phase detector 11 can obtain the phase difference and frequency difference between the two signals by comparing the edges of the reference clock signal CLK REF and the feedback clock signal CLK DIV and convert the phase difference and frequency difference into a differential voltage pulse signal. After the differential voltage pulse signal is low-pass filtered by the first low-pass filter 12 and the second low-pass filter 13, the high-frequency components of the differential voltage pulse signal are filtered out, and the DC voltage component is retained. After these two DC voltage components are subjected to a DC differential subtraction operation by the subtractor 14, a first DC voltage V containing the phase difference and frequency difference information is obtained ctrl , the first DC voltage V ctrl is used to control the oscillation frequency of the cross-coupled oscillator and the pulse frequency of the pulse generator 2.

[0109] In one embodiment, please refer to Figure 3 , the pulse generator 2 includes M buffer units and a second AND gate unit 22. Each buffer unit includes a buffer 211 and a PMOS transistor 212, where M is an integer greater than or equal to 2;

[0110] The bias voltage terminal of each buffer 211 receives the power supply voltage through the corresponding PMOS transistor 212, and the gates of the PMOS transistors 212 all receive the first DC voltage V ctrl ;

[0111] The input terminal of the first buffer 211 receives the reference clock signal CLK REF , the output terminal of the i-th buffer 211 and the output terminal of the M-th buffer 211 are respectively coupled to the first input terminal and the second input terminal of the second AND gate unit 22, and the output terminal of the second AND gate unit 22 outputs the narrow pulse signal CLK pulse, where i is an integer and 1 ≤ i < M.

[0112] In actual implementation, the number of buffers 211 can be set according to the frequency requirements. It can be seen that in Figure 3 the example of REF the input reference clock signal CLK

[0113] successively passes through M buffers 211. The PMOS transistors 212 corresponding to each buffer 211 are used to control the bias voltage of the buffer 211 to change the pulse generation speed. The output of the last-stage buffer 211 and the output of a certain buffer 211 between stages pass through an AND gate circuit to generate the final pulse. Figure 3 Among them, in Figure 4 the example of

[0114] V 1 , which can be understood as the output voltage waveform of the first-stage buffer 211;

[0115] V M , which can be understood as the output voltage waveform of the Mth-stage buffer 211;

[0116] CLK pulse , which can be understood as the waveform of the narrow pulse signal CLK pulse .

[0117] It can be seen that the present invention can output the narrow pulse signal CLK REF with the same frequency as the reference clock signal CLK pulse .

[0118] In one implementation manner, please refer to Figure 5 , the cross-coupled loop 31 includes N coupling units 311 connected end to end;

[0119] The output ends of the N coupling units 311 are sequentially coupled to the output nodes in the secondary ring oscillator 32 according to the phase order. The coupling unit 311 is used for voltage-current conversion and signal amplification;

[0120] Each coupling unit 311 is used to output a corresponding coupling current to the corresponding output node, so that the cross-coupled ring oscillator 3 outputs N oscillation clock signals with equal phase intervals. The N oscillation clock signals with equal phase intervals are evenly divided into 4 oscillation clock signal groups according to the phase order, and the oscillation clock signals in each oscillation clock signal group come from different secondary ring oscillators 32.

[0121] As an example, the coupling unit 311 may further include a transistor, a buffer, a transconductance unit (such as Figure 1 shown) or a single-stage amplifier.

[0122] In a specific embodiment, the above-mentioned transistor may be an NMOS transistor. When the coupling unit 311 is a transistor, the gate of the NMOS transistor can be understood as the signal input terminal, its source is grounded, and its drain is used as the signal output terminal.

[0123] It should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate components as the coupling unit 311 according to needs.

[0124] Please continue to refer to Figure 5 , in Figure 5 example, the second-order ring oscillator 32 includes 2 identical delay units 321; where:

[0125] The first output terminal of the first delay unit 321 is coupled to the first input terminal of the second delay unit 321, and the second output terminal of the first delay unit 321 is coupled to the second input terminal of the second delay unit 321;

[0126] The first output terminal of the second delay unit 321 is coupled to the second input terminal of the first delay unit 321, and the second output terminal of the second delay unit 321 is coupled to the first input terminal of the first delay unit 321;

[0127] Wherein, the first output terminal and the second output terminal of the delay unit 321 also receive corresponding coupling currents.

[0128] It can be seen that due to the small number of stages of the second-order ring oscillator 32, it can achieve higher-frequency signal output.

[0129] In the embodiment of the present invention, the first input terminal is used to output a positive-phase voltage signal Vin+, and the second input terminal is used to output an inverted-phase voltage signal Vin-.

[0130] In Figure 5 example, for each second-order ring oscillator 32, the first letter of its subscript represents the number of the ring oscillator (such as represents the first ring oscillator, represents the (N-1)th ring oscillator); and the second number represents the phase sequence in the ring oscillator. For example represents 0°, 90°, 180° and 270°, and so on.

[0131] Please refer to Figure 6 , the delay unit 321 includes:

[0132] A positive main inverter 3211, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage VCC through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal;

[0133] A negative main inverter 3212, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage VCC through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal;

[0134] A first cross-coupled inverter 3213, coupled between the first output terminal and the second output terminal;

[0135] Wherein, the first output terminal and the second output terminal of the delay unit 321 also respectively receive 2 coupling currents corresponding to the delay unit 321 ( Figure 6 not shown in the figure).

[0136] The first cross-coupled inverter 3213 therein is used to connect the positive main inverter 3211 and the negative main inverter 3212 to ensure that the second-order ring oscillator 32 is not in a locked state.

[0137] In a preferred embodiment, please continue to refer to Figure 6 , the delay unit 321 further includes a power supply voltage adjustment module 3214 and a current adjustment module 3215. The power supply voltage adjustment module 3214 and the current adjustment module 3215 are both coupled between the first node and the power supply voltage VCC. The control terminal of the power supply voltage adjustment module 3214 receives a power supply voltage adjustment signal, and the control terminal of the current adjustment module 3215 receives the first DC voltage V ctrl ;

[0138] The power supply voltage adjustment module 3214 is used to control the power supply voltages of the positive main inverter 3211 and the negative main inverter 3212 based on the power supply voltage adjustment signal, adjust the delay magnitudes of the positive main inverter 3211 and the negative main inverter 3212, so as to adjust the free oscillation frequency of the delay unit 321;

[0139] The current adjustment module 3215 is used to control the magnitude of the current flowing through the delay unit 321 based on the first DC voltage V ctrl , so as to adjust the free oscillation frequency of the delay unit 321.

[0140] As an example, the power supply voltage adjustment module 3214 may include a variable resistor.

[0141] The current regulation module 3215 may include a PMOS transistor, which is configured to convert the low-frequency DC voltage generated by the frequency-locked loop into a current, and is synchronized with the power supply voltage regulation module 3214 to adjust the current of the delay unit 321 so as to adjust the oscillation frequency.

[0142] Of course, the present invention is not limited thereto, and those skilled in the art can select appropriate components or circuits as the power supply voltage regulation module 3214 or the current regulation module 3215 according to needs.

[0143] In one embodiment, please refer to Figure 7 , the frequency divider 4 is coupled to any one of the output nodes, and the frequency divider 4 includes a third D flip-flop 41, a fourth D flip-flop 42, an OR gate unit 43, a third AND gate unit 44, and a second buffer 45;

[0144] The clock input terminal of the third D flip-flop 41 receives the high-frequency clock signal CLK RO , its data input terminals are respectively coupled to the first input terminal of the third AND gate unit 44 and the input terminal of the second buffer 45, the output terminal of the third D flip-flop 41 is coupled to the first input terminal of the OR gate unit 43, the second input terminal of the OR gate unit 43 receives an external control signal Ctrl, the output terminal of the OR gate unit 43 is coupled to the second input terminal of the third AND gate unit 44, the output terminal of the third AND gate unit 44 is coupled to the data input terminal of the fourth D flip-flop 42, the clock input terminal of the fourth D flip-flop 42 receives the high-frequency clock signal, its output terminal is coupled to the input terminal of the second buffer 45, and the output terminal of the second buffer 45 outputs the feedback clock signal CLK DIV .

[0145] It should be understood that the external control signal Ctrl is a control signal for externally controlling the working state of the frequency divider 4. This external control signal Ctrl is a prior art and will not be elaborated herein.

[0146] Now, taking the cross-coupled ring oscillator 3 including two second-order ring oscillators 32 as an example, the working principle of the circuit provided by the present invention will be described.

[0147] In the initial state, the two ring oscillators oscillate freely, and their initial phase states are random, but the four phase states inside each ring oscillator are spaced at intervals of 90°.

[0148] In this case, the cross-coupled loop 31 can be a loop formed by connecting 8 buffers 211 end to end. According to the Barkhausen criterion, this loop presents a positive feedback state, that is, if not connected to other circuits, any small voltage fluctuation will cause the voltage at each node of this loop to quickly change to 0 or Vdd, and finally lock in the state of 0 or 1, and there will be no oscillation phenomenon. It can be seen that the cross-coupled loop 31 is a strong feedback loop.

[0149] Since the cross-coupled loop 31 is connected to each output node of the two secondary ring oscillators 32 in phase sequence, this positive feedback loop can achieve phase coupling between the two secondary ring oscillators 32. This enables the vector synthesis of two currents at each output node of each ring oscillator: namely, the current of the secondary ring oscillator 32 itself and the corresponding coupled current provided by the cross-coupled loop 31. As time goes by, the current change at each node gradually stabilizes, forming a vector synthesis current with the same magnitude and a phase difference of 45°. Finally, the cross-coupled ring oscillator 3 enters a stable oscillation state, and the two secondary ring oscillators 32 achieve frequency and phase synchronization, and the phase difference between the 8 equally spaced oscillation clock signals output by the two secondary ring oscillators 32 is 45°. It can be seen that the two secondary ring oscillators 32 achieve spontaneous phase alignment and calibration through cross-coupling.

[0150] Moreover, the cross-coupled loop 31 evenly divides the 8 equally spaced oscillation clock signals output by the two secondary ring oscillators 32 into 4 oscillation clock signal groups according to the phase sequence, and the oscillation clock signals in each oscillation clock signal group come from different secondary ring oscillators 32.

[0151] This implementation scheme of the cross-coupled ring oscillator 3 can decouple the output phase number and the highest oscillation frequency of the multi-phase clock generator, and can achieve multi-phase clock output without frequency division. It can be seen that the present invention avoids using an LC voltage-controlled oscillator and greatly reduces the chip area consumption.

[0152] However, the cross-coupled ring oscillator 3 can only ensure a high output oscillation frequency and multiple output phases. To reduce the phase noise, the present invention needs to lock the frequency and phase of the cross-coupled ring oscillator 3 through the combination of a frequency-locked loop and injection locking to reduce the output phase noise of the ring oscillator.

[0153] This is because during the oscillation of the oscillator, phase noise (or clock jitter) will be generated in each oscillation period. Without external interference, the phase noise of the oscillator will accumulate over time, resulting in a gradual increase in the noise level. To suppress this noise, the injection locking technique injects a reference clock signal CLK with low phase noise REFInject into the internal node of the oscillator, thereby periodically refreshing the phase noise of the node. This refresh period is determined by the frequency of the injection signal. The higher the frequency of the injection signal, the faster the refresh speed, and the lower the phase noise of the oscillator.

[0154] Also, since in general, the reference clock signal CLK with extremely low phase noise REF can only be physically generated by a crystal oscillator, and the characteristics of the crystal oscillator itself limit it to generating only a very slow and low-noise reference signal. Therefore, while injecting the reference signal to refresh the phase noise of the node, a negative feedback loop (i.e., the frequency-locked loop of the present invention) is required to align the output phase of the oscillator and the phase of the reference signal.

[0155] In summary, the clock signal generation circuit provided by the present invention outputs a first DC voltage including the phase difference information and frequency difference information of the reference clock signal and the feedback clock signal through the frequency discriminator and phase discriminator module. The pulse generator generates a narrow pulse signal based on this DC voltage and the reference clock signal. The oscillation frequencies of the secondary ring oscillators in the cross-coupled ring oscillator are controlled by the first DC voltage. The cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross-coupled ring oscillator receives this narrow pulse signal, and frequency and phase locking are completed through injection locking. The frequency divider is used to perform frequency division processing on any high-frequency clock signal and output a feedback clock signal. Thus, the present invention can generate a high-frequency multi-phase clock signal with low phase noise and high phase accuracy using a low-frequency reference clock signal.

[0156] Considering that interpolation can be performed using the high-frequency multi-phase clock signal with low phase noise and high phase accuracy generated by the present invention to generate a high-frequency clock signal with the required phase, low phase noise, and high phase accuracy. Furthermore, in a preferred embodiment, please refer to Figure 8 ., the clock signal generation circuit further includes a phase interpolator 5;

[0157] The input end of the phase interpolator 5 receives 2N pairs of different differential clock signal pairs, and its control end receives an interpolation control signal. Each pair of differential clock signal pairs includes two of the high-frequency clock signals with a phase difference of 180°. The interpolation control signal includes target phase information;

[0158] The phase interpolator 5 is configured to: based on the interpolation control signal, select two pairs of differential clock signal pairs for signal weighting processing, and output a first differential phase signal and a second differential phase signal, and the phase of the first differential phase signal and / or the phase of the second differential phase signal are the same as the target phase information.

[0159] In practical applications, since the linearity of the phase interpolator 5 increases as the number of input clock phases increases, it can be seen that since the present invention can generate a multi-phase high-frequency clock signal with 4N phases, low phase noise, and high phase accuracy, the linearity of the phase interpolator 5 of the present invention is relatively high, and the phase noise and phase accuracy of the output first differential phase signal and second differential phase signal are also relatively good, and it can support the output of a relatively high frequency.

[0160] In a specific embodiment, please refer to Figure 9 , the phase interpolator 5 includes: a first voltage-current conversion unit 51, a second voltage-current conversion unit 52, 2N differential phase interpolation units, and 2N weight adjustment units 54, and the interpolation control signal includes 2N interpolation control sub-signals;

[0161] The first end of each differential phase interpolation unit is coupled to the first voltage-current conversion unit 51 through a second node, the second end of each differential phase interpolation unit is coupled to the second voltage-current conversion unit 52 through a third node, the third end of each differential phase interpolation unit is grounded through a corresponding weight adjustment unit 54, the control end of each weight adjustment unit 54 receives a corresponding interpolation control sub-signal, and both the first voltage-current conversion unit 51 and the second voltage-current conversion unit 52 are coupled to the power supply voltage VCC, and the second node therein is used to output the first differential phase signal, and the third node is used to output the second differential phase signal;

[0162] Wherein, the input end of each differential phase interpolation unit receives a corresponding differential clock signal pair, and the differential clock signal pairs received by the input ends of each differential phase interpolation unit are different.

[0163] In Figure 9 's example, the differential phase interpolation unit includes a first NMOS transistor and a second NMOS transistor.

[0164] The drain of the first NMOS transistor is coupled to the second node, the drain of the second NMOS transistor is coupled to the third node, the sources of the first NMOS transistor and the second NMOS transistor are both grounded through corresponding weight adjustment units 54; the gates of the first NMOS transistor and the second NMOS transistor are respectively used to receive two of the high-frequency clock signals in the corresponding differential clock signal pair.

[0165] It can be seen that the phase interpolator 5 receives 4N high-frequency clock signals with different phases, and each pair of differential clock signal pairs is input into a differential phase interpolation unit, and the weight adjustment unit 54 controls the attenuation process of different clock signals. According to the required phase of the output signal, the present invention can select two differential phase interpolation units for signal interpolation each time to output a pair of differential signals.

[0166] It should be understood that only two differential phase interpolation units work in each phase interpolation process of the present invention, that is, only 4 high-frequency clock signals participate in the phase interpolation process, and the weight adjustment unit 54 realizes the output of differential signals with the target phase by adjusting the weights of different clock signals.

[0167] Since Figure 9 the phase interpolator 5 in the embodiment only outputs differential signals, the target phase can be set to only one, or of course, it can also be set to two.

[0168] Now, taking the differential signals with the output target phases of 20 degrees and 200 degrees as an example, the Figure 9 working principle of the phase interpolator 5 shown is described.

[0169] Specifically, in the Figure 9 example, φ 10 (0°) and φ 12 (180°) are input into the first differential phase interpolation unit, and φ 20 (45°) and φ 22 (225°) are input into the second differential phase interpolation unit.

[0170] The φ 10 clock signal is connected to the second node through the transistor M N1 , the φ 12 clock signal is connected to the third node through the transistor M N2 , the φ 20 clock signal is connected to the second node through the transistor M N3 , and the φ 22 clock signal is connected to the third node through the transistor M N4 .

[0171] The weight adjustment unit 54 corresponding to the first differential phase interpolation unit and the weight adjustment unit 54 corresponding to the second differential phase interpolation unit start to work. The first interpolation control sub-signal adjusts the signal amplitudes of 0° and 180°, and the second interpolation control sub-signal adjusts the signal amplitudes of 45° and 225°. Finally, the 0° and 45° signals are vectorially combined into a 20° signal at φ outN , and the 180° and 225° signals are vectorially combined into a 200° signal at φ outP .

[0172] The working principle of the first differential phase interpolation unit will now be described.

[0173] For this differential phase interpolation unit, in the absence of the weight adjustment unit 54, the two currents received at its input from the cross-coupled ring oscillator 3 are equal. However, the presence of the weight adjustment unit 54 can attenuate these two currents, thereby being used to synthesize signals of more phases.

[0174] Please refer to Figure 10 , which shows the process of phase interpolation (vector synthesis) by the phase interpolator 5. Among them, I 1 and I 2 are respectively the two currents from the cross-coupled ring oscillator 3, and their phases are φ n-1 and φ n , and the magnitudes of the two currents after weight adjustment are αI 1 and βI 2 .

[0175] These two currents are vectorially combined by the differential phase interpolation unit into an I tot current, and its phase is φ out . By changing the current weights, the final output phase can be changed. The relationship between the weights and the output phase can be expressed by the following formula:

[0176]

[0177] Please refer to Figure 11 , Figure 11 shows the linearity effect diagram of the phase interpolator 5. It can be seen that in the present invention, the phase interpolator 5 with multi-phase input can effectively improve the output linearity of the phase interpolator 5. When the phase interpolator 5 inputs a 4-phase clock signal, the vector synthesis process is easily affected by the current weights and amplitude non-linearity occurs;

[0178] As the phase interpolator 5 inputs an 8-phase clock signal, the amplitude non-linearity will be suppressed, and a clock signal with a smaller output amplitude error will be output.

[0179] Continuing to increase the input clock phase of the phase interpolator 5 can further reduce the amplitude non-linearity.

[0180] In actual work, the weight adjustment unit 54 can be a controllable current source. Please refer to Figure 12 , and this controllable current source is composed of P current mirrors.

[0181] In this case, the interpolation control sub-signal can include a P-bit control word, and the digital control signal Vctrl <p:1>It is possible to control the number of current mirrors connected to the differential phase interpolation unit, thereby adjusting the current magnitudes passing through the first NMOS transistor and the second NMOS transistor.

[0182] In Figure 11 the example of, Vctrl1 <p:1>and Vctr2 <p:1>Control the currents of different differential phase interpolation units respectively, and then control the amplitude of the clock signal used for interpolation.

[0183] In this case, whether each differential phase interpolation unit works or not is controlled by an external interpolation control sub-signal. It should be understood that the external interpolation control signal only controls two phase interpolation units to work each time clock interpolation is performed.

[0184] Of course, the specific circuit structure of the weight adjustment unit 54 can be designed as needed, and the present invention does not limit this.

[0185] It can be seen that since the phase interpolator 5 of the present invention can utilize 2N pairs of different differential clock signal pairs, it can not only output first and second differential phase signals with higher frequencies, but also has better linearity of the phase interpolator 5.

[0186] In addition, the present invention also provides a wired communication transceiver, including the clock signal generation circuit described in any one of the above.

[0187] As an example, the clock signal generation circuit provided by the present invention can be applied to the clock generation circuit and clock recovery circuit (CDR, Clock Data Recovery) of a wired communication transceiver.

[0188] In practical applications, the wired communication transceiver can be used in multiple fields such as data centers, base stations, and heterogeneous chip integration. Of course, the present invention does not limit this.

[0189] In addition, the present invention also provides an electronic device, including the clock signal generation circuit described in any one of the above. As an example, the electronic device can be a network switch, a router, an embedded device, etc. The present invention does not limit this, and those skilled in the art can select a suitable device for application according to needs.

[0190] In summary, the circuit of the embodiment of the present invention outputs a first DC voltage including phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a frequency discriminator and phase discriminator module. The pulse generator generates a narrow pulse signal based on the DC voltage and the reference clock signal. The oscillation frequencies of the secondary ring oscillators in the cross-coupled ring oscillator are controlled by the first DC voltage. The cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross-coupled ring oscillator receives the narrow pulse signal, and frequency and phase locking are completed by means of injection locking. The frequency divider is used to perform frequency division processing on any high-frequency clock signal and output a feedback clock signal. Thus, the present invention can generate a high-frequency multi-phase clock signal with low phase noise and high phase accuracy by using a low-frequency reference clock signal.

[0191] Although the present invention has been disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A clock signal generating circuit, characterized in that: include: A frequency and phase detection module, configured to output a first DC voltage based on a reference clock signal and a feedback clock signal, wherein the first DC voltage includes phase difference information and frequency difference information between the reference clock signal and the feedback clock signal; a pulse generator, configured to generate a narrow pulse signal based on the first DC voltage and the reference clock signal, wherein the frequency of the narrow pulse signal is the same as the frequency of the reference clock signal, and the narrow pulse signal is used to frequency lock and phase lock a cross-coupled ring oscillator; A cross-coupled ring oscillator, comprising N secondary ring oscillators and a cross-coupling loop, wherein the cross-coupling loop is coupled to four output nodes of the N secondary ring oscillators based on a phase sequence, one output node of the N secondary ring oscillators also receives the narrow pulse signal, and a frequency control terminal of each secondary ring oscillator receives the first DC voltage, wherein N is an integer greater than or equal to 1; Each secondary ring oscillator is used to output four high-frequency clock signals with equal phase intervals, and the cross-coupling loop is used to perform synchronous coupling processing and phase sequence adjustment processing on each secondary ring oscillator; The frequency divider is used to perform frequency division processing on any of the high-frequency clock signals and output a feedback clock signal.

2. The clock signal generating circuit according to claim 1, wherein: The cross-coupling loop includes N coupling units connected end to end; The output ends of the N coupling units are sequentially coupled to the output nodes of the secondary ring oscillator in phase order, and the coupling units are used for voltage-current conversion and signal amplification; Each coupling unit is used to output a corresponding coupling current to a corresponding output node, so that the cross-coupled ring oscillator outputs N oscillation clock signals with equal phase intervals, and the N oscillation clock signals with equal phase intervals are equally divided into 4 oscillation clock signal groups according to the phase sequence, and the oscillation clock signals in each oscillation clock signal group are derived from different secondary ring oscillators.

3. The clock signal generating circuit according to claim 2, wherein: The coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

4. The clock signal generating circuit according to claim 2, wherein: The secondary ring oscillator includes two identical delay units; wherein: The first output end of the first delay unit is coupled to the first input end of the second delay unit, and the second output end of the first delay unit is coupled to the second input end of the second delay unit; The first output end of the second delay unit is coupled to the second input end of the first delay unit, and the second output end of the second delay unit is coupled to the first input end of the first delay unit; Wherein, the first output end and the second output end of the delay unit also receive corresponding coupling currents.

5. The clock signal generating circuit according to claim 4, characterized in that: The delay unit comprises: a positive phase main inverter, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage through the first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal; an inverting main inverter, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage through the first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal; A first cross-coupled inverter coupled between the first output terminal and the second output terminal; The first output end and the second output end of the delay unit further receive the two coupling currents corresponding to the delay unit respectively.

6. The clock signal generating circuit according to claim 5, characterized in that: The delay unit further includes a power supply voltage regulating module and a current regulating module, wherein the power supply voltage regulating module and the current regulating module are both coupled between the first node and the power supply voltage, a control end of the power supply voltage regulating module receives a power supply voltage regulating signal, and a control end of the current regulating module receives the first DC voltage; The power supply voltage regulating module is used to control the power supply voltage of the positive phase main inverter and the negative phase main inverter based on the power supply voltage regulating signal, and adjust the delay size of the positive phase main inverter and the negative phase main inverter to adjust the free oscillation frequency of the delay unit; The current regulating module is used to control the magnitude of the current flowing through the delay unit based on the first DC voltage, so as to adjust the free oscillation frequency of the delay unit.

7. The clock signal generating circuit according to claim 1, wherein: The frequency and phase detection module comprises: a frequency and phase detector, a first low-pass filter, a second low-pass filter and a subtractor; The first input terminal of the frequency detector receives the reference clock signal, the second input terminal thereof receives the feedback clock signal, the first output terminal thereof is coupled to the non-inverting input terminal of the subtractor through the first low-pass filter, the first output terminal thereof is coupled to the inverting input terminal of the subtractor through the second low-pass filter, and the output terminal of the subtractor outputs the first DC voltage.

8. The clock signal generating circuit according to claim 7, wherein: The frequency and phase detector comprises a first D flip-flop, a second D flip-flop and a first AND gate unit; The clock input terminal of the first D flip-flop receives the reference clock signal, the data input terminal thereof receives the power supply voltage, the output terminal thereof is coupled to the first input terminal of the first AND gate unit, the reset terminal thereof is coupled to the output terminal of the first AND gate unit, and the output terminal of the first D flip-flop is also coupled to the non-inverting input terminal of the subtractor through the first low-pass filter; The clock input terminal of the second D flip-flop receives the feedback clock signal, the data input terminal thereof is grounded, the output terminal thereof is coupled to the second input terminal of the first AND gate unit, the reset terminal thereof is coupled to the output terminal of the first AND gate unit, and the output terminal of the second D flip-flop is also coupled to the inverting input terminal of the subtractor through the second low-pass filter.

9. The clock signal generating circuit according to claim 1, wherein: The pulse generator includes M buffer units and a second AND gate unit, each buffer unit includes a buffer and a PMOS transistor, wherein M is an integer greater than or equal to 2; The bias voltage terminal of each buffer receives the power supply voltage through the corresponding PMOS transistor, and the gate of each PMOS transistor receives the first DC voltage; The input end of the 1st buffer receives the reference clock signal, the output end of the i-th buffer and the output end of the M-th buffer are respectively coupled to the first input end and the second input end of the second AND gate unit, and the output end of the second AND gate unit outputs the narrow pulse signal, where i is an integer and 1≤i<M.

10. The clock signal generating circuit according to claim 1, wherein: The frequency divider is coupled to any output node, and the frequency divider includes a third D flip-flop, a fourth D flip-flop, an OR gate unit, a third AND gate unit, and a second buffer; The clock input terminal of the third D flip-flop receives the high-frequency clock signal, and the data input terminal thereof is respectively coupled to the first input terminal of the third AND gate unit and the input terminal of the second buffer, the output terminal of the third D flip-flop is coupled to the first input terminal of the OR gate unit, the second input terminal of the OR gate unit receives an external control signal, the output terminal of the OR gate unit is coupled to the second input terminal of the third AND gate unit, the output terminal of the third AND gate unit is coupled to the data input terminal of the fourth D flip-flop, the clock input terminal of the fourth D flip-flop receives the high-frequency clock signal, and the output terminal thereof is coupled to the input terminal of the second buffer, and the output terminal of the second buffer outputs the feedback clock signal.

11. The clock signal generating circuit according to claim 1, wherein: The clock signal generating circuit also includes a crystal oscillator; The crystal oscillator is coupled to the frequency and phase detection module and the pulse generator respectively, and the crystal oscillator is used to output the reference clock signal.

12. The clock signal generating circuit according to any one of claims 1 to 11, characterized in that: The clock signal generating circuit also includes a phase interpolator; The input end of the phase interpolator receives 2N pairs of different differential clock signal pairs, and the control end thereof receives an interpolation control signal, each pair of differential clock signal pairs includes two high-frequency clock signals with a phase difference of 180°, and the interpolation control signal includes target phase information; The phase interpolator is configured to: based on an interpolation control signal, select two pairs of differential clock signal pairs for signal weighted processing, output a first differential phase signal and a second differential phase signal, and the phase of the first differential phase signal and / or the phase of the second differential phase signal are the same as the target phase information.

13. The clock signal generating circuit according to claim 12, wherein: The phase interpolator comprises: a first voltage-current conversion unit, a second voltage-current conversion unit, 2N differential phase interpolation units and 2N weight adjustment units, and the interpolation control signal comprises 2N interpolation control sub-signals; The first end of each differential phase interpolation unit is coupled to the first voltage-current conversion unit via a second node, the second end of each differential phase interpolation unit is coupled to the second voltage-current conversion unit via a third node, the third end of each differential phase interpolation unit is grounded via a corresponding weight adjustment unit, the control end of each weight adjustment unit receives a corresponding interpolation control sub-signal, the first voltage-current conversion unit and the second voltage-current conversion unit are coupled to a power supply voltage, the second node is used to output the first differential phase signal, and the third node is used to output the second differential phase signal; The input end of each differential phase interpolation unit receives a corresponding differential clock signal pair, and the differential clock signal pairs received by the input end of each differential phase interpolation unit are different.

14. The clock signal generating circuit according to claim 13, wherein: The differential phase interpolation unit includes a first NMOS tube and a second NMOS tube; The drain of the first NMOS tube is coupled to the second node, the drain of the second NMOS tube is coupled to the third node, the source of the first NMOS tube and the source of the second NMOS tube are both grounded through the corresponding weight adjustment unit; the gate of the first NMOS tube and the gate of the second NMOS tube are respectively used to receive the two high-frequency clock signals in the corresponding differential clock signal pair.

15. A wired communication transceiver, characterized in that: It comprises the clock signal generating circuit as claimed in any one of claims 1 to 14.

16. An electronic device, characterized in that: It comprises the clock signal generating circuit as claimed in any one of claims 1 to 14.

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