Verification method and system of chip simulation model, medium and program product

Abstract

The invention discloses a verification method and system of a chip simulation model, a medium and a program product, and relates to the technical field of chip verification, and the method comprises the steps: obtaining a simulation model and a performance parameter index of a to-be-verified chip; generating model training data based on the historical performance indexes, the corresponding historical use case set and the historical verification result, and performing model training based on the model training data to obtain a use case generation model; inputting the performance parameter indexes to a case generation model to obtain a test case set and a test verification expectation; executing a plurality of test cases in the test case set based on the simulation model, and recording an actual response result of the simulation model; based on the actual response result and the test verification expectation, generating a test log, and determining an abnormal mark in the test log; and marking the fault features corresponding to the exception, taking the test cases as newly added training data, and optimizing the case generation model based on the newly added training data. According to the invention, the chip verification efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular, to a method, system, medium, and program product for verifying a chip simulation model. Background Art

[0002] With the continuous development of integrated circuit technology and the continuous improvement of application requirements, chip design is increasingly tending towards large-scale, complexity, and high performance. In this context, chip design verification has become a key link to ensure product quality. Among them, simulation verification, as the main verification method, is of great significance for early detection and elimination of design defects and ensuring the correctness of chip functions.

[0003] The related technology adopts a simulation verification method based on preset test cases. This method constructs test cases containing input stimuli, timing constraints, etc. by manually writing test scripts, and then runs these cases in a simulation environment to observe the response of each functional module of the chip. The verification personnel judge whether the chip behavior meets the expectations according to the simulation results, and locate and analyze abnormal phenomena through debugging tools.

[0004] However, the traditional debugging process mainly relies on manual analysis and judgment. Facing complex fault phenomena, it often takes repeated attempts to find the root cause of the problem, which seriously affects the verification efficiency. Summary of the Invention

[0005] This application provides a method, system, medium, and program product for verifying a chip simulation model, which is used to improve the chip verification efficiency.

[0006] In a first aspect, this application provides a method for verifying a chip simulation model, which is applied to a simulation system. The method includes: obtaining a simulation model and performance parameter indicators of a chip to be verified; generating model training data based on historical performance indicators, corresponding historical use case sets, and historical verification results, and performing model training based on the model training data to obtain a use case generation model; inputting the performance parameter indicators into the use case generation model to obtain a test case set and test verification expectations; executing multiple test cases in the test case set based on the simulation model, and recording the actual response results of the simulation model; generating a test log based on the actual response results and the test verification expectations, and determining the abnormal marks in the test log; using the fault features and test cases corresponding to the abnormal marks as new training data, and optimizing the use case generation model based on the new training data.

[0007] In the above embodiments, the simulation system realizes the intelligent generation and continuous optimization of test cases by training a use case generation model based on historical data and feeding back the verification results to optimize the model. By automatically generating a targeted set of test cases, comparing the actual response results with the expectations, promptly detecting anomalies, and using the relevant information for model optimization, the efficiency and accuracy of chip verification are improved.

[0008] In combination with some embodiments of the first aspect, in some embodiments, after the steps of generating a test log based on the actual response results and test verification expectations and determining the anomaly markers in the test log, the method further includes: determining the actual fault characteristics corresponding to the anomaly markers; performing a similarity match between the actual fault characteristics and the historical fault characteristics in the historical use case set, determining the historical fault characteristics with the highest similarity and the corresponding historical verification results, and extracting the historical fault causes and historical solutions corresponding to the historical verification results; generating multiple fault handling suggestions based on the historical fault characteristics, historical fault causes, and historical solutions; and integrating the multiple fault handling suggestions according to the real-time performance data of the simulation model to generate a list of fault handling suggestions sorted by priority.

[0009] In the above embodiments, the simulation system can quickly locate the problem cause based on historical experience and provide targeted solution suggestions by performing a similarity match between the current anomaly and historical fault characteristics and generating a list of fault handling suggestions sorted by priority in combination with the historical verification results, thus improving the fault handling efficiency.

[0010] In combination with some embodiments of the first aspect, in some embodiments, the step of recording the actual response results of the simulation model based on the execution of multiple test cases in the test case set specifically includes: determining the complexity values of the multiple test cases in the test case set, performing a priority ranking on the multiple test cases based on the complexity values to obtain a test case queue; monitoring the resource utilization rates of each computing node in the distributed verification platform in real time; determining the allocation rules of the multiple test cases on the computing nodes based on the test case queue and the resource utilization rates, and performing task allocation based on the allocation rules; and recording the actual response results of the simulation model on the computing nodes.

[0011] In the above embodiments, the simulation system can perform intelligent task scheduling according to the test case characteristics and the computing node status by evaluating the complexity and performing a priority ranking on the test cases and combining the resource utilization of the distributed verification platform, thus improving the overall utilization efficiency of the verification platform.

[0012] In some embodiments in combination with some embodiments of the first aspect, before the step of obtaining the simulation model and performance parameter indicators of the chip to be verified, the method further includes: determining chip features including protocol specifications, architecture features, and key performance parameters according to the type identifier of the chip to be verified; constructing a hierarchical module division template according to the chip features; the levels include an interface layer, a control layer, a computing layer, and a storage layer; performing functional module mapping on the chip to be verified based on the module division template to generate a monitoring point configuration table; the monitoring point configuration table includes signal types, timing requirements, and verification rules for each level; generating a probe program adapted to the chip to be verified according to the monitoring point configuration table; the probe program is used to collect performance index data and timing signal data of each monitoring point during simulation operation.

[0013] In the above embodiments, the simulation system realizes systematic monitoring of chip functions by establishing a hierarchical module division template and a monitoring point configuration system, automatically generates an adapted probe program according to chip features, realizes accurate acquisition of signals and performance indicators at each level, and facilitates subsequent verification.

[0014] In some embodiments in combination with some embodiments of the first aspect, after the step of generating a probe program adapted to the chip to be verified according to the monitoring point configuration table, the method further includes: calculating multi-dimensional evaluation index scores including timing integrity, functional correctness, resource utilization rate, and performance bottleneck based on the real-time data collected by the probe program; determining corresponding abnormal functional modules according to the evaluation index scores and preset benchmark indexes, and extracting state features and data features corresponding to the abnormal functional modules; inputting the state features and data features into an abnormal classification model to obtain an abnormal type and a confidence score; when the confidence score is higher than a preset confidence threshold, displaying an abnormal prompt message including the abnormal functional module and the abnormal type.

[0015] In the above embodiments, the simulation system realizes accurate identification of chip performance anomalies through multi-dimensional evaluation index calculation and an abnormal classification model, ensures the accuracy of abnormal judgment by monitoring the operating states of each functional module and through a confidence score mechanism, and improves the reliability of the verification process.

[0016] In some embodiments in combination with some embodiments of the first aspect, after the steps of using the fault features and test cases corresponding to the anomaly marks as new training data and optimizing the use case generation model based on the new training data, the method further includes: constructing a fault feature knowledge graph and adding the fault feature nodes in the new training data to the fault feature knowledge graph; calculating the association strength between each fault feature node in the fault feature knowledge graph based on a graph attention network, and determining a fault feature cluster with a correlation higher than a preset correlation threshold based on the association strength; using the historical verification data of the fault feature cluster as training data to generate a fault prediction model; when detecting a performance anomaly trend during the simulation process, invoking the fault prediction model for early warning and fault location.

[0017] In the above embodiments, the simulation system realizes fault prediction and early warning by constructing a fault feature knowledge graph and analyzing feature correlation based on a graph attention network, can learn fault patterns from historical verification data, and give an early warning in time when detecting an anomaly trend, effectively reducing the fault risk.

[0018] In some embodiments in combination with some embodiments of the first aspect, the steps of generating a test log based on the actual response result and the test verification expectation and determining the anomaly marks in the test log specifically include: generating a test log including operation events, execution time, and result status according to the actual response result; converting the actual response result into a multi-dimensional feature vector including timestamps, function block identifiers, status values, and performance metric values in a time series; generating a difference matrix including deviation types and deviation degrees based on the multi-dimensional feature vector and the test verification expectation; extracting a set of anomaly points exceeding a preset deviation threshold based on the difference matrix to generate anomaly marks, and integrating the anomaly marks into the test log.

[0019] In the above embodiments, the simulation system realizes the accurate evaluation of test results by converting the response result into a multi-dimensional feature vector and performing difference analysis, can automatically identify anomaly points exceeding the preset threshold, and generate a detailed test log, providing a reliable basis for the analysis of verification results.

[0020] In a second aspect, an embodiment of the present application provides a simulation system, which includes: one or more processors and a memory; the memory is coupled to the one or more processors, and the memory is used to store computer program code, the computer program code includes computer instructions, and the one or more processors invoke the computer instructions to enable the simulation system to execute the methods described in the first aspect and any possible implementation manner in the first aspect.

[0021] In a third aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when the computer program product is run on a simulation system, enables the simulation system to execute the method described in the first aspect and any possible implementation of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions, which, when executed on a simulation system, enable the simulation system to execute the method described in the first aspect and any possible implementation of the first aspect.

[0023] It is understandable that the simulation system provided in the second aspect, the computer program product provided in the third aspect, and the computer storage medium provided in the fourth aspect are all used to execute the method provided in the embodiment of the present application. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method, which will not be repeated here.

[0024] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. Since the method of generating models based on historical verification data training cases and continuously optimizing through verification results is adopted, the system can automatically learn historical verification experience, generate targeted test cases, and continuously improve model performance through feedback mechanism, which effectively solves the problem that test case generation in the existing technology relies on manual experience and lacks adaptive ability, thereby realizing the precision of test case generation, improving verification efficiency, and ensuring the comprehensiveness and accuracy of verification coverage.

[0025] 2. Due to the adoption of hierarchical module division and monitoring point configuration method based on chip characteristics, as well as adaptive probe program generation technology, the system can automatically build a suitable monitoring framework according to the chip type and realize accurate collection of signals at all levels, effectively solving the problems of cumbersome monitoring point configuration and difficulty in adapting to different chip characteristics in the existing technology, thereby realizing the systematization and standardization of the verification process, ensuring the integrity and accuracy of performance data collection.

[0026] 3. Due to the use of fault feature analysis based on knowledge graph and correlation calculation method of graph attention network, the system can deeply explore the potential correlation between fault features and build an accurate fault prediction model, which effectively solves the problem of insufficient fault prediction ability and inability to timely detect potential risks in existing technologies, and then realizes fault warning and early intervention in the verification process, thereby improving the reliability of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flow chart of a verification method of a chip simulation model in an embodiment of the present application; Figure 2It is another schematic flowchart of the verification method for the chip simulation model in the embodiments of the present application; Figure 3 It is a schematic structural diagram of an entity device of the simulation system in the embodiments of the present application. Detailed implementation manners

[0028] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the specification of the present application, the singular forms "a", "an", "the above", "the", and "this" are also intended to include the plural forms, unless clearly indicated to the contrary in the context. It should also be understood that the term "and / or" used in the present application refers to any or all possible combinations including one or more of the listed items.

[0029] Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as implying or suggesting relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0030] For ease of understanding, the application scenarios of the embodiments of the present application are introduced below.

[0031] A certain chip design company is developing a complex AI chip, which integrates multiple functional modules such as a neural network processor, multi-level caches, and high-speed interfaces. During the verification phase, engineers found that the chip would have intermittent data transmission errors under high load. These errors are irregular and behave inconsistently in different test environments. Traditional manual analysis methods require a large amount of time to check each module one by one, and it is very difficult to reproduce and locate the problems. At the same time, due to the complexity of the chip, the number of possible failure modes is huge, and it is difficult for humans to cover all test scenarios. This leads to an extended verification cycle and affects the product development progress.

[0032] In the related art, the correctness verification of chip functions can be achieved by adopting an artificial verification method based on preset test cases. The verification personnel manually write test scripts, set input stimuli and verification rules, run the tests in the simulation environment, and then view the results through a waveform analysis tool.

[0033] The scenarios of using the verification method in the related art are introduced below.

[0034] Engineers tried to use traditional verification methods based on preset test cases. They wrote hundreds of test scripts to cover various possible usage scenarios. Each script required manual design of input stimuli, definition of verification rules, and expected results. When anomalies were found, the verification personnel manually analyzed the signal waveforms through a waveform viewer to try to locate the source of the problem. However, this method had obvious defects: it was difficult for test cases to cover all scenarios, manual script writing was error-prone, and when complex interactive failures occurred in the chip, relying solely on waveform analysis often could not accurately locate the root cause. In addition, as the testing progressed, a large number of test logs needed to be manually screened and analyzed, resulting in low efficiency.

[0035] By adopting the verification method of the chip simulation model in the embodiments of the present application, through constructing a use case generation model based on machine learning, a hierarchical monitoring framework, and a fault feature knowledge graph, automated test case generation, multi-dimensional performance evaluation, and intelligent fault prediction are realized, which not only improves the verification efficiency but also realizes early warning and accurate positioning of faults.

[0036] The following introduces the scenario of using the verification method of the chip simulation model in the present application.

[0037] After adopting the verification method of the present application, when the system detects an abnormal data transmission, the system automatically inputs the collected performance data into the trained use case generation model to quickly generate targeted test cases. These cases are executed in parallel through a distributed verification platform, and the system monitors the execution status of each node in real time. Based on the similarity matching of the historical fault database, the system quickly locates the cache coherence problem that causes the error and generates a prioritized handling suggestion. The whole process requires no manual intervention, improving the verification efficiency.

[0038] It can be seen that by adopting the verification method of the chip simulation model in the embodiments of the present application, while realizing the chip function verification, it can effectively solve problems such as incomplete coverage of test cases, difficult fault location, and low verification efficiency in traditional methods, thereby improving the efficiency of the verification process.

[0039] For easy understanding, the following combines the above scenario to describe the process of the method provided in this embodiment. Please refer to Figure 1 , which is a flowchart of the verification method of the chip simulation model in the embodiments of the present application.

[0040] S101. Obtain the simulation model and performance parameter indicators of the chip to be verified.

[0041] Among them, the chip to be verified refers to an integrated circuit chip that needs to be functionally verified and performance - tested; the simulation model represents a software description of the function, structure, and behavioral characteristics of the chip to be verified, usually including RTL - level or gate - level design descriptions; the performance parameter indicators are used to represent the key performance characteristics of the chip, including quantitative indicators such as timing parameters, power consumption indicators, throughput, etc.

[0042] Before starting the verification process, the simulation system needs to first obtain the basic data required for verification. Specifically, the simulation system reads the chip design file through the data interface of the verification platform and parses it to generate the corresponding simulation model; at the same time, it extracts the performance index requirements from the chip design specification, including parameters such as timing constraints, power consumption limits, and performance targets, to form a standardized set of performance parameter indicators.

[0043] In some embodiments, the acquisition of the simulation model and performance parameter indicators can be achieved in multiple ways: Optionally, generate the simulation model by parsing the HDL design file and extract the performance parameters from the design constraint file: read the RTL - level HDL description file; perform syntax analysis and compilation; establish a memory data model; parse the SDC constraint file to extract parameters. Optionally, directly call the existing simulation model and parameter configuration from the verification platform database: query the chip model information; match the corresponding model from the model library; extract the configuration data from the parameter library. It can be understood that other ways can also be used to achieve the process of obtaining the model and parameters, such as reading through the API interface or manual configuration, etc., which are not limited here.

[0044] S102. Generate model training data based on historical performance indicators, the corresponding historical test case set, and historical verification results, and perform model training based on the model training data to obtain a test case generation model.

[0045] Among them, the historical performance indicators represent the performance parameter records of the verified chips; the historical test case set refers to the test case library used in the previous verification process; the historical verification results are used to represent the execution results and fault records of the corresponding test cases; the model training data refers to the standardized data set used to train the test case generation model; the test case generation model represents a machine - learning model that can automatically generate test cases according to input parameters.

[0046] After the simulation system obtains the basic data, it needs to construct and train the test case generation model. Specifically, the simulation system first extracts historical performance indicators, test case sets, and verification results from the verification history database, cleans and standardizes the data, and establishes a training sample set; then selects a suitable machine - learning algorithm, uses the processed training data for model training and verification, and finally obtains a model that can generate test cases according to performance indicators.

[0047] It should be noted that in the use case generation model of this application, during the training phase, historical performance metrics (such as timing parameters, power consumption metrics, bandwidth requirements, etc.), historical use case sets (including test scenarios, input stimuli, verification rules, etc.), and historical verification results (including execution status, fault records, repair solutions, etc.) are input as training data; the model analyzes the verification effects and coverage rates of historical use cases as training objectives to learn the mapping relationship between performance metrics and effective test cases. This use case generation model adopts a deep neural network structure, including a feature extraction layer, a scenario understanding layer, and a use case generation layer, and can understand performance requirements and generate corresponding test strategies. During use, by inputting the performance parameter metrics of the chip to be verified, the model outputs a targeted test case set and expected verification results, and the test case set includes detailed test steps and verification rules.

[0048] In some embodiments, the generation of model training data and model training can be achieved in various ways: Optionally, a supervised learning method is used to train the generation model: construct a historical data feature matrix; annotate the use case effect score; divide the training set and the verification set; train the model and optimize the parameters; evaluate the model performance. Optionally, a reinforcement learning method is used to train the generation model: define the state space and the action space; design the reward function; initialize the policy network; perform interactive training and optimization; verify the model effect. It can be understood that other methods can also be used to implement the model training process, such as transfer learning or ensemble learning, etc., which are not limited here.

[0049] S103. Input the performance parameter metrics into the use case generation model to obtain a test case set and test verification expectations.

[0050] Among them, the performance parameter metrics represent the performance requirements of the current chip to be verified; the test case set refers to a set of test cases generated by the model; the test verification expectations are used to represent the expected verification results of each test case.

[0051] After the model training is completed, the simulation system starts to generate targeted test cases. Specifically, the simulation system inputs the performance parameter metrics of the chip to be verified into the trained use case generation model, and the model automatically generates a set of use cases covering various test scenarios according to the input parameters, and at the same time predicts the expected execution results of each use case to form a complete test verification plan.

[0052] S104. Execute multiple test cases in the test case set based on the simulation model, and record the actual response results of the simulation model.

[0053] Among them, the actual response results are used to represent the behavior performance and output data of the simulation model when executing test cases; executing test cases refers to the process of running a test program in a simulation environment and collecting data.

[0054] After the simulation system prepares the test cases, it begins to execute the verification process. Specifically, the simulation system first initializes the simulation environment, converts the test cases into executable stimulus sequences, then sequentially executes each test case on the simulation model, monitors and records the response status, output signals, and performance metrics of the model in real time, and finally forms a complete test execution record.

[0055] In some embodiments, the execution of test cases and the recording of response results can be achieved in multiple ways: Optionally, a serial execution method is adopted: configure the simulation environment parameters; load the test cases; execute the simulation process; collect the response data; save the execution record. Optionally, use parallel distributed execution: task decomposition and allocation; multi-node synchronous startup; parallel execution of cases; summarize the response data; generate an execution report. It can be understood that other methods can also be used to implement the test execution process, such as hybrid execution or dynamic scheduling, etc., which are not limited here.

[0056] S105. Generate a test log based on the actual response results and the test verification expectations, and determine the exception markers in the test log.

[0057] Among them, the test log refers to a detailed information file recording the test process; the exception marker refers to an identifier of a test result that does not meet the expectations; the test verification expectations are used to represent the expected correct results.

[0058] After the simulation system completes the test execution, it needs to analyze the verification results. Specifically, the simulation system compares and analyzes the collected actual response results with the pre-set test verification expectations, generates a detailed test log including the execution process, performance data, and result comparison, and at the same time identifies and marks the abnormal situations therein, including problems such as functional errors and performance non-compliance.

[0059] In some embodiments, the generation of test logs and the marking of exceptions can be achieved in multiple ways: Optionally, based on rule matching analysis: extract response features; compare with verification expectations; calculate the deviation degree; determine the exception type; generate exception markers. Optionally, use machine learning methods for detection: construct feature vectors; input into the anomaly detection model; calculate the anomaly probability; determine the anomaly threshold; mark the abnormal items. It can be understood that other methods can also be used to implement the result analysis process, such as statistical analysis or expert system methods, etc., which are not limited here.

[0060] S106. Use the fault features and test cases corresponding to the exception markers as new training data, and optimize the test case generation model based on the new training data.

[0061] Among them, the fault feature represents the feature description of the abnormal situation; the new training data refers to the model optimization data extracted from the current verification process; the optimized test case generation model refers to the process of updating the model parameters to improve the performance.

[0062] After the simulation system completes the anomaly analysis, it performs model optimization. Specifically, the simulation system extracts the test records with anomaly marks from the test logs, analyzes and extracts the corresponding fault features and related test cases, and uses these data as new training samples to perform incremental training and parameter optimization on the use case generation model to improve the model's processing ability for similar scenarios.

[0063] In some embodiments, model optimization can be achieved in various ways: Optionally, an online learning method is adopted: extract new features; construct training batches; perform incremental training; evaluate model effects; update model parameters. Optionally, a transfer learning method is used: freeze the base layer; add an adaptation layer; fine-tune model parameters; verify the optimization effect; save the optimized model. It can be understood that other ways can also be adopted to implement the model optimization process, such as ensemble learning or active learning, etc., which are not limited here.

[0064] In the above embodiments, the simulation system collects performance data in real time through a probe program and uses a machine learning model for analysis and prediction. In actual applications, the system can automatically generate targeted test cases, quickly locate the cause of the fault, and provide processing suggestions with priority sorting.

[0065] The following supplements the scenario of this embodiment.

[0066] As the system continues to run, the fault feature knowledge graph is continuously enriched, and the system's prediction ability is improved. In a verification, the system analyzed through a graph attention network and found that the change patterns of certain performance indicators were highly correlated with historical fault cases, providing an early warning before the actual fault occurred. Through the optimized use case generation model, the system automatically generated a series of boundary test cases and successfully discovered a potential design defect. At the same time, the system can dynamically adjust the test strategy based on the real-time load status, optimizing resource usage while ensuring verification coverage. This intelligent verification method has increased the chip verification efficiency by 300% and shortened the verification cycle by 60%.

[0067] After combining the above scenarios, the following further describes the more specific process of the method provided in this embodiment in more detail. Please refer to Figure 2 , which is another process schematic diagram of the verification method for the chip simulation model in the embodiments of the present application.

[0068] S201. Determine the chip features including protocol specifications, architecture features, and key performance parameters according to the type identifier of the chip to be verified.

[0069] Among them, the type identifier represents the basic classification information of the chip; the protocol specification refers to the communication and interface standards followed by the chip; the architecture feature is used to represent the internal structure and organization mode of the chip; the key performance parameters represent the core technical indicators of the chip, including clock frequency, power consumption, bandwidth, etc.; the chip feature refers to the set of technical parameters used to describe the overall characteristics of the chip.

[0070] Before starting the module division, the simulation system needs to first clarify the specific characteristics of the chip. Specifically, the simulation system analyzes the model identifier of the chip, queries the feature database to obtain the standard protocol specification of this type of chip, analyzes its internal architecture features, extracts the key performance parameters, and finally forms a complete chip feature description document to provide a basis for subsequent module division.

[0071] S202. Construct a hierarchical module division template according to the chip features.

[0072] Among them, the hierarchical module division template represents the hierarchical organizational structure of the chip functional modules.

[0073] After determining the chip features, the simulation system needs to establish a standardized module division structure. Specifically, the simulation system designs four basic functional levels according to the chip feature analysis, defines standard interfaces and interaction rules for each level; the interface layer refers to the set of modules responsible for external communication; the control layer is used to represent the module group for management and scheduling functions; the computing layer represents the core modules for executing data processing; the storage layer refers to the cache and storage modules responsible for data access. The simulation system will construct the connection relationships and data flow directions between the modules to form a complete module division template for guiding subsequent function mapping.

[0074] In some embodiments, the construction of the module division template can be achieved in multiple ways: Optionally, adopt the top-down decomposition method: define the hierarchical structure; divide the functional boundaries; design the interface specifications; establish the interconnection relationships; verify the integrity of the template. Optionally, use the template library configuration method: select the basic template; customize the hierarchical structure; configure the module parameters; optimize the module relationships; generate the final template. It can be understood that other methods can also be used to implement the construction process of the module division template, such as bottom-up aggregation or hybrid methods, etc., which are not limited here.

[0075] S203. Perform function module mapping on the chip to be verified based on the module division template to generate a monitoring point configuration table.

[0076] Among them, the function module mapping represents the process of corresponding the chip functions to the template levels; the monitoring point configuration table is a data structure that defines the verification monitoring positions and rules.

[0077] After the simulation system completes the construction of the module division template, it performs specific function mapping. Specifically, the simulation system maps each functional module of the chip to be verified to the corresponding level according to its characteristics, determines the key signal points to be monitored at each level, defines the signal types, timing requirements, and verification rules of these monitoring points, and finally generates a complete monitoring point configuration table; the signal type is used to represent the types of data signals to be monitored; the timing requirements represent the timing constraints for signal sampling and verification; the verification rules refer to the set of criteria for judging the correctness of signals.

[0078] In some embodiments, the generation of the monitoring point configuration table can be achieved in various ways: Optionally, configure based on empirical rules: identify key signal points; define monitoring parameters; set verification rules; configure timing constraints; generate a configuration table. Optionally, adopt an automated analysis method: analyze the design file; extract signal features; generate a monitoring strategy; optimize the distribution of monitoring points; output configuration data. It can be understood that other methods can also be used to implement the process of monitoring point configuration, such as interactive configuration or template reuse, etc., which are not limited here.

[0079] S204. Generate a probe program adapted to the chip to be verified according to the monitoring point configuration table.

[0080] Among them, the probe program refers to the embedded code used to collect monitoring data; adapted to the chip to be verified means the matching of the probe program with the specific chip design.

[0081] After the simulation system completes the monitoring point configuration, it needs to generate a specific data acquisition program. Specifically, the simulation system generates corresponding data acquisition code for each monitoring point according to the monitoring point configuration table, including signal sampling, data processing, and storage logic, to ensure that the probe program can accurately collect the required performance indicators and timing data; the performance indicator data refers to the quantitative indicators reflecting the chip performance; the timing signal data is used to represent the timing characteristics of signal changes.

[0082] In some embodiments, the generation of the probe program can be achieved in various ways: Optionally, adopt a templated generation method: select a probe template; configure sampling parameters; generate acquisition code; add processing logic; optimize program performance. Optionally, use automatic code generation: parse configuration requirements; generate a program framework; implement the acquisition function; integrate processing modules; verify the correctness of the program. It can be understood that other methods can also be used to implement the process of generating the probe program, such as manual programming or component reuse, etc., which are not limited here.

[0083] In some embodiments, the simulation system calculates multi-dimensional evaluation metric scores including timing integrity, functional correctness, resource utilization, and performance bottlenecks based on real-time data collected by a probe program; determines corresponding abnormal functional modules according to the evaluation metric scores and preset benchmark metrics, and extracts the state features and data features corresponding to the abnormal functional modules; inputs the state features and data features into an anomaly classification model to obtain the anomaly type and confidence score; when the confidence score is higher than a preset confidence threshold, it displays an anomaly prompt message including the abnormal functional module and the anomaly type.

[0084] Among them, the probe program refers to a monitoring program used to collect chip operation data; timing integrity refers to the correct degree of signal timing relationship; functional correctness is used to represent the accuracy of function execution; resource utilization represents the usage efficiency of system resources; performance bottleneck is used to represent the key factors restricting system performance; the evaluation metric score refers to the quantitative score of each dimension of performance; the state feature represents the running state description of the abnormal module; the data feature refers to the data performance feature of the abnormal module; the confidence score is used to represent the credibility of the anomaly judgment.

[0085] During the operation monitoring stage, the simulation system needs to perform multi-dimensional evaluation on the chip performance. Specifically, the simulation system continuously collects real-time operation data through the probe program, calculates the evaluation scores of four dimensions: timing integrity, functional correctness, resource utilization, and performance bottleneck respectively, compares the scores with the preset benchmark, identifies the abnormal functional modules, extracts their state and data features, inputs them into the anomaly classification model for analysis, and when the confidence level exceeds the threshold, generates and displays an anomaly prompt message.

[0086] It should be noted that in the training stage of the above anomaly classification model, the state features (such as signal state, resource occupancy, etc.) and data features (such as performance indicators, timing data, etc.) in the historical anomaly data are input as training data; the known anomaly type labels are used as training targets, and the model parameters are optimized by minimizing the classification error. The anomaly classification model uses a multi-layer classifier structure, including modules such as feature extraction, pattern recognition, and classification decision-making, and can identify different types of anomaly patterns. By inputting the state features and data features collected in real time, the model can output anomaly type judgments and confidence scores for anomaly detection and early warning.

[0087] S205. Obtain the simulation model and performance parameter indicators of the chip to be verified.

[0088] Referring to step S101, the simulation system determines the simulation model and performance parameter indicators.

[0089] S206. Generate model training data based on historical performance indicators, the corresponding historical use case set, and historical verification results, and perform model training based on the model training data to obtain a use case generation model.

[0090] Referring to step S102, the simulation system trains the test case generation model.

[0091] S207. Input performance parameter indicators into the test case generation model to obtain a test case set and test verification expectations.

[0092] Referring to step S103, the simulation system generates a test case set and test verification expectations.

[0093] S208. Execute multiple test cases in the test case set based on the simulation model, and record the actual response results of the simulation model.

[0094] Referring to step S104, the simulation system determines the actual response results.

[0095] In some embodiments, the simulation system determines the complexity values of multiple test cases in the test case set, sorts the multiple test cases based on the complexity values to obtain a test case queue, monitors the resource utilization rates of each computing node in the distributed verification platform in real time, determines the allocation rules of the multiple test cases on the computing nodes based on the test case queue and the resource utilization rates, and performs task allocation based on the allocation rules, and records the actual response results of the simulation model on the computing nodes.

[0096] Among them, the complexity value represents the computing resource requirements of the test case; the priority sorting refers to determining the execution order according to the complexity; the test case queue is used to represent the sorted case sequence; the computing node represents the processing unit in the distributed platform; the resource utilization rate refers to the resource occupancy situation of the computing node; the allocation rule is used to represent the policy basis for task allocation; the actual response result represents the output data of the test execution.

[0097] Before the simulation system executes the test cases, it needs to perform task scheduling optimization. Specifically, the simulation system first evaluates the complexity of each test case, performs priority sorting according to the complexity to form an execution queue, monitors the resource status of each node in the distributed platform at the same time, formulates an optimal task allocation strategy based on the case queue and the resource status, allocates the test tasks to the appropriate computing nodes for execution, and records the execution results of each node.

[0098] In some embodiments, task scheduling and execution can be implemented in multiple ways: Optionally, a dynamic scheduling strategy is adopted: calculate the task complexity, generate a priority queue, monitor the node status, optimize the task allocation, and collect the execution results. Optionally, a load balancing method is used: analyze the resource requirements, evaluate the node load, formulate an allocation plan, perform task scheduling, and record the operation data. It can be understood that other methods can also be used to implement the task scheduling and execution process, such as the greedy algorithm or the heuristic search method, etc., which are not limited here.

[0099] S209. Generate a test log based on the actual response result and the test verification expectation, and determine the anomaly markers in the test log.

[0100] Referring to step S105, the simulation system generates a test log and performs anomaly marking.

[0101] In some embodiments, the simulation system determines the actual fault characteristics corresponding to the anomaly markers; performs similarity matching between the actual fault characteristics and the historical fault characteristics in the historical use case set to determine the historical fault characteristics with the highest similarity and the corresponding historical verification results, and extracts the historical fault causes and historical solutions corresponding to the historical verification results; generates multiple fault handling suggestions based on the historical fault characteristics, historical fault causes, and historical solutions; and integrates the multiple fault handling suggestions according to the real-time performance data of the simulation model to generate a list of fault handling suggestions sorted by priority.

[0102] Among them, the actual fault characteristics represent the currently detected fault manifestations; the historical fault characteristics refer to the known fault characteristics stored in the database; the similarity matching is used to represent the calculation of the similarity degree between features; the historical fault causes represent the root causes of the faults; the historical solutions refer to the successful experiences in handling similar faults; and the fault handling suggestions represent the recommended solutions to solve the current faults.

[0103] After detecting a fault, the simulation system needs to provide handling suggestions. Specifically, the simulation system extracts the feature description of the current fault, calculates the similarity with the fault characteristics in the historical database, finds the most similar historical case and its solution, combines the fault characteristics, cause analysis, and solution experience to generate multiple possible handling suggestions, and finally sorts the suggestions by priority according to the current real-time state of the system to form an ordered list of suggestions.

[0104] In some embodiments, the generation of fault handling suggestions can be achieved in multiple ways: Optionally, based on the case-based reasoning method: feature extraction and matching; solution similarity calculation; solution adaptation; suggestion priority sorting; generation of a suggestion report. Optionally, using knowledge graph reasoning: constructing a fault graph; path similarity analysis; solution rule matching; generation of a suggested solution; optimizing the suggestion sequence. It can be understood that other methods can also be used to implement the generation process of fault handling suggestions, such as expert systems or deep learning methods, which are not limited here.

[0105] In some embodiments, the simulation system generates a test log containing operation events, execution time, and result status based on the actual response result; converts the actual response result into a multi-dimensional feature vector containing timestamps, function block identifiers, status values, and performance metric values according to the time series; generates a difference matrix containing deviation types and deviation degrees based on the multi-dimensional feature vector and the test verification expectation; extracts a set of abnormal points exceeding the preset deviation threshold based on the difference matrix, generates an abnormality mark, and integrates the abnormality mark into the test log.

[0106] Among them, the test log represents a data file recording the test execution process; the operation event refers to the key operation during the test; the multi-dimensional feature vector is used to represent the feature representation of time series data; the difference matrix represents the deviation description between the actual result and the expectation; the deviation type refers to different types of verification failures; the deviation degree is used to represent the severity of the verification failure; the set of abnormal points represents abnormal data points exceeding the threshold.

[0107] After the simulation system completes the test execution, it needs to perform result analysis. Specifically, the simulation system first generates a test log containing complete execution information based on the actual response result, converts the time series data into a standardized feature vector, generates a difference matrix by comparing with the verification expectation, analyzes the abnormal points exceeding the threshold in the matrix, generates an abnormality mark and integrates it into the test log to form a complete test result analysis report.

[0108] In some embodiments, the test result analysis can be implemented in various ways: Optionally, a time series analysis method is adopted: generating a time series log; feature vector conversion; difference calculation and analysis; abnormal point identification; result report generation. Optionally, a statistical analysis method is used: data preprocessing; statistical feature extraction; deviation pattern analysis; abnormal mark generation; log integration and output. It can be understood that other methods can also be used to implement the test result analysis process, such as machine learning or pattern recognition methods, which are not limited here.

[0109] S210. Use the fault features and test cases corresponding to the abnormality marks as new training data, and optimize the test case generation model based on the new training data.

[0110] Referring to step S106, the simulation system will optimize the test case generation model.

[0111] S211. Construct a fault feature knowledge graph and add the fault feature nodes in the new training data to the fault feature knowledge graph.

[0112] Among them, the fault feature knowledge graph represents a structured knowledge base describing fault features and their relationships; the fault feature node refers to the basic unit representing specific fault features in the graph; the new training data represents the fault information obtained from the current verification process.

[0113] After the simulation system obtains new fault data, it needs to update the knowledge base. Specifically, the simulation system first constructs a knowledge graph structure representing fault features and their relationships, transforms the newly discovered fault features into standardized node descriptions, determines the association relationships between nodes, and adds these new nodes to the existing knowledge graph to form a more complete fault knowledge base. In some embodiments, the construction and update of the fault feature knowledge graph can be achieved in various ways: Optionally, a structured modeling method is adopted: define the node architecture; extract feature attributes; establish a relationship model; integrate new nodes; verify the integrity of the graph. Optionally, an automated mining method is used: analyze fault data; identify feature patterns; construct node relationships; merge similar nodes; update the knowledge graph. It can be understood that other methods can also be used to implement the construction and update process of the knowledge graph, such as semi-automated annotation or expert rule definition, etc., which are not limited here.

[0114] S212. Calculate the association strength between each fault feature node in the fault feature knowledge graph based on the graph attention network, and determine a fault feature cluster with a correlation higher than a preset correlation threshold based on the association strength.

[0115] Among them, the graph attention network represents a deep learning model for processing graph-structured data; the association strength refers to the importance of the connection between nodes; the fault feature cluster represents a set of fault features with strong correlation; the preset correlation threshold is used to represent the standard value for determining strong correlation.

[0116] After the simulation system updates the knowledge graph, it needs to analyze the association relationships between features. Specifically, the simulation system uses the graph attention network to analyze the knowledge graph, calculates the association strength between each fault feature node, filters out strongly correlated feature nodes based on a preset correlation threshold, and organizes these nodes into a fault feature cluster to provide a basis for subsequent fault prediction.

[0117] In some embodiments, the calculation of the association strength and the determination of the feature cluster can be achieved in various ways: Optionally, based on a deep learning method: construct an attention model; train network parameters; calculate the association score; cluster related nodes; verify the effectiveness of the cluster. Optionally, a graph analysis algorithm is adopted: establish an adjacency matrix; calculate node similarity; determine the association weight; form a feature cluster; optimize the cluster structure. It can be understood that other methods can also be used to implement the association analysis process, such as probability graph models or community discovery, etc., which are not limited here.

[0118] It should be noted that the above steps will use the graph attention network model. During the training stage, the node features (fault descriptions, performance parameters, etc.) and edge relationships (fault associations, evolution paths, etc.) in the fault feature knowledge graph are input as training data; the model parameters are optimized by maximizing the attention weights between relevant nodes. The graph attention network model includes a graph structure encoding layer, an attention calculation layer, and a feature aggregation layer, and can learn the complex association relationships between nodes. By inputting the fault feature knowledge graph, the graph attention network model can calculate the association strength between each node and output high-correlation fault feature clusters for fault analysis and prediction.

[0119] S213. Use the historical verification data of the fault feature clusters as training data to generate a fault prediction model.

[0120] Among them, the historical verification data represents the historical fault records related to the fault feature clusters; the fault prediction model refers to a machine learning model used to predict potential faults; the training data is used to represent the data set required for model training.

[0121] After determining the fault feature clusters, the simulation system starts to build a prediction model. Specifically, the simulation system collects the historical verification data related to the fault feature clusters, preprocesses the data and performs feature engineering, selects a suitable machine learning algorithm to build a fault prediction model, optimizes the model parameters through the training data, and finally forms an intelligent model that can predict potential faults.

[0122] It should be noted that during the training stage of this fault prediction model, the historical verification data of the fault feature clusters (including the fault evolution process, performance change trends, etc.) are input as training data; the time and type of fault occurrence are used as the prediction targets, and the model is trained by optimizing the prediction accuracy. The fault prediction model adopts a time series prediction network structure and combines the attention mechanism, and can capture the time correlation of performance indicators and the fault development law. During use, by inputting the real-time monitored performance data, this fault prediction model can predict the type, occurrence probability, and expected time of potential faults for early warning.

[0123] In some embodiments, the generation of the fault prediction model can be achieved in various ways: Optionally, use the supervised learning method: prepare the training data; design the model structure; train the model parameters; verify the model effect; optimize the model performance. Optionally, adopt the ensemble learning method: build the base models; design the ensemble strategy; train the sub-models; combine the prediction results; evaluate the model accuracy. It can be understood that other methods can also be used to implement the generation process of the prediction model, such as semi-supervised learning or reinforcement learning, etc., which are not limited here.

[0124] S214. When a performance anomaly trend is detected during the simulation process, call the fault prediction model for early warning and fault location.

[0125] Among them, the performance anomaly trend represents the abnormal change pattern of the chip performance indicators; early warning means giving warning information before a failure occurs; fault location is used to represent the process of determining the location where the failure occurs.

[0126] During the operation of the simulation system, the chip performance is continuously monitored. Specifically, the simulation system analyzes the performance indicator data in real time. When an abnormal trend is detected, it immediately calls the fault prediction model for analysis, predicts the possible types and locations of faults, generates warning information, and provides preliminary fault location results to help the verification personnel take preventive measures in time.

[0127] In some embodiments, fault warning and location can be achieved in multiple ways: Optionally, based on the threshold monitoring method: collect real-time data; analyze the performance trend; predict the fault risk; locate the fault location; generate a warning report. Optionally, adopt the dynamic prediction method: construct a state vector; calculate the anomaly probability; predict the fault type; determine the fault range; output warning information. It can be understood that other methods can also be used to implement the fault warning and location process, such as pattern recognition or expert system methods, which are not limited here.

[0128] In the embodiments of the present application, due to the adoption of an intelligent verification method based on a machine learning-based use case generation model, a hierarchical monitoring framework, and a fault feature knowledge graph, the system can automatically learn historical verification experience, generate targeted test cases, monitor the chip performance in real time, predict and locate potential faults, effectively solve the problems of incomplete test case coverage, difficult fault location, and low verification efficiency in traditional verification methods, and thus improve the efficiency of the verification process. Through innovative technologies such as real-time data collection by the probe program, parallel verification execution on the distributed platform, and fault correlation analysis by the graph attention network, the system improves the verification efficiency, shortens the verification cycle, and improves the accuracy of fault prediction and location.

[0129] The following describes the simulation system in the embodiments of the present invention application from the perspective of hardware processing. Please refer to Figure 3 , which is a schematic structural diagram of an entity device of the simulation system in the embodiments of the present application.

[0130] It should be noted that Figure 3 The structure of the simulation system shown is only an example and should not impose any limitations on the functions and usage scopes of the embodiments of the present invention.

[0131] Such as Figure 3As shown, the simulation system includes a Central Processing Unit (CPU) 301, which can perform various appropriate actions and processes according to the program stored in the Read-Only Memory (ROM) 302 or the program loaded from the storage section 308 into the Random Access Memory (RAM) 303, such as executing the method described in the above embodiments. In the RAM 303, various programs and data required for system operation are also stored. The CPU 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An Input / Output (I / O) interface 305 is also connected to the bus 304.

[0132] The following components are connected to the I / O interface 305: an input section 306 including an audio input device, a button switch, etc.; an output section 307 including a Liquid Crystal Display (LCD), an audio output device, an indicator light, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. A removable medium 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 310 as needed so that a computer program read from it can be installed into the storage section 308 as needed.

[0133] Specifically, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network via the communication section 309, and / or installed from the removable medium 311. When the computer program is executed by the Central Processing Unit (CPU) 301, various functions defined in the present invention are executed.

[0134] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present invention, a computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. Among them, each block in the flowchart or block diagram may represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings.

[0136] Specifically, the simulation system of this embodiment includes a processor and a memory, and a computer program is stored on the memory. When the computer program is executed by the processor, the verification method of the chip simulation model provided in the above embodiment is implemented.

[0137] On the other hand, the present invention also provides a computer-readable storage medium, which may be included in the simulation system described in the above embodiment; or it may exist separately without being assembled into the simulation system. The above storage medium carries one or more computer programs, and when the one or more computer programs are executed by a processor of the simulation system, the simulation system implements the verification method of the chip simulation model provided in the above embodiment.

[0138] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present application.

[0139] As used in the foregoing embodiments, depending on the context, the term "when" may be interpreted to mean "if" or "after" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "when determining" or "if (the stated condition or event) is detected" may be interpreted to mean "if determining" or "in response to determining" or "when (the stated condition or event) is detected" or "in response to detecting (the stated condition or event)".

[0140] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the foregoing embodiments can be implemented. The processes can be completed by relevant hardware instructed by a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the foregoing method embodiments. The foregoing storage media include: various media such as ROM or random access memory RAM, magnetic disks, or optical discs that can store program codes.

Claims

1. A chip simulation model verification method, characterized in that: Applied to a simulation system, the method comprises: Obtain the simulation model and performance parameter indicators of the chip to be verified; Generate model training data based on historical performance indicators, corresponding historical use case sets and historical verification results, and perform model training based on the model training data to obtain a use case generation model; Input the performance parameter index into the use case generation model to obtain a test case set and test verification expectations; Execute multiple test cases in the test case set based on the simulation model, and record actual response results of the simulation model; Based on the actual response result and the test verification expectation, generate a test log, and determine an abnormal mark in the test log; The fault characteristics and test cases corresponding to the abnormal marks are used as new training data, and the use case generation model is optimized based on the new training data.

2. The method according to claim 1, characterized in that After the step of generating a test log based on the actual response result and the test verification expectation, and determining an abnormal mark in the test log, the method further includes: Determining an actual fault feature corresponding to the abnormal mark; Perform similarity matching between the actual fault feature and the historical fault feature in the historical use case set, determine the historical fault feature with the highest similarity and the corresponding historical verification result, and extract the historical fault cause and historical solution corresponding to the historical verification result; Based on the historical fault characteristics, the historical fault causes and the historical solutions, generate multiple fault handling suggestions; The plurality of fault handling suggestions are integrated according to the real-time performance data of the simulation model to generate a priority-ordered fault handling suggestion list.

3. The method according to claim 1, characterized in that The step of executing multiple test cases in the test case set based on the simulation model and recording actual response results of the simulation model specifically includes: Determine complexity values ​​of multiple test cases in the test case set, and prioritize the multiple test cases based on the complexity values ​​to obtain a test case queue; Real-time monitoring of resource utilization of each computing node in the distributed verification platform; Determine, based on the test case queue and the resource utilization, an allocation rule for the multiple test cases on the computing nodes, and perform task allocation based on the allocation rule; The actual response result of the simulation model on the computing node is recorded.

4. The method according to claim 1, characterized in that Before the step of obtaining the simulation model and performance parameter index of the chip to be verified, the method further includes: Determine chip characteristics including protocol specifications, architecture characteristics, and key performance parameters according to the type identification of the chip to be verified; Constructing a hierarchical module partitioning template according to the chip characteristics; the hierarchical levels include an interface layer, a control layer, a computing layer, and a storage layer; Based on the module division template, the functional modules of the chip to be verified are mapped to generate a monitoring point configuration table; the monitoring point configuration table includes signal types, timing requirements and verification rules at each level; A probe program adapted to the chip to be verified is generated according to the monitoring point configuration table; the probe program is used to collect performance indicator data and timing signal data of each monitoring point during simulation operation.

5. The method according to claim 4, characterized in that After the step of generating a probe program adapted to the chip to be verified according to the monitoring point configuration table, the method further includes: Based on the real-time data collected by the probe program, calculating the scores of multi-dimensional evaluation indicators including timing integrity, functional correctness, resource utilization and performance bottlenecks; According to the evaluation index score and the preset benchmark index, the corresponding abnormal function module is determined, and the state characteristics and data characteristics corresponding to the abnormal function module are extracted; Inputting the state feature and the data feature into an anomaly classification model to obtain an anomaly type and a confidence score; When the confidence score is higher than a preset confidence threshold, abnormal prompt information including the abnormal function module and the abnormal type is displayed.

6. The method according to claim 1, characterized in that After the step of using the fault features and test cases corresponding to the abnormal marks as new training data and optimizing the use case generation model based on the new training data, the method further includes: Constructing a fault feature knowledge graph, and adding the fault feature nodes in the newly added training data to the fault feature knowledge graph; Calculating the correlation strength between each fault feature node in the fault feature knowledge graph based on the graph attention network, and determining the fault feature cluster whose correlation is higher than a preset correlation threshold based on the correlation strength; Using the historical verification data of the fault feature cluster as training data, generating a fault prediction model; When abnormal performance trends are detected during the simulation process, the fault prediction model is called to perform early warning and fault location.

7. The method according to claim 1, characterized in that The step of generating a test log based on the actual response result and the test verification expectation, and determining an abnormal mark in the test log specifically includes: Generate a test log including operation events, execution time and result status according to the actual response result; Converting the actual response result into a multidimensional feature vector including a timestamp, a function block identifier, a state value, and a performance index value according to a time series; Based on the multidimensional feature vector and the test verification expectation, generating a difference matrix including deviation types and deviation degrees; Based on the difference matrix, a set of abnormal points exceeding a preset deviation threshold is extracted, an abnormal mark is generated, and the abnormal mark is integrated into the test log.

8. A simulation system, characterized in that: The simulation system includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to enable the simulation system to execute the method described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on a simulation system, the simulation system is caused to execute the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that When the computer program product is run on a simulation system, the simulation system is caused to execute the method according to any one of claims 1 to 7.

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