HBM chip with optimized heat dissipation structure

Abstract

The invention belongs to the field of chip packaging, and discloses an HBM chip with an optimized heat dissipation structure. The HBM chip sequentially comprises a substrate, a micro-bulge layer, a logic chip layer, a storage layer, a heat conduction layer and a heat dissipation layer from bottom to top, the storage layer is formed by stacking a plurality of storage chips from bottom to top; a heat optimization area is also arranged between the logic chip layer and the heat dissipation layer; the heat optimization area is made of a heat conduction material, the upper end of the heat optimization area is directly bonded with the heat dissipation layer, and the lower end of the heat optimization area is directly bonded with the logic chip layer and is in contact with the storage layer and the heat conduction layer. The heat optimization area directly connected with the logic chip layer and the heat dissipation layer is arranged between the logic chip layer and the heat dissipation layer, heat of the logic chip can be directly transmitted into the heat dissipation layer through the heat optimization heat dissipation area, heat dissipation in a more efficient mode is achieved, the storage performance is higher, and chip warping is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field related to chip packaging, and more specifically, relates to an HBM chip with an optimized heat dissipation structure. Background Art

[0002] Optimization of the heat dissipation structure is the core of improving the thermal management performance of high bandwidth memory (HBM) chips. In order to effectively reduce the chip temperature, it is necessary to first consider how to improve the heat conduction efficiency by optimizing the chip structure itself.

[0003] Research shows that in a three-dimensional stacked structure, by designing a reasonable heat channel, it can help heat conduct more effectively from the inside of the chip to the external heat dissipation system. A common solution is to add microstructures or thermal conduction layers on the chip surface, and use these structures to enhance the directivity of heat, so that heat can propagate along a specific path and avoid heat accumulation inside the chip. For example, a heat dissipation structure of an HBM device is proposed in Patent CN119340286A. By adding TTSV vias above the heat source and connecting them to the topmost thermal conduction layer through multiple storage chips, heat is effectively transferred to the surface.

[0004] In addition, with the progress of materials science, using new high thermal conductivity materials as chip heat dissipation layers or interface materials is also an important trend in thermal management technology in recent years. For example, materials with ultra-high thermal conductivity such as graphene and metal matrix composites have been applied in some high-end chips, which can significantly improve the heat conduction efficiency and help the chips dissipate heat quickly.

[0005] At the same time, the thermal management solution is not only limited to structural design, but also includes the selection and layout optimization of thermal interface materials (TIM). Thermal interface materials play a role in connecting and conducting heat between the chip and the radiator, and their performance directly affects the efficiency of the entire heat dissipation system. In HBM chips, using efficient thermal interface materials can minimize the thermal resistance and improve the heat conduction efficiency. Common thermal interface materials include metal-filled polymers, metal thin films, and graphite sheets, etc. They have good thermal conductivity and can effectively fill the tiny gaps between the chip and the heat dissipation system, improving the overall heat dissipation effect.

[0006] However, in the above-mentioned technical solutions, due to the bonding layer with a low thermal conductivity between multiple storage chips, heat cannot be effectively conducted, and because each layer has a complex wiring layer, adding TTSV and microchannel structures to these chips has extremely high process requirements. Therefore, it is still necessary to explore the thermal optimization solution of HBM chips to meet the heat dissipation requirements of high power density chips.

[0007] Above the logic chip with the highest heat generation, a thermal optimization area is demarcated. By adding high - thermal - conductivity materials and heat - conducting structures such as TTSV and microchannels in this area, the heat generated by the logic chip can directly reach the chip surface through this area. Summary of the Invention

[0008] In view of the above - mentioned defects or improvement requirements of the prior art, the present invention provides an HBM chip with an optimized heat - dissipation structure. The purpose is to directly transfer the heat generated by the logic chip to the chip surface through a thermal optimization area directly connected to both the logic chip layer and the heat - dissipation layer, thereby solving the technical problem of uneven internal heat distribution, that is, poor heat dissipation, in existing HBM chips.

[0009] To achieve the above - mentioned purpose, according to the first aspect of the present invention, an HBM chip with an optimized heat - dissipation structure is provided, which sequentially includes from bottom to top: a substrate, a micro - bump layer, a logic chip layer, a storage layer, a heat - conducting layer, and a heat - dissipation layer;

[0010] The storage layer is formed by stacking multiple storage chips from bottom to top; a thermal optimization area is also provided between the logic chip layer and the heat - dissipation layer; the thermal optimization area is made of a heat - conducting material, its upper end is directly bonded to the heat - dissipation layer, its lower end is directly bonded to the logic chip layer, and it is in contact with the storage layer and the heat - conducting layer.

[0011] Preferably, the thermal optimization area is arranged in a surrounding manner around the outer periphery of the storage layer and the heat - conducting layer.

[0012] Preferably, a heat - dissipation structure is provided in the thermal optimization area, which is vertically connected between the logic chip layer and the heat - dissipation layer.

[0013] Preferably, the heat - dissipation structure is a thermal through - silicon via or a microchannel structure.

[0014] Preferably, multiple power - consumption blocks in the logic chip layer are arranged in positions from far to near the thermal optimization area in ascending order of power consumption.

[0015] Preferably, multiple power - consumption blocks in the storage chips are arranged in positions from far to near the thermal optimization area in ascending order of power consumption.

[0016] Preferably, a thermal interface material layer is further included in the HBM chip, which is arranged between the storage layer and the heat - conducting layer.

[0017] Preferably, the layers in the HBM chip are connected by Cu / SiO 2 hybrid bonding.

[0018] Preferably, the heat-conducting material of the heat optimization region is selected from silicon materials, hexagonal boron nitride or diamond.

[0019] Preferably, the material of the heat dissipation layer is aluminum, copper, aluminum alloy or copper alloy, and the material of the heat conduction layer is copper, aluminum, silicon or aluminum nitride ceramic material.

[0020] Generally speaking, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following technical advantages:

[0021] 1. The HBM chip with an optimized heat dissipation structure provided by the present invention can directly transfer the heat generated by the logic chip layer to the chip surface through the heat optimization region directly connected to both of them by arranging a heat optimization region between the logic chip layer and the heat dissipation layer, so as to achieve more efficient heat dissipation, make the internal temperature distribution of the chip more uniform, and have greater storage performance and reduce chip warping. Specifically, the upper and lower ends of the heat optimization region of the present invention are directly connected to the logic chip layer and the heat dissipation layer respectively, so that the heat of the logic chip that mainly generates heat can reach the chip surface through this region, without the need to transfer the heat to the surface through multiple storage chips like the traditional structure; at the same time, due to the improvement of heat dissipation performance, the internal temperature distribution is more uniform, the maximum junction temperature is significantly reduced, the difference between the maximum junction temperature and the minimum junction temperature is smaller, and more storage chip layers can be stacked, which can achieve greater storage performance and reduce chip warping.

[0022] 2. Preferably, the heat optimization region is in contact with the storage layer and the heat conduction layer, and is arranged in a circumferential manner with the central axis in the stacking direction as the reference. The surface area of the logic chip layer is larger than the storage layer and the heat conduction layer above it. A heat optimization region is arranged between the logic chip layer and the heat dissipation layer to more fully and comprehensively direct the heat generated by each layer in the HBM chip to the uppermost surface of the HBM chip through heat optimization.

[0023] 3. Preferably, a microchannel structure or a thermal vias is also arranged in the heat optimization region, which further helps to export heat through the coolant or heat-conducting metal material filled inside, improving the system stability and reliability.

[0024] 4. On the basis of the above solution, by optimizing the layout of the power consumption blocks in the logic chip layer and / or the storage chip, that is, arranging the power consumption blocks with higher power consumption in the logic chip layer and / or the storage chip closer to the heat optimization region, to further optimize the thermal management solution for using the heat optimization region to dissipate heat in each module.

[0025] 5. Preferably, the HBM chip further includes a thermal interface material layer disposed between the storage layer and the thermal layer. By filling the tiny gaps between the chip and the radiator, it helps to conduct heat from the chip to the heat dissipation layer more effectively, thereby improving the heat dissipation effect. And this layer also has electrical insulation properties to prevent electrical short circuits between the chip and the radiator.

[0026] 6. Preferably, the layers in the HBM chip of the present invention are bonded together by Cu / SiO 2 hybrid bonding, that is, a bonding technology that combines metallic copper and silicon dioxide. It is mainly used in the packaging of three-dimensional chips. Since copper provides excellent electrical conductivity and silicon oxide acts as an insulating layer, the combination of the two achieves high-density electrical connection and thermal management, ensuring the performance and stability of the chip. In particular, the combination of microchannel cooling and Cu / SiO 2 hybrid bonding can further improve the thermal management ability of the chip and meet the heat dissipation requirements of high-power density chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic cross-sectional view in the vertical direction of an HBM chip with an optimized heat dissipation structure according to an example of the present invention;

[0028] Figure 2 is a schematic cross-sectional view in the vertical direction of another HBM chip with an optimized heat dissipation structure according to an example of the present invention;

[0029] Figure 3 is a schematic diagram of the power consumption division area of a logic chip according to an example of the present invention;

[0030] Figure 4 is a power consumption distribution diagram of the logic chip according to an example of the present invention;

[0031] Figure 5 is a power consumption distribution diagram of the storage chip according to an example of the present invention;

[0032] Figure 6 is a thermal distribution diagram of the logic chips in the examples and comparative examples of the present invention, where Figure 6 (a) is the thermal distribution diagram of Example 1, (b) is the thermal distribution diagram of Example 2, (c) is the thermal distribution diagram of Comparative Example 1, and (d) is the thermal distribution diagram of Example 3.

[0033] In all the drawings, the same reference numerals are used to represent the same structures, where:

[0034] 1 - Heat dissipation layer, 2 - Thermal conduction layer, 3 - Power consumption block in the storage chip, 4 - Storage chip, 5 - Hybrid bonding layer, 6 - Through - silicon via, 7 - Logic chip layer, 8 - High - power consumption block in the logic chip, 9 - Low - power consumption block in the logic chip, 10 - Thermal optimization area, 11 - Micro - bump layer, 12 - Substrate, 13 - Thermal conductive material, 14 - Heat dissipation structure, A - Power consumption block with a power density of 500000W / m 2 of the power consumption block, B - Power consumption block with a power density of 400000W / m 2 of the power consumption block, C - Power consumption block with a power density of 300000W / m 2 of the power consumption block, D - Power consumption block with a power density of 500000W / m 2 of the power consumption block, E - Power consumption block with a power density of 400000W / m 2 of the power consumption block, F - Power consumption block with a power density of 50000W / m 2 of the power consumption block. Specific embodiments

[0035] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] To achieve the above objectives, in a first aspect, the present invention provides an HBM with an optimized heat dissipation structure, which includes, from bottom to top: a substrate 12, a micro - bump layer (Micro - Bump layer) 11, a logic chip layer (Logic chip layer) 7, a storage layer (Memory - Stack layer) formed by stacking multiple storage chips 4, a thermal conduction layer (IHS layer) 2, a heat dissipation layer (Heat Sink layer) 1, and a thermal optimization area 10; the thermal optimization area 10 is arranged along the stacking direction on the side of the storage layer and the thermal conduction layer 2, and its upper end is bonded to the lower surface of the heat dissipation layer 1 and the upper surface of the logic chip layer 7; and the thermal optimization area is made of a thermal conductive material 13.

[0037] The material of the heat dissipation layer 1 is aluminum, copper, aluminum alloy or copper alloy; the material of the thermal conduction layer 2 is metal copper, aluminum, or silicon or aluminum nitride ceramic material; the thermal conductive material in the thermal optimization area 10 is silicon material (including thermal conductive silicone grease, silicon - based composite materials, etc.), hexagonal boron nitride, diamond, etc. A thermal optimization area 10 is arranged between the logic chip layer 7 where power consumption mainly occurs and the heat dissipation layer 1, for directly guiding the heat of the logic chip layer 7 where heat is mainly generated in the HBM chip to the uppermost surface of the HBM chip through the thermal optimization area 10.

[0038] The logic chip layer 7 and the memory chip 4 successively include a wiring layer, a device layer, and through-silicon vias (TSVs) 6 from bottom to top. The TSVs are used to achieve electrical interconnection between chip layers, providing a high-speed and low-latency signal transmission channel by drilling holes in the silicon chip and filling them with conductive materials.

[0039] In some embodiments, the thermal optimization region 10 is in contact with the memory layer and the thermal conduction layer 2 and is arranged in a surrounding manner with respect to the central axis in the stacking direction, as Figure 1 shown in the cross-sectional schematic diagram of the chip. The surface area of the logic chip layer is larger than that of the memory layer and the thermal conduction layer 2 above it. A thermal optimization region 10 is directly provided between the peripheries of the memory layer and the thermal conduction layer 2 in the stacking direction, between the logic chip layer 7 and the heat dissipation layer 1, so as to more fully and comprehensively direct the heat generated by each layer in the HBM chip to the uppermost surface of the HBM chip through the thermal optimization region 10.

[0040] In some embodiments, as Figure 2 shown, a heat dissipation structure 14 vertically connected between the logic chip layer 7 and the heat dissipation layer 1 is further provided in the thermal optimization region, and a thermal conductive material 13 is filled in the gaps in the thermal optimization region.

[0041] Furthermore, the heat dissipation structure 14 is a microchannel structure or a thermal through-silicon via (TTSV). The microchannel structure is a microchannel prepared according to the microchannel cooling technology, specifically by designing tiny cooling channels inside or on the surface of the chip and circulating a liquid coolant to take away the heat generated inside the chip. The thermal through-silicon via provides an efficient heat conduction path by drilling holes in the silicon chip and filling them with a thermally conductive metal material (such as copper or tungsten), helping to conduct the heat out, preventing the chip from overheating, and improving the system stability and reliability.

[0042] In some embodiments, the power consumption blocks of the logic chip layer are arranged in the direction towards the thermal optimization region in ascending order of power consumption.

[0043] An example is that the surface area of a logic chip layer is larger than that of the memory layer above it. By placing the high-heat-generation power consumption blocks in the logic chip outside the area of the memory chip and placing the power consumption blocks with lower heat generation in the logic chip in the overlapping area with the memory layer, it is possible to directly guide the heat generated by the high-heat-generation power consumption blocks in the logic chip to the top radiator of the HBM without passing through the memory layer through the thermal optimization region.

[0044] Exemplarily, when the thermal optimization region is arranged in a surrounding manner outside the memory layer and the thermal conduction layer, at this time, the power consumption blocks of the logic chip are arranged in the direction towards the thermal optimization region in ascending order of power consumption, specifically manifested as the power consumption blocks of the logic chip diverging outward from the center on the power consumption block arrangement surface of the logic chip in ascending order of power consumption.

[0045] To further prevent heat from accumulating within the chip, the module layout method in the above-mentioned logic chip is also applicable to the memory chips in the memory layer.

[0046] In some embodiments, the layers in the HBM chip are connected by means such as microbump bonding, thermocompression bonding, hybrid bonding, etc. Preferably, the layers in the HBM chip in the present invention are connected by Cu / SiO 2 hybrid bonding, which is a bonding technology that combines metallic copper and silicon dioxide. It is mainly used in the packaging of three-dimensional chips. Since copper provides excellent electrical conductivity and silicon oxide serves as an insulating layer, the combination of the two enables high-density electrical connection and thermal management, ensuring chip performance and stability. In particular, the combination of microchannel cooling and Cu / SiO 2 hybrid bonding can further enhance the thermal management ability of the chip and meet the heat dissipation requirements of high-power density chips.

[0047] In some embodiments, the heat-conducting material in the heat-optimized region involved in the present invention is a high-thermal-conductivity material, including silicon material (Dummy-Si), hexagonal boron nitride (h-BN), diamond, etc.

[0048] In some embodiments, a thermal interface material layer is further provided between the memory layer and the heat-conducting layer.

[0049] In some embodiments, the HBM chip further includes a packaging layer disposed in the gap between the substrate 12 and the heat dissipation layer.

[0050] It should be noted that the number of stacked memory chips in the memory layer can be multiple, as long as the maximum internal junction temperature does not exceed the maximum junction temperature that the chip can tolerate. Of course, the more memory chips there are, the higher the storage performance and data parallel processing ability. With the optimization of the heat dissipation structure of the basic invention, the number of memory chips involved in the present invention can be as high as 33 layers. Specific details will be described in detail in the following embodiments.

[0051] According to the HBM chip with an optimized heat dissipation structure according to any one of the above embodiments, the following is an example of a method for manufacturing an HBM chip with an optimized heat dissipation structure, including the following steps:

[0052] S1: First, fabricate memory chips and logic chips on a wafer through processes such as lithography, deposition, and etching. Prepare TSV holes on the chips, and connect the memory chips and logic chips to each other through hybrid bonding technology by depositing a bonding layer on the chip surface;

[0053] S2: Process the silicon substrate through processes such as photolithography, etching, and metal deposition. Then, prepare a micro-bump layer on the surface of the logic chip and the surface of the silicon substrate through deposition and photolithography processes (the commonly used material is a tin-based alloy (such as SnAg, SnCu, or Cu)), and connect the silicon substrate to the stacked chips through a thermocompression bonding technique;

[0054] S3: Deposit a high thermal conductivity material (such as silicon material, hexagonal boron nitride, and diamond, etc.) in the thermal optimization area by deposition;

[0055] S4: Apply a layer of thermal paste as the TIM layer above the chip, then add the HIS layer above it by thermocompression bonding, and finally add a heat dissipation layer above it by soldering. Finally, use a resin material to fill the gap between the silicon substrate and the heat dissipation layer through molding to fill the voids in the chip.

[0056] To further illustrate a thermal management method for an optimized structure of HBM chip heat dissipation based on Cu / SiO 2 bonding, the following will be described in detail with specific embodiments:

[0057] Taking the equivalent HBM chip model as an example, the chip structure includes a substrate, a micro-bump layer, a logic chip layer, a memory layer, a thermal interface material layer, a thermal conduction layer, and a heat dissipation layer from bottom to top.

[0058] The present invention will be introduced in detail below. In the present invention, by expanding the area of the Logic chip and performing thermal optimization on the area between the heat generation and power consumption block of the Logic layer and the Heat Sink layer, the maximum junction temperature inside the chip is significantly reduced, the stacking layer number of the Memory chip can be increased, and the temperature distribution of the area can be made more uniform.

[0059] The following are specific embodiments:

[0060] Example 1:

[0061] In this embodiment, after expanding the area of the logic chip, the obtained is as Figure 1The schematic diagram of the device structure shown includes, from bottom to top: a substrate (including silicon dioxide material and copper material, with anisotropic equivalent thermal conductivity, where the equivalent thermal conductivity in the horizontal direction is 10 W / mK and the equivalent thermal conductivity in the vertical direction is 2 W / mK), a micro-bump layer (including tin-silver alloy and epoxy resin material, with an equivalent thermal conductivity of 4 W / mK in the horizontal direction and 194 W / mK in the vertical direction), a logic chip layer (mainly silicon material, with a thermal conductivity of 150 W / mK), a memory layer formed by stacking 9 memory chips (mainly silicon material, with a thermal conductivity of 150 W / mK), a thermal interface material layer (composed of metal oxide thermal paste, including alumina and zinc oxide, with a thermal conductivity of 8 W / mK), a heat conduction layer (using copper metal, with a thermal conductivity of 400 W / mK), and a heat dissipation layer (using aluminum material, with a thermal conductivity of 235 W / mK), as well as a heat optimization area bonded between the heat dissipation layer and the logic chip layer; where the areas of the substrate and the heat dissipation layer are 20 mm × 20 mm, the areas of the micro-bump layer and the logic chip layer are 15 mm × 15 mm, and the areas of the remaining layers are all 10 mm × 10 mm. In this embodiment, the area between the heat generation and power consumption block of the logic chip layer and the heat dissipation layer is thermally optimized by constructing a material in the heat optimization area (the heat optimization area uses hexagonal boron nitride material, with a thermal conductivity of 390 W / mK).

[0062] Example 2:

[0063] In this embodiment, after expanding the area of the logic chip, the schematic diagram of the device structure shown in Figure 2 is obtained. The areas of each layer are the same as those in Example 1, where 14 is a micro-channel hole (deionized water is used in the hole, the cross-sectional area of the micro-channel hole is 30 um × 60 um, the hole pitch is 120 um, the flow rate is 3.5 m / s, and the thermal conductivity of this material is 0.606 W / mK). In this embodiment, the area between the heat generation and power consumption block of the logic chip layer and the heat dissipation layer is thermally optimized by adding a micro-channel structure to the heat optimization area on the basis of Example 1.

[0064] Example 3:

[0065] This embodiment is based on Example 2, only increasing the number of stacked memory chips to 30 layers, with the thermal optimization scheme remaining unchanged, and observing whether the maximum junction temperature inside the chip will exceed 85°C that the chip can tolerate.

[0066] Comparative Example 1:

[0067] The device structure of the comparative example is the same as that of Example 1. The main difference is that the area of the logic chip is not expanded, and the area of the logic chip is the same as that of the memory chip (both are 15 mm × 15 mm), and the two chips completely overlap in the vertical direction.

[0068] In addition, in the structures of Example 1, Example 2, and Comparative Example 1, the thicknesses of each layer are as follows: the substrate thickness is 900 um, the micro-protrusion layer thickness is 40 um, the logic chip layer thickness is 96 um (where the wiring layer thickness is 16 um, the TSV thickness is 80 um, and the device layer is equivalent to a two-dimensional layer with no thickness), the hybrid bonding layer thickness is 10 um, the memory chip layer thickness is 42 um (where the wiring layer thickness is 2 um, the TSV thickness is 40 um, and the device layer is equivalent to a two-dimensional layer with no thickness), the TIM layer thickness is 30 um, the IHS layer thickness is 1000 um, and the heat dissipation layer thickness is 7000 um. The power consumption blocks in the logic chip layer are distributed as Figure 3 shown, where the power density in area A is 500000 W / m 2 , where the power density in area B is 400000 W / m 2 , where the power density in area C is 300000 W / m 2 , where the power density in area D is 500000 W / m 2 , where the power density in area E is 400000 W / m 2 , the power density of the power consumption blocks in the memory chip is 50000 W / m 2 , and the power consumption distribution is as Figure 4 shown in area F in Figure 1 (4 in

[0069] ). The TSV, hybrid bonding layer, wiring layer, and substrate are modeled using an equivalent model.

[0069] Then, taking Example 1, Example 2, Example 3, and Comparative Example as examples, the performance tests are as follows:

[0070] (1) In terms of heat distribution:

[0071] For Example 1, Example 2, Example 3, and Comparative Example, modeling is performed using Comsol software, and simulation is carried out through the solid heat transfer module to obtain the surface heat distribution diagram of their logic chips, as Figure 6As shown, the heat distribution in Example 1 is the most uniform. The heat distribution in the comparative example is concentrated at all power consumption blocks in the logic chip, indicating that the internal heat cannot be effectively conducted out. Benefiting from this structure, Example 1 and Example 2 add a high thermal conductivity material heat optimization area, a microchannel structure, and a heat conduction bridge in the heat optimization area, enabling the heat in the logic chip to be directly conducted to the heat dissipation layer through this area for heat dissipation, with higher heat dissipation efficiency. It can be seen from Example 3 that even if the number of stacked memory chips far exceeds the current number of HBM3, the maximum junction temperature inside does not exceed the maximum junction temperature that the chip can tolerate. Moreover, compared with the comparative example, the temperature distributions of Example 1, Example 2, and Example 3 are more uniform. The heat is mainly generated by the stacking of memory chips, and the heat generated is much more optimized compared with the comparative example, and there will be no such serious phenomenon of heat concentration as in the comparative example, greatly optimizing the internal heat dissipation performance of the chip, making the heat more uniform to achieve the purpose of reducing chip warping.

[0072] (2) In terms of the maximum and minimum junction temperatures:

[0073] Similarly, the steady-state analysis can be carried out through the solid heat transfer module of the COMSOL software to obtain the maximum and minimum junction temperature values of Example 1, Example 2, and the comparative example. The highest junction temperature of the comparative example is 72.723 °C, the highest junction temperature of Example 1 is 37.289 °C, and the highest junction temperature of Example 2 is 69.574 °C. The maximum junction temperature of Example 1 is reduced by 48.724% compared with the comparative example, and the maximum junction temperature of Example 2 is reduced by 4.331% compared with the comparative example. Moreover, the minimum junction temperatures of Example 2 and the comparative example are almost the same. The minimum junction temperature of Example 1 is as low as 19.636 °C. It can be seen that the difference between the maximum and minimum junction temperatures of Example 1 and Example 2 is smaller than that of the comparative example. A smaller junction temperature difference represents a more uniform heat distribution.

[0074] And the maximum junction temperature of the chip is related to the maximum number of stackable memory chips. If the maximum tolerable temperature of the HBM chip is 85 °C, and it is found through thermal simulation that the temperature inside the chip increases by 2 °C for each additional memory chip, then the maximum number of stackable layers of the comparative example is 15 layers, the maximum number of stackable layers of Example 1 is 33 layers, and the maximum number of stackable layers of Example 2 is 17 layers. A larger number of stacked memory chips represents higher storage performance. The current most advanced HBM3 can reach 16 layers in terms of the number of stacked layers. Example 3 proves that by adopting this heat optimization structure and scheme, even when the number of stacked layers is as high as 30 layers, it will not exceed the maximum junction temperature that the chip can tolerate.

[0075] Table 1: Comparison of device performance with different oxidation treatment times

[0076]

[0077] In addition, it should be noted that the above embodiments are only examples, and each parameter condition can be flexibly adjusted according to the actual situation or the existing technology.

[0078] In summary, the present invention studies the influence of different thermal optimization schemes in the thermal optimization area on the chip heat dissipation based on a new structure, and compares it with the chip without structural optimization, proving that the new structure can be more convenient for thermal optimization and improve the heat dissipation performance. It is mainly reflected in that the temperature distribution inside the chip is more uniform, the maximum junction temperature is significantly reduced, the difference between the maximum junction temperature and the minimum junction temperature is smaller, the number of stackable memory chips is more, a larger storage performance is achieved, and the chip warping is reduced.

[0079] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the present invention and its equivalent technologies, the present invention also intends to include these changes and modifications. The above-described embodiments are only preferred embodiments given to fully illustrate the present invention, and the scope of protection is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are within the scope of protection of the present invention.

Claims

1. An HBM chip with an optimized heat dissipation structure, characterized in that: The device comprises, from bottom to top, a substrate (12), a micro-convex layer (11), a logic chip layer (7), a storage layer, a heat-conducting layer (2) and a heat-dissipating layer (1); The storage layer is formed by stacking a plurality of storage chips (4) from bottom to top; a thermal optimization zone (10) is also provided between the logic chip layer (7) and the heat dissipation layer (1); the thermal optimization zone (10) is made of a thermally conductive material, the upper end of which is directly bonded to the heat dissipation layer (1), the lower end of which is directly bonded to the logic chip layer (7), and the thermal optimization zone (10) is in contact with the storage layer and the thermally conductive layer (2).

2. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The thermal optimization zone (10) is arranged around the storage layer and the outer periphery of the heat conducting layer (2).

3. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: A heat dissipation structure (14) is provided in the thermal optimization area (10) and is vertically connected between the logic chip layer (7) and the heat dissipation layer (1).

4. The HBM chip with optimized heat dissipation structure according to claim 3, characterized in that: The heat dissipation structure (14) is a thermal through silicon via or a microchannel structure.

5. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The plurality of power consumption blocks in the logic chip layer (7) are arranged in order from low to high power consumption and in positions from far to near to the thermal optimization area (10).

6. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The plurality of power consumption blocks in the storage chip (4) are arranged in order from low to high power consumption and in positions from far to near to the thermal optimization area (10).

7. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The HBM chip also comprises a thermal interface material layer, which is arranged between the storage layer and the heat conducting layer (2).

8. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The layers in the HBM chip are connected by Cu / SiO2 mixed bonding.

9. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The heat-conducting material of the heat-optimized zone (10) is selected from silicon material, hexagonal boron nitride or diamond.

10. The HBM chip with optimized heat dissipation structure according to claim 1, characterized in that: The material of the heat dissipation layer (1) is aluminum, copper, aluminum alloy or copper alloy, and the material of the heat conduction layer (2) is copper, aluminum, silicon or aluminum nitride ceramic material.

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