Driving control circuit with dead time control and voltage change rate interference resistance

Abstract

The invention relates to the field of integrated circuits, in particular to a drive control circuit with dead-time control and voltage change rate interference resistance, which comprises a logic circuit, a high-side drive circuit and a low-side drive circuit, and is characterized in that the logic circuit is used for processing input high-low-side PWM (Pulse Width Modulation) control signals and high-low-side logic signals fed back in the circuit; interlocking between high and low side signals is realized; the high-side driving circuit is used for realizing level shift from a low-voltage logic signal to high-voltage driving, generating dead time and inhibiting anti-voltage change rate interference generated when a low-side power tube is conducted; the low-side driving circuit is used for generating dead time and suppressing anti-voltage change rate interference generated when the high-side power tube is conducted; the drive control circuit designed by the invention has the capabilities of dead time control and voltage change rate interference resistance, and the integration level of the circuit is improved while the reliability of the circuit is ensured.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and particularly relates to a drive control circuit with both dead time control and anti-dV / dt interference. Background Art

[0002] With the rapid development of electronic technology, drive circuits are widely used in power electronic systems such as half-bridge / full-bridge inverters, motor drive circuits, and DC-DC converters. The drive control circuit is a key unit circuit of the drive circuit in the power electronic system, and dead time control and dV / dt noise crosstalk have always been hot topics in this technical field. In power conversion circuits such as half-bridges and full-bridges, in order to prevent the power devices on the upper and lower bridge arms (such as insulated gate bipolar transistors, metal-oxide-semiconductor field effect transistors) from conducting simultaneously due to differences in switching speed, signal transmission delay, etc., resulting in short-circuit damage to the devices, a time interval, that is, the dead time, is set when the upper and lower transistors switch states. The dV / dt noise crosstalk problem refers to the phenomenon that noise generated due to too high a dV / dt interferes with other circuit parts or signal transmission, which may cause the upper and lower two tubes of the half-bridge to conduct directly and cause damage in the half-bridge power conversion circuit.

[0003] Existing dead time control methods include an off-chip adjustable dead time control circuit and a self-adjusting dead time drive circuit; for anti-dV / dt noise interference, traditional circuit structures often use RC filtering to eliminate noise or design an equivalent circuit with an adaptive structure.

[0004] Existing dead time control circuits and anti-dV / dt interference are both processed separately through two modules, resulting in low integration. Summary of the Invention

[0005] In view of this, the present invention discloses a drive control circuit with both dead time control and anti-dV / dt interference to solve the above problems; the drive control circuit with both dead time control and anti-dV / dt interference proposed by the present invention includes: a logic circuit, a high-side drive circuit, and a low-side drive circuit; wherein the logic circuit is used to process the input high and low side PWM control signals and the high and low side logic signals fed back in the circuit to achieve interlocking between the high and low side signals; the high-side drive circuit is used to achieve level shift from low-voltage logic signals to high-voltage drive, generate dead time, and suppress anti-dV / dt interference generated when the low-side power transistor conducts; the low-side drive circuit is used to generate dead time and suppress anti-dV / dt interference generated when the high-side power transistor conducts.

[0006] The drive control circuit designed by the present invention has both the ability of dead time control and anti-dV / dt interference, improving the integration of the circuit while ensuring the reliability of the circuit. Brief Description of the Drawings

[0007] Figure 1 Schematic diagram of the drive control circuit with dead time control and anti-dV / dt interference in the present invention;

[0008] Figure 2 Topological structure diagram of the logic circuit in the present invention;

[0009] Figure 3 Waveform diagram of the logic circuit in the present invention;

[0010] Figure 4 Circuit diagram of the high-side drive circuit in the present invention;

[0011] Figure 5 Waveform diagram of the high-side drive circuit in the present invention;

[0012] Figure 6 Circuit diagram of the low-side drive circuit in the present invention;

[0013] Figure 7 Waveform diagram of the low-side drive circuit in the present invention;

[0014] Among them, point A represents the drain of MP5, point B represents the drain of MP12, point C represents the drain of MP2, point D represents the drain of MP4, point E represents the drain of MP7, point F represents the drain of MP9, point G represents the drain of MP11, and point H represents the drain of MP13. Detailed implementation manners

[0015] In order to make the objectives, technical solutions, features, and advantages of the present invention clearer and more understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0016] The drive control circuit with dead time control and anti-dV / dt interference in this embodiment is as Figure 1 shown, and includes: a logic circuit, a high-side drive circuit, and a low-side drive circuit. When the drive control circuit works, it is connected to an external power supply VS, internal power supplies V0 and VINT0, and an external circuit.

[0017] Furthermore, the logic circuit is used to obtain high- and low-side PWM control signals and process the high- and low-side logic signals fed back in the circuit to achieve interlocking between the high- and low-side signals.

[0018] Specifically, as Figure 2As shown, the logic circuit includes 10 ports, namely PWM_H, PWM_L, H_DET, L_DET, H_A1N, H_A0N, H_A1, H_A0, L_A1, and L_A0. Among them, PWM_H and PWM_L serve as external input port 1 and external input port 2 of the drive control circuit respectively. H_A1N, H_A0N, H_A1, H_A0, and H_DET are connected to the high-side drive circuit, and L_A1, L_A0, and L_DET are connected to the low-side drive circuit.

[0019] Furthermore, the logic circuit includes: two AND gates AND1 to AND2, five inverters INV1 to INV5, and two NOR gates NOR1 to NOR2. Among them, PWM_H is connected to the lower input terminal of AND1; PWM_L is connected to the lower input terminal of AND2; H_DET is connected to the input terminal of INV1 and the upper input terminal of AND2 respectively; L_DET is connected to the input terminal of INV2 and the upper input terminal of AND1 respectively; the output terminal of INV1 is connected to the upper input terminal of NOR1; the output terminal of AND1 is connected to the lower input terminal of NOR1, the input terminal of INV4, and H_A0N respectively; the output terminal of INV2 is connected to the upper input terminal of NOR2; the output terminal of AND2 is connected to the lower input terminal of NOR2 and L_A0 respectively; the output terminal of NOR1 is connected to the input terminal of INV3 and H_A1 respectively; the output terminal of NOR2 is connected to the input terminal of INV5; the output terminal of INV3 is connected to H_A1N; the output terminal of INV4 is connected to H_A0; the output terminal of INV5 is connected to L_A1.

[0020] Among them, AND1 and AND2 receive input signals from PWM_H and PWM_L respectively; INV1, INV2, AND1, and AND2 receive signals from H_DET and L_DET respectively; after PWM_H and L_DET are ANDed, the H_A0N signal is obtained, and after being inverted by INV4, the H_A0 signal is obtained; the output of AND1 and H_DET inverted by INV1 are NORed to obtain the H_A1 signal, and after being inverted by INV3, the H_A1N signal is obtained; after PWM_L and H_DET are ANDed, the L_A0 signal is obtained; the output of AND2 and L_DET inverted by INV2 are NORed, and then after being inverted by INV5, the L_A1 signal is obtained.

[0021] Furthermore, the high-side drive circuit is used to achieve the level shift from low-voltage logic signals to high-voltage drive, the generation of dead time, and the anti-di / dt interference when the low-side power transistor conducts, and also includes the port H_DRV, which serves as external output port 1 of the drive control circuit.

[0022] Specifically, as Figure 4As shown, the high-side drive circuit includes seven PMOS transistors MP1 to MP7, five NMOS transistors MN1 to MN5, six Zener diodes Z1 to Z6, eight inverters INV6 to INV13, four current sources I1 to I4, and two capacitors C1 and C2. Among them, H_A1N is connected to the gate of MN1. The source of MN1 is respectively connected to the source of MN2 and the input terminal of I1. The output terminal of I1 is grounded. The drain of MN1 is respectively connected to the gate of MP2, the gate of MP1, and the drain of MP1. The source of MP1 is respectively connected to VS, the source of MP2, and the negative terminal of Z1. The drain of MP2 is respectively connected to the drain of MN2, the positive terminal of Z1, and the input terminal of INV6. The gate of MN2 is connected to H_A1. The output terminal of INV6 is connected to the input terminal of INV7. The output terminal of INV7 is connected to the gate of MP6. The source of MP6 is connected to VS. H_A0 is connected to the gate of MN3. The source of MN3 is respectively connected to the source of MN4 and the input terminal of I2. The output terminal of I2 is grounded. The drain of MN3 is respectively connected to the gate of MP4, the drain of MP3, and the gate of MP3. The source of MP3 is respectively connected to VS, the source of MP4, and the negative terminal of Z2. The drain of MP4 is respectively connected to the drain of MN4, the positive terminal of Z2, and the input terminal of INV8. The gate of MN4 is connected to H_A0N. The output terminal of INV8 is connected to the input terminal of INV9. The output terminal of INV9 is connected to the input terminal of INV10. The output terminal of INV10 is respectively connected to one end of C1, one end of C2, the gate of MP5, and the gate of MN5. The other end of C1 is connected to VS. The other end of C2 is respectively connected to V0, the positive terminal of Z3, and the source of MN5. The negative terminal of Z3 is connected to VS. The drain of MN5 is respectively connected to the drain of MP5, the drain of MP6, H_DRV, the positive terminal of Z4, and the input terminal of INV11. The source of MP5 is connected to VS. The negative terminal of Z4 is connected to VS. The output terminal of INV11 is connected to the gate of MP7. The source of MP7 is respectively connected to the output terminal of I3 and the positive terminal of Z5. The input terminal of I3 is connected to VS. The negative terminal of Z5 is connected to VS. The drain of MP7 is respectively connected to the input terminal of I4, the negative terminal of Z6, and the input terminal of INV12. The output terminal of I4 is grounded. The positive terminal of Z6 is grounded. The output terminal of INV12 is connected to the input terminal of INV13. The output terminal of INV13 is connected to H_DET.

[0023] Among them, MP1 to MP4, MN1 to MN4, and Z1 to Z2 form the input stage of the high-side drive circuit;

[0024] INV6 to INV11 are inverters from power supply VS to V0, shaping the signals; MP5, MP6, and MN5 control the charging and discharging of the output gate; Z3 to Z6 clamp the voltage to ensure the safe operation of the device; INV11 and MP7 implement dead-time delay, and INV12 to INV13 are inverters from VINT0 rail to GND, where VINT0 is the internal power supply, typically 5V; the voltage value of V0 is equal to the voltage value of VS minus VZ, and VZ represents the regulated voltage value of the Zener diode, which is 5.7V in this embodiment; I1 to I4 provide bias current for the circuit.

[0025] Furthermore, the low-side drive circuit is used to generate dead time and resist the interference of the rate of voltage change when the high-side power transistor conducts, and also includes port L_DRV, which serves as the external output port 2 of the drive control circuit.

[0026] Specifically, as Figure 6 shown, the low-side drive circuit includes 6 PMOS transistors MP8 to MP13, 5 NMOS transistors MN6 to MN10, 2 Zener diodes Z7, Z8, 7 inverters INV14 to INV20, 5 current sources I5 to I9, 3 capacitors C3 to C5, and 2 resistors R1, R2.

[0027] Among them, L_A0 is connected to the gate of MN6, the source of MN6 is connected to the input terminal of I5, the output terminal of I5 is grounded, the drain of MN6 is respectively connected to the gate of MP9, the gate of MP8, and the drain of MP8. The source of MP8 is respectively connected to VINT0 and the source of MP9. The drain of MP9 is respectively connected to one end of R1, one end of C3, and the input terminal of INV14. The other end of R1 is grounded, the other end of C3 is grounded, the output terminal of INV14 is connected to the input terminal of INV15, the output terminal of INV15 is connected to the input terminal of INV16, and the output terminal of INV16 is respectively connected to one end of C5, one end of C6, the gate of MP12, and the gate of MN8. The other end of C5 is grounded, the other end of C6 is VINT0, the source of MP12 is connected to VINT0, and the drain of MP12 is respectively connected to the drain of MN8, the drain of MN9, L_DRV, the negative terminal of Z7, and the gate of MN10. The source of MN8 is grounded, the positive terminal of Z7 is grounded, the source of MN10 is grounded, and the drain of MN10 is respectively connected to the output terminal of I7, the negative terminal of Z8, and the gate of MP13. The input terminal of I7 is connected to VINT0, the positive terminal of Z8 is grounded, the source of MP13 is connected to the output terminal of I8, the input terminal of I8 is connected to VINT0, the drain of MP13 is respectively connected to I9 and the input terminal of INV18. The output terminal of I9 is grounded, the output terminal of INV18 is connected to the input terminal of INV19, the output terminal of INV19 is connected to the input terminal of INV20, and the output terminal of INV20 is connected to L_DET. L_A1 is connected to the gate of MN7, the source of MN7 is connected to the input terminal of I6, the output terminal of I6 is grounded, the drain of MN7 is respectively connected to the gate of MP11, the gate of MP10, and the drain of MP10. The source of MP10 is respectively connected to VINT0 and the source of MP11. The drain of MP11 is respectively connected to one end of R2, one end of C4, and the input terminal of INV17. The other end of R2 is grounded, the other end of C4 is grounded, the output terminal of INV17 is connected to the gate of MN9, and the source of MN9 is grounded.

[0028] Among them, MN6 - MN7, MP8 - MP11, and R1 - R2 form an input - stage circuit; INV14 - INV17 are inverters from VINT0 to GND, which shape the signals; MP12, MN8 - MN9 realize the control of charging and discharging of the output gate; Zener diodes Z7 - Z8 clamp the voltage to ensure the safe operation of the device; MN10 and MP13 realize dead - time delay; INV18 - INV20 are inverters from the VINT0 power rail to GND; I5 - I9 provide bias current for the circuit.

[0029] Further, the external circuit in the embodiment includes a PMOS transistor MP0 and an NMOS transistor MN0. The gate of MP0 is connected to H_DRV, the source of MP0 is connected to VS, the drain of MP0 is connected to the drain of MN0, the drain of MN0 is connected to L_DRV, and the source of MN0 is grounded. The drain of MN0 serves as the output terminal VOUT of the circuit.

[0030] Further, when the input signal PWM_H switches from low to high and PWM_L switches from high to low: PWM_L is not delayed to obtain L_A0, indicating that the low-side power transistor MN0 is turned off first; PWM_H is ANDed with the L_DET signal and delayed to obtain H_A0, H_A0N, H_A1, and H_A1N signals, indicating that when the power transistor output switches from low to high, the turn-on of the high-side power transistor MP0 is delayed; L_A1 has the same delay time as H_A0, H_A0N, H_A1, and H_A1N signals, indicating that while the high-side power transistor MP0 is conducting, the gate of the low-side power transistor MN0 is discharged and pulled down.

[0031] When PWM_H switches from high to low and PWM_L switches from low to high: PWM_H is not delayed to obtain H_A0 and H_A0N, indicating that the high-side power transistor MP0 is turned off first; PWM_L is ANDed with the H_DET signal and delayed to obtain L_A0 and L_A1 signals, indicating that when the power transistor output switches from high to low, the turn-on of the low-side power transistor MN0 is delayed; H_A1, H_A1N have the same delay time as L_A0 and L_A1 signals, indicating that while the low-side power transistor MN0 is conducting, the gate of the high-side power transistor MP0 is charged and pulled up.

[0032] The working process of the drive control circuit includes:

[0033] When the power bridge output VOUT switches from low to high, the output signal of L_DRV is at a low level, first turning off the low-side power transistor MN0; after a certain dead time, the drive control circuit makes the H_DRV output a low level, turning on the high-side power transistor MP0, and VOUT is pulled high; while MP0 is turned on, the drive control circuit discharges and pulls down the gate of MN0 to prevent the gate voltage of the MN0 transistor from rising as the drain voltage of MN0 rises due to the Miller capacitance of MN0, which may cause the MN0 transistor to turn on and avoid the direct connection of the power half-bridge MN0 and MP0.

[0034] When the power bridge output VOUT switches from high to low, the drive control circuit makes the H_DRV signal high, first turning off the high-side power transistor MP0; after a certain dead time, the drive control circuit makes the L_DRV output high, turning on the low-side power transistor MN0, and VOUT is pulled low; while MN0 is turned on, the drive control circuit charges and pulls up the gate of MP0 to prevent the gate voltage of MP0 from dropping as the drain voltage of MP0 drops due to the Miller capacitance of MP0, which may cause MP0 to turn on and avoid the direct connection between the power half-bridges MN0 and MP0.

[0035] As Figure 3 shown in the working timing state diagram of the logic circuit, where:

[0036] During the period from t1 to t3, the power transistor output switches from low to high: at time t1, the L_A0 signal drops, turning off the low-side power transistor MN0; the period from t1 to t2 is the dead time; at time t2, the H_A0, H_A0N, H_A1, and H_A1N signals switch, turning on the high-side power transistor MP0, and L_A1 drops, discharging and pulling down the gate of the low-side power transistor MN0 to suppress the interference of dv / dt (rate of voltage change).

[0037] During the period from t4 to t6, the power transistor output switches from low to high: at time t4, the H_A0 and H_A0N signals switch, turning off the high-side power transistor MP0; the period from t4 to t5 is the dead time; at time t5, the L_A0 and L_A1 signals rise, turning on the low-side power transistor MN0, and H_A1 and H_A1N switch, charging and pulling up the gate of the high-side power transistor MP0 to suppress the interference of dv / dt.

[0038] As Figure 5 shown in the waveform schematic diagram when the high-side drive circuit is working, where:

[0039] During the period from t1 to t3, the power bridge output switches from low to high; the period from t1 to t2 is the dead time generated by the low-side drive circuit. During this period, the low-side power transistor MN0 is turned off, and the state of the high-side drive circuit remains unchanged; at time t2, the H_A0, H_A0N, H_A1, and H_A1N signals switch, the potential at point C changes from low to high, the potential at point D changes from high to low. After passing through the inverters INV6 - INV10, MP6 and MP5 are turned off, MN5 is turned on, discharging point A, the H_DRV signal is connected to the gate of the high-side power transistor MP0, and the potential slowly drops, and MP0 gradually turns on; the potential at point A drops slowly and reaches the inversion point of INV11 after a period of time, MP7 is turned off, the potential at point E discharges and drops through I4, and reaches the inversion point of INV12 after a period of time. After passing through INV12 - INV13, the H_DET signal changes from high to low, and this is time t3.

[0040] During the time period from t4 to t6, the output of the power bridge switches from high to low; at the moment of t4, H_A0 and H_A0N switch, the potential at point D changes from low to high. Through INV8 to INV10, MN5 is turned off and MP5 is turned on to charge point A. The H_DRV signal is connected to the gate of the high-side power transistor MP0, and the potential gradually rises, and MP0 gradually turns off. After a period of time, the potential at point A reaches the inversion point of INV11, MP7 is turned on, the current I3 is greater than the current I4, and I3 charges point E. After a period of time, the potential at point E reaches the inversion point of INV12. Through INV12 to INV13, the H_DET signal changes from low to high. This is the moment of t5, and the time period from t4 to t5 is the dead time generated by the high-side drive circuit; at the moment of t5, through the control of the logic circuit, the low-side power transistor MN0 is turned on.

[0041] The signals of H_A1 and H_A1N switch, the potential at point C changes from high to low, and MP6 is turned on to charge point A with a large current; that is, when the low-side power transistor MN0 is conducting, the output VOUT changes from high to low, generating a large dv / dt. The drain of the high-side power transistor MP0 is connected to VOUT, and the potential drops rapidly. To prevent the gate voltage of the MP0 transistor from dropping as the drain voltage of the MP0 drops due to the Miller capacitance of MP0, causing the MP0 transistor to turn on, point A connected to the gate of MP0 is charged at this moment to counteract the dv / dt interference and prevent the MP0 transistor from turning on. The time period from t5 to t6 is generated by the low-side drive circuit.

[0042] As Figure 7 shown is the waveform schematic diagram when the low-side drive circuit is working, where:

[0043] During the time period from t1 to t3, the output switches from low to high; at the moment of t1, L_A0 drops, the potential at point F changes from high to low. After passing through INV14 to INV16, MP12 is turned off and MN8 is turned on to discharge point B. The L_DRV signal is connected to the gate of the low-side power transistor MN0, and the potential gradually drops, and the N transistor is gradually turned off. After a period of time, the potential at point B reaches the threshold voltage of MN10, and MN10 is turned off. I7 gradually charges the gate of MP13. After a period of time, MP13 is turned off. I9 discharges point H. After a period of time, the potential at point H reaches the inversion point of INV18. After passing through LIN18 to INV20, the L_DET signal changes from low to high. This is the moment of t2. The time period from t1 to t2 is the dead time generated by the low-side drive circuit; at the moment of t2, under the control of the logic circuit, the high-side power transistor is turned on. The L_A1 signal changes from high to low, and the potential at point G changes from high to low. After passing through INV17, MN9 is turned on to discharge point B with a large current; that is, when the high-side power transistor MP0 is conducting, the output VOUT changes from low to high, generating a large dv / dt. The drain of the low-side power transistor MN0 is connected to VOUT, and the potential rises rapidly. To prevent the gate voltage of the MN0 transistor from rising as the drain voltage of MN0 rises due to the Miller capacitance of MN0, point B connected to the gate of MN0 is discharged at this moment to counteract the dv / dt interference and avoid the conduction of the MN0 transistor; the time period from t2 to t3 is generated by the high-side drive circuit.

[0044] During the time period from t4 to t6, the output of the power bridge switches from high to low; the time period from t4 to t5 is the dead time generated by the high-side drive circuit. During this time period, the high-side power transistor MP0 is turned off, and the state of the low-side drive circuit remains unchanged; at the moment of t5, the L_A0 and L_A1 signals change from low to high, and the potentials at points G and F both change from low to high. After passing through the inverters INV14 to INV17, MN8 and MN9 are turned off, and MP12 is turned on to charge point B. The L_DRV signal is connected to the gate of the low-side power transistor MN0, and the potential rises slowly, and the N transistor is gradually turned on; the potential at point B rises slowly and reaches the threshold voltage of MN10 after a period of time. MN10 is turned on, the gate potential of MP13 drops, MP13 is turned on, the current I8 is greater than the current I9, and point H is charged. After a period of time, the potential at point H reaches the inversion point of INV18. After passing through LIN18 to INV20, the L_DET signal changes from high to low.

[0045] Finally, it should be noted that the above description only depicts some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and deformations can be conceived without departing from the principles and spirits of the present invention. The protection scope of the present invention is defined by the appended claims and their equivalents, and the above actions should all be covered within the protection scope of the present invention.

Claims

1. A driving control circuit with both dead time control and voltage change rate resistance, characterized in that: include: Logic circuit, high-side driver circuit and low-side driver circuit; The logic circuit includes 10 ports, namely PWM_H, PWM_L, H_DET, L_DET, H_A1N, H_A0N, H_A1, H_A0, L_A1, L_A0; among which H_A1N, H_A0N, H_A1, H_A0, H_DET are connected to the high-side drive circuit, and L_A1, L_A0, L_DET are connected to the low-side drive circuit; PWM_H and PWM_L are respectively used as external input port 1 and external input port 2 of the drive control circuit; The high-side drive circuit also includes a port H_DRV, which serves as an external output port 1 of the drive control circuit; The low-side driving circuit also includes a port L_DRV, which serves as an external output port 2 of the driving control circuit; The drive control circuit is connected to the external power supply VS, the internal power supply V0 and VINT0 when working.

2. The driving control circuit with both dead time control and voltage change rate resistance according to claim 1, characterized in that: The logic circuit is used to obtain high-side and low-side PWM control signals and process the high-side and low-side logic signals fed back within the circuit to achieve interlocking between the high-side and low-side signals; the high-side drive circuit is used to achieve level shifting from low-voltage logic signals to high-voltage drive, generation of dead time, and resistance to voltage change rate interference when the low-side power tube is turned on; the low-side drive circuit is used to achieve generation of dead time and resistance to voltage change rate interference when the high-side power tube is turned on.

3. The driving control circuit with both dead time control and voltage change rate resistance according to claim 1, characterized in that: The logic circuit includes: 2 AND gates AND1-AND2, 5 inverters INV1-INV5, and 2 NOR gates NOR1-NOR2; Among them, PWM_H is connected to the lower input end of AND1; PWM_L is connected to the lower input end of AND2; H_DET is respectively connected to the input end of INV1 and the upper input end of AND2; L_DET is respectively connected to the input end of INV2 and the upper input end of AND1; the output end of INV1 is connected to the upper input end of NOR1; the output end of AND1 is respectively connected to the lower input end of NOR1, the input end of INV4 and H_A0N; the output end of INV2 is connected to the upper input end of NOR2; the output end of AND2 is respectively connected to the lower input end of NOR2 and L_A0; the output end of NOR1 is respectively connected to the input end of INV3 and H_A1; the output end of NOR2 is connected to the input end of INV5; the output end of INV3 is connected to H_A1N; the output end of INV4 is connected to H_A0; the output end of INV5 is connected to L_A1.

4. The driving control circuit with both dead time control and voltage change rate resistance according to claim 1, characterized in that: The high-side driving circuit includes: 7 PMOS tubes MP1-MP7, 5 NMOS tubes MN1-MN5, 6 Zener diodes Z1-Z6, 8 inverters INV6-INV13, 4 current sources I1-I4, and 2 capacitors C1 and C2; Among them, H_A1N is connected to the gate of MN1, the source of MN1 is respectively connected to the source of MN2 and the input end of I1, the output end of I1 is grounded, the drain of MN1 is respectively connected to the gate of MP2, the gate of MP1, and the drain of MP1, the source of MP1 is respectively connected to VS, the source of MP2, and the negative end of Z1, the drain of MP2 is respectively connected to the drain of MN2, the positive end of Z1, and the input end of INV6, the gate of MN2 is connected to H_A1, the output end of INV6 is connected to the input end of INV7, the output end of INV7 is connected to the gate of MP6, and the source of MP6 is connected to VS; H_A0 is connected to the gate of MN3, the source of MN3 is respectively connected to the source of MN4 and the input of I2, the output of I2 is grounded, the drain of MN3 is respectively connected to the gate of MP4, the drain of MP3, and the gate of MP3, the source of MP3 is respectively connected to VS, the source of MP4, and the negative terminal of Z2, the drain of MP4 is respectively connected to the drain of MN4, the positive terminal of Z2, and the input of INV8, the gate of MN4 is connected to H_A0N, The output end of INV8 is connected to the input end of INV9, the output end of INV9 is connected to the input end of INV10, the output end of INV10 is respectively connected to one end of C1, one end of C2, the gate of MP5, and the gate of MN5, the other end of C1 is connected to VS, the other end of C2 is respectively connected to V0, the positive end of Z3, and the source of MN5, the negative end of Z3 is connected to VS, the drain of MN5 is respectively connected to the drain of MP5, the drain of MP6, H_DRV, the positive end of Z4, and the input end of INV11, The source of MP5 is connected to VS, the negative end of Z4 is connected to VS, the output end of INV11 is connected to the gate of MP7, the source of MP7 is connected to the output end of I3 and the positive end of Z5 respectively, the input end of I3 is connected to VS, the negative end of Z5 is connected to VS, the drain of MP7 is connected to the input end of I4, the negative end of Z6, and the input end of INV12 respectively, the output end of I4 is grounded, the positive end of Z6 is grounded, the output end of INV12 is connected to the input end of INV13, and the output end of INV13 is connected to H_DET.

5. The driving control circuit with both dead time control and voltage change rate resistance according to claim 4, characterized in that: I1~I4 provide bias current for the circuit, and the current of I3 is greater than the current of I4.

6. The driving control circuit with both dead time control and voltage change rate resistance according to claim 4, characterized in that: The voltage value of V0 is equal to the voltage value of VS minus VZ, where VZ represents the voltage regulation value of the Zener diode.

7. The driving control circuit with both dead time control and voltage change rate resistance according to claim 1, characterized in that: The low-side driving circuit includes 6 PMOS tubes MP8-MP13, 5 NMOS tubes MN6-MN10, 2 Zener diodes Z7, Z8, 7 inverters INV14-INV20, 5 current sources I5-I9, 3 capacitors C3-C5, and 2 resistors R1, R2; Among them, L_A0 is connected to the gate of MN6, the source of MN6 is connected to the input end of I5, the output end of I5 is grounded, the drain of MN6 is respectively connected to the gate of MP9, the gate of MP8, and the drain of MP8, the source of MP8 is respectively connected to VINT0, the source of MP9, and the drain of MP9 are respectively connected to one end of R1, one end of C3, and the input end of INV14, the other end of R1 is grounded, the other end of C3 is grounded, the output end of INV14 is connected to the input end of INV15, the output end of INV15 is connected to the input end of INV16, the output end of INV16 is respectively connected to one end of C5, one end of C6, the gate of MP12, and the gate of MN8, the other end of C5 is grounded, the other end of C6 is VINT0, and the source of MP12 is connected to V INT0, the drain of MP12 is respectively connected to the drain of MN8, the drain of MN9, L_DRV, the negative terminal of Z7, and the gate of MN10, the source of MN8 is grounded, the positive terminal of Z7 is grounded, the source of MN10 is grounded, the drain of MN10 is respectively connected to the output terminal of I7, the negative terminal of Z8, and the gate of MP13, the input terminal of I7 is connected to VINT0, the positive terminal of Z8 is grounded, the source of MP13 is connected to the output terminal of I8, the input terminal of I8 is connected to VINT0, the drain of MP13 is respectively connected to the input terminal of I9 and the input terminal of INV18, the output terminal of I9 is ​​grounded, the output terminal of INV18 is connected to the input terminal of INV19, the output terminal of INV19 is connected to the input terminal of INV20, and the output terminal of INV20 is connected to L_DET; L_A1 is connected to the gate of MN7, the source of MN7 is connected to the input of I6, the output of I6 is grounded, the drain of MN7 is respectively connected to the gate of MP11, the gate of MP10, and the drain of MP10, the source of MP10 is respectively connected to VINT0 and the source of MP11, the drain of MP11 is respectively connected to one end of R2, one end of C4, and the input of INV17, the other end of R2 is grounded, the other end of C4 is grounded, the output of INV17 is connected to the gate of MN9, and the source of MN9 is grounded.

8. The driving control circuit with both dead time control and voltage change rate resistance according to claim 7, characterized in that: I5~I9 provide bias current for the circuit, and the current of I8 is greater than the current of I9.

9. The driving control circuit with both dead time control and voltage change rate resistance according to claim 1, characterized in that: The voltage of VINT0 is 5V.

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