Continuous time pipeline analog-to-digital converter based on multipath interleaving time domain

Abstract

The invention provides a continuous time pipeline analog-to-digital converter based on a multipath interleaving time domain. The continuous time pipeline analog-to-digital converter comprises a continuous time level ADC, a time domain ADC and a digital reconfigurable filter, the continuous time-stage ADC performs high-order quantization on an input signal and then outputs the input signal to the digital reconfigurable filter, and performs filtering processing on a residual signal in the input signal and then outputs the residual signal to the time-domain ADC; the time domain ADC is used for quantizing the residual signals passing through the continuous time level ADC and then outputting the quantized residual signals to the digital reconfigurable filter; and the digital reconfigurable filter is used for carrying out digital filtering on the quantization result of the continuous time level ADC and carrying out data reconstruction on the quantization code value output by the time domain ADC. The architecture not only retains the characteristics of ultrahigh energy efficiency and digitization of a time domain ADC, but also benefits from the continuous time ADC architecture, and the resistive input impedance and the inherent anti-aliasing filtering effect of the continuous time ADC architecture are beneficial to the realization of a high-speed ADC in a completely integrated wireless receiver.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly relates to a continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain. Background Art

[0002] Time-domain ADC is a new architecture with great potential for high-speed and high energy efficiency, which has important significance and research value for realizing high-performance ultra-high-speed communication systems. Especially in radio frequency receivers or zero-IF receivers, a hybrid-domain ADC composed of a front-stage voltage-domain sub-ADC cascaded with a rear-stage multi-channel time-domain ADC has a higher energy efficiency ratio compared with a pure voltage-domain ADC.

[0003] Most ADC architectures are implemented in discrete-domain (DT) circuits, that is, switch capacitors are required for sampling operations and subsequent signal processing; however, discrete-time (DT) ADCs require additional circuits in fully integrated wireless receiver applications, such as an anti-aliasing filter (AAF) to filter out out-of-band frequency signals, and an ADC driver stage circuit to drive the PF-level switch capacitor sampling network and suppress kickback, thereby increasing the system-level power consumption and system design complexity. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain, specifically including:

[0005] In a first aspect, the present invention provides a continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain, including:

[0006] A continuous-time stage ADC, a time-domain ADC, and a digital reconfigurable filter;

[0007] The continuous-time stage ADC performs high-order quantization on the input signal, outputs the quantization result to the digital reconfigurable filter, and filters the residual signal in the input signal, and outputs the processed signal to the time-domain ADC.

[0008] Specifically, the continuous-time stage ADC serves as the input end of the overall ADC, performs high-order quantization on the input signal and filters the residual signal, and its output end is connected to the input end of the time-domain ADC.

[0009] The time-domain ADC quantizes the residual signal that has passed through the continuous-time stage ADC, and outputs the obtained quantization code value to the digital reconfigurable filter.

[0010] Specifically, the input end of the time-domain ADC is connected to the output end of the continuous-time stage ADC, and is used to quantize the residual signal after the continuous-time stage ADC.

[0011] A digital reconfigurable filter is used to digitally filter the quantization results of a continuous-time ADC and reconstruct the data of the quantized code values output by the time-domain ADC to achieve the anti-aliasing filtering effect.

[0012] Specifically, the input end of the digital reconfigurable filter is connected to the quantization result of the continuous-time stage, which is used to digitally filter the quantized code values of the continuous-time ADC, reconstruct the data of the quantized code values of the subsequent time-domain ADC, and achieve the anti-aliasing filtering effect.

[0013] In a second aspect, the present invention also provides an electronic device, including any continuous-time pipelined analog-to-digital converter based on multiplexed interleaved time domain provided in the first aspect.

[0014] Advantages of the present invention:

[0015] The continuous-time pipelined analog-to-digital converter based on multiplexed interleaved time domain provided by the present invention includes: a continuous-time ADC, a time-domain ADC, and a digital reconfigurable filter; the continuous-time ADC is used to perform high-order quantization on the input signal, output the quantization result to the digital reconfigurable filter, filter the residual signal in the input signal, and output the processed signal to the time-domain ADC; the time-domain ADC is used to quantize the residual signal that has passed through the continuous-time ADC and output the obtained quantized code value to the digital reconfigurable filter; the digital reconfigurable filter is used to digitally filter the quantization result of the continuous-time ADC and reconstruct the data of the quantized code value output by the time-domain ADC to achieve the anti-aliasing filtering effect. This architecture not only retains the characteristics of ultra-high energy efficiency and digitization of the time-domain ADC but also benefits from the continuous-time ADC architecture with its resistive input impedance and inherent anti-aliasing filtering effect, which is of great significance for the design of high-speed ADCs and system design in fully integrated wireless receivers.

[0016] The following will further elaborate on the present invention in conjunction with the accompanying drawings and embodiments. Description of the Drawings

[0017] Figure 1 It is a schematic structural diagram of a continuous-time pipelined analog-to-digital converter based on multiplexed interleaved time domain provided by the present invention;

[0018] Figure 2 It is a schematic structural diagram of a delay chain array provided by the present invention;

[0019] Figure 3 It is a schematic structural diagram of a filter circuit provided by the present invention;

[0020] Figure 4 It is a schematic diagram of the calibration process of an IDAC circuit provided by the present invention;

[0021] Figure 5 Schematic diagram of the impulse response of a digital reconfigurable digital filter provided by the present invention;

[0022] Figure 6 Schematic diagram of the operation process of a digital reconfigurable digital filter provided by the present invention;

[0023] Figure 7 Schematic diagram of the architecture of a high - energy - efficient time - domain ADC based on a ring oscillator provided by the present invention;

[0024] Figure 8 Schematic diagram of an experimental result provided by the present invention;

[0025] Figure 9 Another schematic diagram of an experimental result provided by the present invention. Detailed implementation manners

[0026] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0027] To solve the problems existing in the prior art, the present invention proposes a continuous - time pipelined analog - to - digital converter based on a multi - path interleaved time domain. This ADC architecture not only retains the characteristics of ultra - high energy efficiency and digitization of the time - domain ADC, but also benefits from the continuous - time ADC architecture, its resistive input impedance and inherent anti - aliasing filtering effect, which is of great significance for the design of high - speed ADCs and system design in fully integrated wireless receivers.

[0028] Figure 1 Schematic diagram of the structure of a continuous - time pipelined analog - to - digital converter based on a multi - path interleaved time domain provided by the present invention, including: a continuous - time - stage ADC10, a time - domain ADC, and a digital reconfigurable filter.

[0029] The continuous - time - stage ADC10 is used to perform high - bit quantization on the input signal, output the quantization result to the digital reconfigurable filter, and filter the residual signal in the input signal, and output the processed signal to the time - domain ADC.

[0030] The time - domain ADC is used to quantize the residual signal that has passed through the continuous - time - stage ADC, and output the obtained quantization code value to the digital reconfigurable filter.

[0031] The digital reconfigurable filter is used to perform digital filtering on the quantization result of the continuous - time - stage ADC, and perform data reconstruction on the quantization code value output by the time - domain ADC to achieve the anti - aliasing filtering effect.

[0032] Optionally, as Figure 1As shown, the continuous-time stage ADC10 includes: a filter circuit 101, a sub-ADC, an IDAC, a DAC, and a PRBS.

[0033] The filter circuit 101 is used to amplify the signal residue and implement anti-aliasing filtering.

[0034] The sub-ADC quantizes the input signal and generates a quantized code value output.

[0035] The IDAC is controlled by the quantized code value output by the sub-ADC to output a current. The sum of the outputs of each controlled IDAC is subtracted from the input current signal at the output end of the delay chain and connected to the TIA, flowing into the TIA.

[0036] The DAC is a 1-bit IDAC and is used to generate a 1-bit random pulse signal according to the pseudo-random signal generated by the PRBS.

[0037] The PRBS is used to control the 1-bit IDAC according to the generated pseudo-random signal.

[0038] Specifically, the PRBS is used to generate a "0, 1" code stream with pseudo-random attributes to separately control the 1-bit IDAC.

[0039] Optionally, the filter circuit 101 includes: a delay chain array, a residue amplifier, and an RC feedback unit.

[0040] The output end of the delay chain array 1110 is input to the inverting input end of the residue amplifier, and the input end is used to receive the external voltage V in ; The RC feedback unit is connected across the output end and the inverting input end of the residue amplifier; the non-inverting input end of the residue amplifier is grounded.

[0041] Exemplarily, as Figure 2 shown, the delay chain array is composed of RC low-pass filters.

[0042] As Figure 2 shown, the delay chain array includes N low-pass filters composed of RC. The N RCs are connected in parallel, one end serves as the input signal port, and the other end is connected to the IDAC output, jointly generating a residue current signal flowing through the filter circuit 101.

[0043] Each RC low-pass filter includes a capacitor, a resistor, and a control switch.

[0044] In a pipelined ADC, a residual signal with an appropriate amplitude needs to be generated, which requires the phase delay matching between the signal passing through the main path and the IDAC output signal. However, in a CT_Pipeline (continuous-time pipelined) ADC, in order to avoid spectral aliasing introduced by sampling, the input signal directly passes through the main signal path without being sampled, and there is no delay in the input signal, which will lead to a phase mismatch with the IDAC output signal, thus generating a relatively large residual exceeding the amplitude of the input signal. By using a delay chain array, a positive delay can be introduced into the signal path to match the phase difference and obtain the correct residual signal.

[0045] A great advantage of CT ADC is the inherent anti-aliasing filter. In the application of a wireless receiver system, the CT ADC integrates the anti-aliasing filter at the front end of the ADC into the inter-stage residual amplifier inside the ADC.

[0046] Exemplarily, as Figure 3 shown, the low-pass filter consists of a front-end delay chain array, a TIA (transimpedance amplifier), and peripheral feedback capacitance and resistance. In order to improve out-of-band rejection and make the out-of-band roll-off more obvious, the filter circuit 101 adopts Figure 3 the second-order Tow-Tomas structure shown. Due to the requirements of 5G / 6G communication systems, the ADC needs a larger digital bandwidth, and the filter op-amp needs to have a high gain at the signal bandwidth (500 MHz) to achieve high linearity. At the same time, for a second-order system, there are also certain requirements for the stability of the op-amp. The third-order feedforward op-amp shown in Figure 3 can be adopted (corresponding to the AMP part in the figure). To achieve a high gain while achieving a large GBW (gain-bandwidth product), the cascading of multiple-stage op-amps is required. However, the cascading of traditional two-stage and above requires methods such as Miller compensation to ensure phase margin and stability, and this method pushes the poles inward, which will reduce the overall GBW; on the contrary, Figure 3 the feedforward op-amp shown provides zeros by adding a feedforward path, forms zero-pole pairs near the poles, and offsets the influence of the poles. Thus, a multi-stage multi-path feedforward amplifier can achieve high gain at high frequencies at a relatively low unity-gain frequency.

[0047] Optionally, the selection of the DC gain of the filter, the cut-off frequency of the filter, and the filter order are all related to the phase matching effect of the above-mentioned delay chain array and the coarse quantization bits of the continuous-time stage.

[0048] Optionally, the IDAC includes: a complementary current-steering IDAC array and a calibration circuit, and the calibration circuit includes a switch array and a sequential rotation control signal generation module.

[0049] A switch array is used to control the respective reference voltages corresponding to the complementary current-steering IDAC array in a one-hot control manner based on the control signals generated by the sequential rotation control signal generation module.

[0050] As Figure 4 shown, the IDAC circuit includes a complementary current-steering IDAC array and a calibration circuit. The reference voltage is obtained by voltage division of a resistor string. The reference voltage is not directly connected to the input terminal of the comparator (COMP). Each reference voltage is connected to the input terminal of the comparator through a switch array composed of a plurality of switches. The control signal of this switch array is generated by a dedicated pseudo-random control signal generation circuit, and the reference voltage at the input terminal of each comparator is updated in real time according to a period, achieving the effect of reference voltage rotation, indirectly realizing the effect of sequential rotation of the IDAC circuit. The output of the comparator controls the output of the IDAC circuit, injecting or extracting current into the input node of the TIA, completing the subtraction of the signal from the first-stage coarse quantization result to generate a residual current, which is amplified by the TIA and then quantified and processed by the subsequent-stage ADC.

[0051] Optionally, the reconstruction logic of the digital reconfigurable filter is expressed as:

[0052] D out_cali (n)=D 1 '(n)+D 2 (n)-D 2_prbs (n),

[0053]

[0054] where D out_cali (n) represents the reconstructed output signal, n represents the index of the clock cycle, D 1 '(n) represents the digital code at the continuous-time level after digital domain filtering convergence after n clock cycles, D 2 (n) represents the quantization digital code of the residual signal by the time-domain ADC in the nth clock cycle, D 2_prbs (n) represents the digital code of the PRBS generation module after digital domain filtering convergence after n clock cycles, D 1 (n) represents the quantization digital code at the continuous-time level in the nth clock cycle, d 1 (n) represents the digital code of the PRBS generation module in the nth clock cycle, represents injecting a unit impulse at the input terminal of the filter. After passing through the filter, the subsequent-stage time-domain ADC respectively represents the system responses at the current cycle and delayed by one cycle, represents injecting a unit impulse at the input terminal of the filter. After passing through the filter, the subsequent-stage time-domain ADC respectively represents the system responses at the current cycle and delayed by two cycles, It represents injecting a unit impulse at the input of the filter. After passing through the filter, the system responses of the subsequent time-domain ADC at the current cycle and with a three-cycle delay are respectively obtained.

[0055] Exemplarily, the signal reconstruction process of the CT Pipeline ADC is as Figure 5 shown. Similar to the DT Pipeline ADC, however, due to the filter, when injecting a pulse in the IDAC, the pulse response observed by the subsequent quantizer will be distributed over multiple cycles (instead of being distributed only in one cycle as in the DT Pipeline ADC), denoted as F(z). The present invention can also design the filter as 1 / F(z) to reconstruct the input signal. However, the difficulty is that 1 / F(z) corresponds to a non-causal sequence in the digital domain. Therefore, the present invention introduces filter A and designs filter A as F(z), and filter B as 1 to restore causality. The acquisition of the filter tap coefficients is based on the Figure 6 cross-correlation operation as shown. To obtain the transfer function of H[z], a random dither sequence d[n] is added to the input u[n]; the cross-correlation operation is performed on the random dither sequence d[n] and its delayed sequences with the output y[n] to obtain the cross-correlation result H[z], which is expressed as:

[0056]

[0057] where H[z] represents the discrete z-domain expression corresponding to a linear time-invariant (LTI) system, d[n - i] represents the digital code of the PRBS generation module before the i-th clock cycle, represents the convolution operation, N represents the filter tap order, y[n] represents the response of the input signal passing through the linear time-invariant (LTI) system, h[n - i] represents the i-th term of the linear time-invariant (LTI) system, and * represents the multiplication operation.

[0058] When given sufficient samples, the correlation result of two uncorrelated signals (the input signal sequence and the random dither sequence) is 0, and the correlation of the random dither sequence with itself gives a coefficient. In the case of sufficient samples, the correlation coefficients form the taps of the impulse response of H[z]. The correlation operation is sequentially performed with its delayed sequences to obtain all tap coefficients. Subsequently, the obtained tap coefficients are used to perform digital filtering on the first-stage coarse quantization code value and reconstruct the subsequent code value to achieve the effects of ADC quantization and anti-aliasing filtering.

[0059] Optionally, the time-domain ADC includes a single-channel high-energy-efficiency time-domain ADC based on a ring oscillator.

[0060] Exemplarily, the subsequent time-domain ADC adopts as Figure 7The shown high - energy - efficient time - domain analog - to - digital converter based on a gated ring oscillator is formed by time - domain interleaving.

[0061] Optionally, the high - energy - efficient time - domain analog - to - digital converter based on a gated ring oscillator specifically includes:

[0062] A voltage - to - time conversion circuit, a pulse generation circuit, a self - tracking sampling clock generation circuit, and a time - to - digital conversion circuit;

[0063] The time - to - digital conversion circuit includes a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit, and a sampling decoding circuit;

[0064] The voltage - to - time conversion circuit is used to convert a voltage signal into a step signal.

[0065] The pulse generation circuit is used to convert the step signal output by the voltage - to - time conversion circuit into a pulse - width signal.

[0066] The self - tracking sampling clock generation circuit is used to detect the output step signal of the voltage - to - time conversion circuit and generate a sampling clock signal for the sampling decoding circuit.

[0067] The time - to - digital conversion circuit is used to perform count quantization on the pulse - width signal output by the pulse generation circuit to obtain a quantization result.

[0068] Further optionally, the gated ring oscillator circuit includes N - stage gated delay units, and the N - stage gated delay units are cascaded to form a cross - coupled positive - feedback circuit. The gated delay unit resets the voltage of the internal node of the gated delay unit under the control of an external reset voltage. A positive - feedback resistor is connected on the positive - feedback path of the gated delay unit. The positive - feedback path of the gated delay unit and the gated inverter are controlled by the gating signal generated by the pulse generation circuit, which simplifies the subsequent decoding logic. At the same time, it effectively reduces the delay of the gated delay unit, improves the oscillation frequency and time resolution of the overall ring oscillator, completes the subsequent coarse quantization, and greatly improves the energy efficiency ratio of the ADC.

[0069] The continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain provided by the present invention includes: a continuous-time stage ADC, a time domain ADC, and a digitally reconfigurable filter; the continuous-time stage ADC is used for high-bit quantization of the input signal, outputting the quantization result to the digitally reconfigurable filter, and filtering the residual signal in the input signal, and outputting the processed signal to the time domain ADC; the time domain ADC is used for quantizing the residual signal that has passed through the continuous-time stage ADC, and outputting the obtained quantization code value to the digitally reconfigurable filter; the digitally reconfigurable filter is used for digitally filtering the quantization result of the continuous-time stage ADC and performing data reconstruction on the quantization code value output by the time domain ADC to achieve the anti-aliasing filtering effect. This architecture not only retains the characteristics of ultra-high energy efficiency and digitization of the time domain ADC, but also benefits from the continuous-time ADC architecture, its resistive input impedance and inherent anti-aliasing filtering effect, which is of great significance for the design of high-speed ADCs and system design in fully integrated wireless receivers.

[0070] To further prove the beneficial effects of the present invention, the present invention also provides a set of experimental data, specifically as Figure 8 and Figure 9 shown, Figure 8 is the input of the actual application scenario of the ADC, that is, the output spectrum diagram of the mixer. It can be seen that in the spectrum, in addition to the 100M baseband signal, there are also other sidebands and spurs of the mixing. Due to the interference of these sidebands, the dynamic range SFDR is only 33.71dBc, NSD=-132dBFS / Hz. After quantization and filtering by the continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain (as Figure 9 shown), the dynamic range SFDR=58.86dBc is achieved, more than 20dB of attenuation suppression is achieved for the upper sidebands, the effect of second-order filtering is achieved, and NSD reaches -154dBFS / Hz.

[0071] The present invention also provides an electronic device, including the continuous-time pipelined analog-to-digital converter based on multi-channel interleaved time domain provided in the above embodiments.

[0072] For the embodiment of the electronic device, since it is basically similar to the method embodiment, the description is relatively simple. For the specific content and beneficial effects and other related parts, please refer to the partial description of the method embodiment.

[0073] The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0074] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain, characterized in that: include: Continuous time level ADC, time domain ADC and digital reconfigurable filter; The continuous time-level ADC is used to perform high-bit quantization on the input signal, and output the quantization result to the digital reconfigurable filter, and filter the residual signal in the input signal, and output the processed signal to the time domain ADC; The time domain ADC is used to quantize the residual signal after passing through the continuous time stage ADC, and output the obtained quantization code value to the digital reconfigurable filter; The digital reconfigurable filter is used to digitally filter the quantization result of the continuous time stage ADC and to reconstruct the quantization code value output by the time domain ADC to achieve an anti-aliasing filtering effect.

2. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 1, characterized in that: The continuous time level ADC comprises: Filter circuits, sub-ADCs, IDACs, DACs, and PRBS; The filter circuit is used to amplify the signal residual and implement anti-aliasing filtering; The sub-ADC is used to quantize the input signal and output a quantization code value; The IDAC is used to output a current signal according to the quantization code value output by the sub-ADC; The DAC is used to generate a 1-bit random pulse signal according to the pseudo-random signal generated by the PRBS; The PRBS is used to generate a "0, 1" code stream with pseudo-random properties and independently control a 1-bit IDAC.

3. The continuous time pipeline analog-to-digital converter based on multi-path interleaved time domain according to claim 2, characterized in that: The filter circuit comprises: Delay chain array, residual amplifier and RC feedback unit; The output end of the delay chain array is input to the inverting input end of the residual amplifier, and the input end is used to receive an external voltage V in ; The RC feedback unit is connected between the output terminal and the inverting input terminal of the residual amplifier; A non-inverting input terminal of the residual amplifier is grounded.

4. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 3, characterized in that: The IDAC comprises: A complementary current steering IDAC array and a calibration circuit, wherein the calibration circuit comprises a switch array and a sequential rotation control signal generating module; The switch array is used to control the reference voltages corresponding to the complementary current steering IDAC array in a single-heat control manner based on the control signal generated by the sequential rotation control signal generating module.

5. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 4, characterized in that: The reconstruction logic of the digital reconfigurable filter is expressed as: D out_cali (n)=D1'(n)+D2(n)-D 2_prbs (n), Among them, D out_cali (n) represents the reconstructed output signal, n represents the index of the clock cycle, D1'(n) represents the continuous time level digital code after the digital domain filter converges after n clock cycles, D2(n) represents the quantized digital code of the residual signal of the time domain ADC in the nth clock cycle, D 2_prbs (n) represents the digital code of the PRBS generation module after digital domain filtering converges after n clock cycles, D1(n) represents the continuous time level quantized digital code of the nth clock cycle, d1(n) represents the digital code of the PRBS generation module of the nth clock cycle, It means that a unit pulse is injected into the filter input. After passing through the filter, the subsequent time domain ADC delays the system response by one cycle in the current cycle. It means that a unit pulse is injected into the filter input. After passing through the filter, the subsequent time domain ADC delays the system response by two cycles in the current cycle. It means that a unit pulse is injected into the input of the filter. After passing through the filter, the subsequent time domain ADC delays the system response by three cycles in the current cycle.

6. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 5, characterized in that: The time domain ADC includes a single-channel high-energy-efficiency time domain ADC based on a ring oscillator.

7. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 6, characterized in that: The single-channel ring oscillator-based energy-efficient time-domain ADC includes: Voltage-to-time conversion circuit, pulse generation circuit, self-tracking sampling clock generation circuit and time-to-digital conversion circuit; The time-to-digital conversion circuit includes a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit and a sampling decoding circuit; The voltage-time conversion circuit is used to convert the voltage signal into a step signal; The pulse generating circuit is used to convert the step signal output by the voltage-time conversion circuit into a pulse width signal; The self-tracking sampling clock generating circuit is used to detect the step signal output by the voltage-time conversion circuit and generate a sampling clock signal for the sampling decoding circuit; The time-to-digital conversion circuit is used to count and quantize the pulse width signal output by the pulse generation circuit to obtain a quantization result.

8. The continuous time pipeline analog-to-digital converter based on multi-channel interleaved time domain according to claim 7, characterized in that: The DC gain of the filter, the cutoff frequency of the filter and the selection of the filter order are all related to the phase matching effect of the delay chain array and the number of coarse quantization bits at the continuous time level.

9. An electronic device, characterized in that: It comprises a continuous time pipeline analog-to-digital converter based on multi-path interleaved time domain as described in any one of claims 1-8.

Images