Voltage regulation system with overshoot and undershoot regulation circuit

Abstract

A voltage regulating system comprises a voltage regulator and an overshoot and undershoot regulating circuit. The voltage regulator includes a gate terminal having a gate voltage, and an output terminal having an output voltage. The overshoot and undershoot adjusting circuit comprises an inverting amplifier and a capacitor. The inverting amplifier has an output end for outputting a feedback voltage in response to the change of the output voltage. The capacitor has a first terminal coupled to the gate terminal and a second terminal coupled to the output terminal of the inverting amplifier.

Description

Technical Field

[0001] The present invention relates to a voltage regulation system, and more particularly to a voltage regulation system with feedback. Background Art

[0002] A low dropout regulator (LDO) is a voltage regulator, also known as a low dropout linear regulator, which is a linear DC voltage regulator used to provide a stable DC voltage source. Compared with a general linear DC voltage regulator, the low dropout regulator can operate at a smaller input-output voltage difference.

[0003] The potential difference between the input node and the output node of the low dropout regulator has not been specifically defined, but generally, the minimum potential difference for the regulator to operate stably is less than 1V. Taking an integrated circuit (IC) with a power supply of 3.3V as an example, the standard power supply cannot be reduced from 5V to 3.3V, so a low dropout regulator with a lower potential difference between the input node and the output node is required. In this way, low-potential difference operation can reduce energy loss and heat dissipation.

[0004] The operating speed of high-speed input-output (IO) circuits is getting faster and faster. Using an external low dropout regulator to stabilize the voltage source node of a high-speed IO circuit requires an external capacitor. However, low dropout regulators without capacitors are often used in applications. When using a low dropout regulator without a capacitor, the drain node current will cause voltage noise jitter. Summary of the Invention

[0005] An embodiment of the present invention provides a voltage regulation system, including a voltage regulator and an overshoot and undershoot regulation circuit. The voltage regulator includes a gate terminal having a gate voltage and an output terminal having an output voltage. The overshoot and undershoot regulation circuit includes an inverting amplifier and a capacitor. The inverting amplifier has an output terminal for outputting a feedback voltage in response to a change in the output voltage. The capacitor has a first terminal coupled to the gate terminal and a second terminal coupled to the output terminal of the inverting amplifier.

[0006] Another embodiment of the present invention provides a voltage regulation system, including a voltage regulator and an overshoot and undershoot regulation circuit. The voltage regulator includes a gate terminal having a gate voltage and an output terminal having an output voltage. The overshoot and undershoot regulation circuit includes a first inverting amplifier, a second inverting amplifier, and a capacitor. The first inverting amplifier is coupled to the output terminal to receive the output voltage. The second inverting amplifier is coupled to an output terminal of the first inverting amplifier and has an output terminal for outputting a feedback voltage in response to a change in the output voltage. The capacitor has a first terminal coupled to the gate terminal and a second terminal coupled to the output terminal of the second inverting amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a schematic diagram of a voltage regulation system according to an embodiment of the present invention.

[0008] Figure 2 FIG. is a schematic diagram of a voltage regulation system according to another embodiment of the present invention.

[0009] Figure 3 is Figure 1 the simulation result of the voltage regulation system.

[0010] DESCRIPTION OF REFERENCE NUMERALS:

[0011] 100, 200: Voltage regulation system

[0012] 101, 201: Voltage regulator

[0013] 102, 202: Operational amplifier

[0014] 103, 203: Overshoot and undershoot regulation circuit

[0015] 104, 116, 118, 204, 218, 220, 222, 224: Transistor

[0016] 106, 108, 206, 208: Resistor

[0017] 110, 210, 212: Inverting amplifier

[0018] 112, 214: Capacitor

[0019] 114, 216: Load

[0020] 300: Simulation result DETAILED DESCRIPTION

[0021] Figure 1FIG. 0 is a schematic diagram of a voltage regulation system 100 according to an embodiment of the present invention. The voltage regulation system 100 includes a voltage regulator 101 and an overshoot and undershoot regulation circuit 103. In an embodiment of the present invention, the voltage regulator 101 may be a low dropout regulator (LDO), which has an output node and a gate node for outputting an output voltage Vout and a gate voltage Vdrv, respectively. The voltage regulator 101 includes an operational amplifier 102, a transistor 104, a first resistor 106, and a second resistor 108. The overshoot and undershoot regulation circuit 103 includes an inverting amplifier 110 and a capacitor 112 connected in series. The overshoot and undershoot regulation circuit 103 is coupled between the output node and the gate node of the voltage regulator 101.

[0022] The operational amplifier 102 includes a positive terminal for receiving a reference voltage Vref, a negative terminal, and an output terminal. The transistor 104 (N-type) includes a gate terminal coupled to the output terminal of the operational amplifier 102 to receive the gate voltage Vdrv, a drain terminal for receiving a power supply voltage Vdd, and a source terminal (i.e., the output terminal of the operational amplifier) for outputting the output voltage Vout. The load circuit 114 may use the output voltage Vout as a supply voltage. The first resistor 106 includes a first terminal coupled to the negative terminal of the operational amplifier 102 and a second terminal coupled to a ground terminal. The second resistor 108 includes a first terminal coupled to the source terminal of the transistor 104 and a second terminal coupled to the first terminal of the first resistor 106 (i.e., the negative terminal of the operational amplifier 102).

[0023] The inverting amplifier 110 includes an input terminal coupled to the source terminal of the transistor 104, an output terminal for outputting a feedback voltage in response to a change in the output voltage Vout of the voltage regulator 101, a power supply terminal for receiving the power supply voltage Vdd, and a ground terminal coupled to the ground terminal. The capacitor 112 includes a first terminal coupled to the gate terminal of the transistor 104 (i.e., the output terminal of the operational amplifier 102) and a second terminal coupled to the output terminal of the inverting amplifier 110. In another embodiment, the resistor 108 may be omitted. When the second resistor 108 is removed, the first terminal of the first resistor 106 is coupled to the source terminal of the transistor 104 and the negative terminal of the operational amplifier 102.

[0024] The inverting amplifier 110 further includes a P-type transistor 116 and an N-type transistor 118. The P-type transistor 116 includes a gate terminal coupled to the source terminal of the transistor 104, a source terminal for receiving the power supply voltage Vdd, and a drain terminal coupled to the second terminal of the capacitor 112. The N-type transistor 118 includes a gate terminal coupled to the source terminal of the transistor 104, a drain terminal coupled to the drain of the P-type transistor 116, and a source terminal coupled to the ground terminal.

[0025] By setting the inverting amplifier 110 in the voltage regulation system 100, the jitter of the output voltage Vout will be quickly fed back to the gate terminal of the transistor 104 through the inverting amplifier 110 and the capacitor 112. Therefore, the analog feedback circuit including the inverting amplifier 110 and the capacitor 112 can reduce the jitter in the output voltage Vout. Compared with the digital circuit solution, the analog feedback circuit immediately responds to the jitter to stabilize the voltage regulation system 100 and does not require a control clock signal.

[0026] Figure 2 FIG. 4 is a voltage regulation system 200 according to another embodiment of the present invention, including a voltage regulator 201 and an overshoot and undershoot regulation circuit 203. In an embodiment of the present invention, the voltage regulator 201 may be a low dropout regulator (LDO), which has an output terminal and a gate terminal for outputting an output voltage Vout and a gate voltage Vdrv, respectively. The voltage regulator 201 includes an operational amplifier 202, a transistor 204, a first resistor 206, and a second resistor 208. The overshoot and undershoot regulation circuit 203 includes a first inverting amplifier 210, a second inverting amplifier 212, and a capacitor 214 connected in series. The overshoot and undershoot regulation circuit 203 is connected between the output terminal and the gate terminal of the voltage regulator 201.

[0027] The operational amplifier 202 includes a positive terminal for receiving a reference voltage Vref, a negative terminal, and an output terminal for outputting a gate voltage Vdrv. The transistor 204 includes a gate terminal coupled to the output terminal of the operational amplifier 202, a source terminal for receiving a power supply voltage Vdd, and a drain terminal for outputting an output voltage Vout. The first resistor 206 includes a first terminal coupled to the negative node of the operational amplifier 202 and a second terminal coupled to the ground terminal. The second resistor 208 includes a first terminal coupled to the drain terminal of the transistor 204 and a second terminal coupled to the first terminal of the first resistor 206. The first inverting amplifier 210 includes an input terminal 204 (i.e., the output terminal of the voltage regulator 201) coupled to the drain terminal of the transistor, an output terminal, a power supply terminal for receiving the power supply voltage Vdd, and a ground terminal coupled to the ground terminal. The second inverting amplifier 212 includes an input terminal coupled to the output terminal of the first inverting amplifier 210, an output terminal for outputting a feedback voltage in response to a change in the output voltage of the voltage regulator 201, a power supply terminal for receiving the power supply voltage Vdd, and a ground terminal coupled to the ground terminal. The capacitor 214 includes a first terminal coupled to the output terminal of the operational amplifier 202 and a second terminal coupled to the output terminal of the second inverting amplifier 212. The load 216 includes a first terminal coupled to the drain terminal of the transistor 204 and a second terminal coupled to the ground terminal.

[0028] In one embodiment, the transistor 204 is a P-type transistor. The first inverter amplifier 210 further includes a first P-type transistor 218 and a first N-type transistor 220. The first P-type transistor 218 includes a gate terminal coupled to the drain terminal of the transistor 204, a source terminal for receiving the power supply voltage Vdd, and a drain terminal coupled to the input terminal of the second inverter amplifier 212. The first N-type transistor 220 includes a gate terminal coupled to the drain terminal of the transistor 204, a drain terminal coupled to the drain terminal of the first P-type transistor 218, and a source terminal coupled to the ground terminal. The second inverter amplifier 212 further includes a second P-type transistor 222 and a second N-type transistor 224. The second P-type transistor 222 includes a gate terminal coupled to the output terminal of the first inverter amplifier 210, a source terminal for receiving the power supply voltage Vdd, and a drain terminal coupled to the second terminal of the capacitor 214. The second N-type transistor 224 includes a gate terminal coupled to the output terminal of the first inverter amplifier 210, a drain terminal coupled to the output terminal of the first inverter amplifier 210, and a source terminal coupled to the ground terminal.

[0029] By setting the first inverter amplifier 210 and the second inverter amplifier 212 in the voltage regulation system 200, the jitter of the output voltage Vout will be fed back to the gate terminal of the transistor 204 through the first inverter amplifier 210, the second inverter amplifier 212, and the capacitor 214. Therefore, the jitter in the output voltage Vout can be reduced by the analog feedback circuit including the first inverter amplifier 210, the second inverter amplifier 212, and the capacitor 214. Different from the digital circuit solution, the analog feedback circuit responds to the jitter in a timely manner and immediately stabilizes the voltage regulation system 200.

[0030] Figure 3 It is the simulation result 300 of the voltage regulation system 100 including the voltage regulator 101 and the overshoot and undershoot regulation circuit 103. The solid line and the dashed line respectively represent the relationship between the output voltage and time of the voltage regulation system 100 of the present invention and the prior art. The dashed line shows obvious jitter, while the solid line shows only slight jitter. The simulation result 300 indicates that by using the voltage regulation system 100, the jitter of the output voltage can be significantly reduced. Moreover, the analog feedback circuit can respond to the jitter immediately and has a faster compensation speed than using a digital feedback circuit.

[0031] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. A voltage regulation system, comprising: A voltage regulator includes a gate terminal having a gate voltage, and an output terminal having an output voltage; and An overshoot and undershoot regulation circuit, comprising: an inverting amplifier having an output terminal for outputting a feedback voltage in response to a change in the output voltage; and A capacitor has a first terminal coupled to the gate terminal and a second terminal coupled to the output terminal of the inverting amplifier.

2. The voltage regulation system as claimed in claim 1, wherein the voltage regulator further comprises: An operational amplifier, comprising: a positive electrode for receiving a reference voltage; a negative electrode coupled to the output terminal of the voltage regulator; and an output terminal coupled to the gate terminal; A transistor comprising: the gate terminal; a drain terminal for receiving a power supply voltage; and a source terminal coupled to the output terminal of the voltage regulator; and A first resistor, comprising: a first terminal coupled to the negative terminal of the operational amplifier; and A second terminal is coupled to a ground terminal.

3. The voltage regulation system as claimed in claim 1, wherein the voltage regulator further comprises: An operational amplifier, comprising: a positive electrode for receiving a reference voltage; a negative electrode; and an output terminal coupled to the gate terminal; A transistor comprising: the gate terminal; a drain terminal for receiving a power supply voltage; and a source terminal coupled to the output terminal of the voltage regulator; A first resistor, comprising: a first terminal coupled to the negative terminal of the operational amplifier; and a second terminal coupled to a ground terminal; and A second resistor comprising: a first terminal coupled to the source terminal of the transistor; and A second terminal is coupled to the first terminal of the first resistor.

4. The voltage regulating system as claimed in claim 2 or 3, wherein the transistor is an N-type transistor.

5. The voltage regulation system as claimed in claim 1, further comprising: A load, including: a first terminal coupled to the output terminal of the voltage regulator; and A second terminal is coupled to a ground terminal.

6. A voltage regulation system, comprising: A voltage regulator includes a gate terminal having a gate voltage, and an output terminal having an output voltage; and An overshoot and undershoot regulation circuit, comprising: a first inverting amplifier, coupled to the output terminal, for receiving the output voltage; a second inverting amplifier, coupled to an output terminal of the first inverting amplifier, having an output terminal for outputting a feedback voltage in response to a change in the output voltage; and A capacitor has a first terminal coupled to the gate terminal and a second terminal coupled to the output terminal of the second inverting amplifier.

7. The voltage regulation system as claimed in claim 6, wherein the voltage regulator further comprises: An operational amplifier, comprising: a positive electrode for receiving a reference voltage; a negative electrode coupled to the output terminal of the voltage regulator; and an output terminal coupled to the gate terminal; A transistor comprising: the gate terminal; a source terminal for receiving a power supply voltage; and a drain terminal coupled to the output terminal of the voltage regulator; and A first resistor, comprising: a first terminal coupled to the negative terminal of the operational amplifier; and A second terminal is coupled to a ground terminal.

8. The voltage regulation system as claimed in claim 6, wherein the voltage regulator further comprises: An operational amplifier, comprising: a positive electrode for receiving a reference voltage; a negative electrode; and an output terminal coupled to the gate terminal; A transistor comprising: the gate terminal; a source terminal for receiving a power supply voltage; and a drain terminal coupled to the output terminal of the voltage regulator; A first resistor, comprising: a first terminal coupled to the negative terminal of the operational amplifier; and a second terminal coupled to a ground terminal; and A second resistor comprising: a first terminal coupled to the drain terminal of the transistor; and A second terminal is coupled to the first terminal of the first resistor.

9. The voltage regulating system as claimed in claim 7 or 8, wherein the transistor is a P-type transistor.

10. The voltage regulation system as claimed in claim 6, further comprising: A load, including: a first terminal coupled to the output terminal of the voltage regulator; and A second terminal is coupled to a ground terminal.

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