Instruction processing method and device, electronic equipment, chip and storage medium

Abstract

The invention provides an instruction processing method and device, electronic equipment, a chip and a storage medium, and the method comprises the steps: employing a first branch predictor to predict the branch direction of a current instruction in response to the current instruction being a conditional branch instruction, so as to obtain a first prediction result; wherein the first prediction result is used for indicating whether jumping occurs or not after the current instruction is executed; in response to the current instruction being a cyclic branch instruction, predicting the branch direction of the current instruction by adopting a second branch predictor to obtain a second prediction result; wherein the second prediction result is used for indicating whether jumping occurs or not after the current instruction is executed; and in response to the fact that the second prediction result is different from the first prediction result, the second prediction result is adopted to correct the first prediction result, so that the accuracy of the first prediction result is improved, and based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to an instruction processing method, apparatus, electronic device, chip, and storage medium. Background Art

[0002] With the increasing complexity of programs, the effective processing of branch instructions has become a core factor restricting the performance improvement of processors; when processing these complex and variable branch instructions, the processor needs to quickly and accurately predict whether it will continue to jump to avoid delays caused by waiting for the result of conditional judgment. This prediction ability is crucial for maintaining high throughput and low latency of the processor. Summary of the Invention

[0003] The present disclosure aims to solve one of the technical problems in the related art to a certain extent.

[0004] To this end, the present disclosure provides an instruction processing method, apparatus, electronic device, chip, and storage medium. First, when the current instruction is a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result; further, when the current instruction is a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result. When the second prediction result is different from the first prediction result, the second prediction result is used to correct the first prediction result, improving the accuracy of the first prediction result. Based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

[0005] An embodiment of one aspect of the present disclosure provides an instruction processing method, including:

[0006] In response to the current instruction being a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result, where the first prediction result is used to indicate whether the current instruction jumps;

[0007] In response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result, where the second prediction result is used to indicate whether the loop branch instruction jumps;

[0008] In response to the second prediction result being different from the first prediction result, the second prediction result is used to correct the first prediction result.

[0009] An embodiment of another aspect of the present disclosure provides an instruction processing apparatus, including:

[0010] A first prediction module, configured to, in response to the current instruction being a conditional branch instruction, predict the branch direction of the current instruction by using a first branch predictor to obtain a first prediction result; wherein, the first prediction result is used to indicate whether the current instruction jumps;

[0011] A second prediction module, configured to, in response to the current instruction being a loop branch instruction, predict the branch direction of the current instruction by using a second branch predictor to obtain a second prediction result; wherein, the second prediction result is used to indicate whether the loop branch instruction jumps;

[0012] A correction module, configured to, in response to the second prediction result being different from the first prediction result, correct the first prediction result by using the second prediction result.

[0013] Another embodiment of the present disclosure provides an electronic device, including: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the instruction processing method as described in the foregoing embodiment of one aspect.

[0014] Another embodiment of the present disclosure provides a chip, including a processing circuit configured to execute the instruction processing method as described in the foregoing embodiment of one aspect.

[0015] Another embodiment of the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the instruction processing method as described in the foregoing embodiment of one aspect.

[0016] Another embodiment of the present disclosure provides a computer program product, on which a computer program is stored, and when the program is executed by a processor, it implements the instruction processing method as described in the foregoing embodiment of one aspect.

[0017] For the instruction processing method provided by the present disclosure, in response to the current instruction being a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result; wherein, the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result being different from the first prediction result, the second prediction result is used to correct the first prediction result. Thus, the accuracy of the first prediction result is improved, and based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

[0018] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned by practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a schematic flowchart of an instruction processing method provided by an embodiment of the present disclosure;

[0021] Figure 2 is a schematic flowchart of another instruction processing method provided by an embodiment of the present disclosure;

[0022] Figure 3 is a schematic flowchart of another instruction processing method provided by an embodiment of the present disclosure;

[0023] Figure 4 is a schematic diagram of the principle of an instruction processing method provided by an embodiment of the present disclosure Figure 1 ;

[0024] Figure 5 is a schematic diagram of the principle of an instruction processing method provided by an embodiment of the present disclosure Figure 2 ;

[0025] Figure 6 is a schematic diagram of the principle of an instruction processing method provided by an embodiment of the present disclosure Figure 3 ;

[0026] Figure 7 is a schematic diagram of a loop entry provided by an embodiment of the present disclosure;

[0027] Figure 8 is a schematic structural diagram of an instruction processing apparatus provided by an embodiment of the present disclosure;

[0028] Figure 9 is a block diagram of an electronic device provided by an embodiment of the present disclosure;

[0029] Figure 10 is a schematic structural diagram of a chip proposed by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0031] In the related art, the branch prediction accuracy of most processors has been above 90%. However, loop termination prediction often makes incorrect predictions. Therefore, loop termination mispredictions may account for a large proportion of the remaining branch mispredictions. The Tagged Geometric History Length (TAGE) branch predictor is a very effective branch predictor that combines the advantages of multiple predictors. However, the prediction results of TAGE are generally unsatisfactory when the loop terminates.

[0032] In the related art, during loop termination prediction, it mainly includes the following two aspects. First, a conditional branch instruction with a negative offset is considered a loop branch instruction. However, using a loop predictor to predict all conditional branch instructions with negative offsets will inevitably increase power consumption, which is not conducive to the implementation of high-performance processors. On the other hand, a large number of data structures are used to record the characteristics of the loop body to predict the jump direction of each loop branch instruction. The design complexity of predicting all loop branch instructions is higher than that of only predicting loop termination instructions, which is not conducive to implementation in high-performance processors.

[0033] In view of the above problems, the present disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium.

[0034] The instruction processing method, apparatus, electronic device, chip, and storage medium according to the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0035] Figure 1 It is a flowchart of an instruction processing method provided by an embodiment of the present disclosure.

[0036] In this embodiment, the instruction processing method is configured as an instruction processing apparatus for illustration. The code update apparatus can be applied to any electronic device with computing capabilities so that the electronic device can execute the instruction processing function.

[0037] As Figure 1 shown, the instruction processing method may include the following steps:

[0038] Step 101, in response to the current instruction being a conditional branch instruction, use a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result;

[0039] The first prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0040] A conditional branch instruction is an instruction that determines the program execution path according to a specific condition. Conditional branch instructions include loop branch instructions and other types of conditional branch instructions (such as if-else instructions, switch instructions, etc.).

[0041] In an embodiment of the present disclosure, when the current instruction is a conditional branch instruction, a first branch predictor is used to predict the branch direction of the current instruction to obtain a first prediction result, where the first prediction result is used to indicate whether a jump occurs after the current instruction is executed. A jump means that instead of sequentially executing the next instruction of the current instruction, it will jump to another address to continue execution; no jump means that the next instruction will continue to be executed sequentially without jumping to other addresses. It should be noted that, in order to improve the accuracy of branch prediction, the first branch predictor can be, for example, a TAGE predictor.

[0042] Step 102, in response to the current instruction being a loop branch instruction, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result.

[0043] The second prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0044] In an embodiment of the present disclosure, when the current instruction is a loop branch instruction among conditional branch instructions, a second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result, where the second prediction result is used to indicate whether a jump occurs after the current instruction is executed. A jump means that the current execution process loop of the innermost loop in the multi-level nested loop where the current instruction is located has not terminated, and no jump means that the current execution process loop of the innermost loop in the multi-level nested loop where the current instruction is located has terminated.

[0045] It should be noted that, in order to improve the accuracy of loop termination prediction, in an embodiment of the present disclosure, the second branch predictor can be, for example, a loop termination predictor.

[0046] Step 103, in response to the second prediction result being different from the first prediction result, the second prediction result is used to correct the first prediction result.

[0047] In order to improve the accuracy of branch prediction, in an embodiment of the present disclosure, when the second prediction result is different from the first prediction result, the second prediction result is used to correct the first prediction result.

[0048] In order to improve the accuracy of loop termination prediction, in an embodiment of the present disclosure, when the second prediction result indicates that no jump occurs after execution, but the first prediction result indicates that a jump occurs after the current instruction is executed, the second prediction result is used to correct the first prediction result, and the corrected first prediction result indicates that no jump occurs after the current instruction is executed.

[0049] The instruction processing method according to an embodiment of the present disclosure, in response to the current instruction being a conditional branch instruction, uses a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, uses a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein, the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result being different from the first prediction result, uses the second prediction result to correct the first prediction result. Thus, the accuracy of the first prediction result is improved, and based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

[0050] To clearly illustrate how the second prediction result is generated in the above embodiments, the present disclosure proposes another instruction processing method.

[0051] Figure 2 It is a flowchart of another instruction processing method provided by an embodiment of the present disclosure.

[0052] As Figure 2 shown, the generation steps of the second prediction result are as follows:

[0053] Step 201, in response to the current instruction being a loop branch instruction in a multi-layer nested loop, query the current iteration count of the current execution process of the innermost loop in which the current instruction is located in the multi-layer nested loop.

[0054] In an embodiment of the present disclosure, when the current instruction is a loop branch instruction in a multi-layer nested loop, query the current iteration count of the current execution process of the innermost loop in which the current instruction is located in the multi-layer nested loop to obtain the current iteration count, that is, the number of iterations that the innermost loop variable (such as k) has completed in the current execution process.

[0055] Step 202, in response to the current iteration count being equal to the target count, determine whether the value of the confidence bit is the first target value.

[0056] Wherein, the target count is determined according to the first iteration count of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process terminates the loop.

[0057] To reduce the complexity of branch prediction, as a possible implementation, only the loop termination is predicted. In the embodiments of the present disclosure, when the current iteration count is equal to the target count, it is determined whether the value of the confidence bit is the first target value; wherein, the target count is determined according to the first iteration count of the first complete execution process of the innermost loop. For example, the target count is the iteration count of the first complete execution process of the innermost loop; the value of the confidence bit is used to indicate whether the current execution process is loop-terminated. For example, the value of the confidence bit being the first target value is used to indicate that the current execution process is loop-terminated, and the value of the confidence bit being the second target value is used to indicate that the current execution process is not loop-terminated.

[0058] Among them, it should be noted that when the current iteration count is not equal to the target count, the use of the second branch predictor to predict the branch direction of the current instruction is rejected, or the generation of the second prediction result is rejected.

[0059] When the value of the confidence bit is the second target value, a second prediction result indicating a jump after the current instruction is executed is generated, that is, it indicates that the current execution process is not loop-terminated; or, the use of the second branch predictor to predict the branch direction of the current instruction is rejected; or, the generation of the second prediction result is rejected.

[0060] As a possible implementation, before determining whether the value of the confidence bit is the first target value, the confidence bit needs to be assigned a value.

[0061] As an example, in response to the current instruction being a loop branch instruction in the non-first complete execution process of the innermost loop of a multi-layer nested loop, the first iteration count of the first complete execution process is obtained; the iteration count of the non-first complete execution process is counted to obtain the second iteration count of the non-first complete execution process; in response to the second iteration count being the same as the first iteration count, the decoding result of the current instruction is obtained; and the confidence bit is assigned a value according to the decoding result of the current instruction.

[0062] That is to say, for the loop branch instruction in the non-first complete execution process of the innermost loop in a multi-layer nested loop, obtain the first iteration count (also known as loop count) of the first complete execution process. For example, taking a 3-layer nested loop as an example, i is the index of the outermost loop, j is the index of the middle layer loop, and k is the index of the innermost loop. Among them, the number of times of the outermost loop is 10 times, that is, i ranges from 0 to 9, the number of times of the middle layer loop is 10 times, that is, j ranges from 0 to 9, and the number of times of the innermost loop is 10 times, that is, k ranges from 0 to 9. When i = 0, j = 0, and k ranges from 0 to 9, it is the first complete execution process of the innermost loop, and the loop count of the first complete execution process is 10 times. The execution processes other than this first complete execution process in the multi-layer nested loop are non-first complete execution processes. For any non-first complete execution process, count the iteration count of this non-first complete execution process to obtain the second iteration count of the non-first complete execution process. When the second iteration count is the same as the loop count, obtain the decoding result obtained by the instruction decoding unit for decoding the current instruction. Furthermore, based on the decoding result, assign a value to the confidence bit. Among them, the value of the confidence bit is determined by the following steps:

[0063] 1. In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, determine that the value of the confidence bit is the first target value.

[0064] In the embodiment of the present disclosure, when the iteration count is equal to the loop count and the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, it means that the non-first complete execution process loop of the innermost loop where the current instruction is located terminates. At this time, set the value of the confidence bit to the first target value (for example, 1).

[0065] 2. In response to the decoding result of the current instruction indicating that a jump occurs after the current instruction is executed, determine that the value of the confidence bit is the second target value.

[0066] In the embodiment of the present disclosure, when the decoding result of the current instruction indicates that a jump occurs after the current instruction is executed, it means that the non-first complete execution process loop of the innermost loop where the current instruction is located does not terminate. At this time, set the value of the confidence bit to the second target value (for example, 0).

[0067] To save resources, as another possible implementation, for a loop branch instruction during the second complete execution of the innermost loop in a multi-level nested loop, when the iteration count in the second complete execution is the same as the loop count, obtain the decoding result of the current instruction, and assign a confidence bit according to the decoding result of the current instruction. At the end of each complete execution after the second complete execution of the innermost loop, check whether the value of the confidence bit is the first target value, and when the value of the confidence bit is the first target value, correct the first prediction result.

[0068] Among them, it should be noted that the first iteration count of the first complete execution is determined by the following steps: in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, determine that the current instruction is the last loop branch instruction in the first complete execution; determine the first iteration count according to the first loop branch instruction and the last loop branch instruction in the first complete execution.

[0069] That is to say, when the current instruction is a loop branch instruction in the first complete execution of the innermost loop, the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, which means that the current instruction is the last loop branch instruction in the first complete execution of the innermost loop. Furthermore, according to the first loop branch instruction and the last loop branch instruction in the first complete execution, the loop count of the first complete execution of the innermost loop, that is, the loop count, can be determined.

[0070] To improve the data access efficiency, in the embodiments of the present disclosure, the loop count, the current iteration count, and the value of the confidence bit of the loop branch instructions in the same multi-level nested loop are located in the same loop entry. Among them, it should be noted that the instruction addresses of the loop branch instructions in the same multi-level nested loop are the same. For the convenience of instruction access, the instruction address of the corresponding loop branch instruction can also be stored in the loop entry.

[0071] In addition, to save resources while meeting the user's requirements, the number of loop entries can be set to a specified number. For example, the number of loop entries is 4.

[0072] Step 203, in response to the value of the confidence bit being the first target value, generate a second prediction result for indicating that no jump occurs after the current instruction is executed.

[0073] Among them, the first target value is used to indicate the termination of the current execution process loop.

[0074] In an embodiment of the present disclosure, when the value of the confidence bit is the first target value, obtain the prediction result of the second branch predictor for predicting the current instruction, that is, use the loop termination prediction result of the innermost non-first complete execution process to be generated as the second prediction result.

[0075] To achieve effective management of loop entries, in an embodiment of the present disclosure, the same loop entry further includes the count value of the counter corresponding to the loop branch instruction in the same multi-layer nested loop. After correcting the first prediction result using the second prediction result, when the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, and the second prediction result indicates that no jump occurs after the current instruction is executed, increment the calculated value of the counter corresponding to the current instruction; when the decoding result of the current instruction indicates that no jump occurs after the current instruction is executed, and the second prediction result indicates that a jump occurs after the current instruction is executed, decrement the count value of the counter corresponding to the current instruction, and when the count value corresponding to the current instruction reaches a set value (for example, the count value is 0), delete the loop entry corresponding to the current instruction, that is, when the count value of the counter is the set value, it means that the information recorded in the loop entry has low utilization value, and delete the information in the loop entry to prepare for the next loop termination prediction.

[0076] Exemplarily, the counter includes an aging counter.

[0077] The instruction processing method of the embodiment of the present disclosure, in response to the current instruction being a loop branch instruction in a multi-layer nested loop, queries the current iteration number of the current execution process of the innermost loop in which the current instruction is located in the multi-layer nested loop; in response to the current iteration number being equal to the target number, determines whether the value of the confidence bit is the first target value; wherein, the target number is determined according to the first iteration number of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process terminates the loop; thereby, realizing only predicting the prediction result of loop termination, reducing the prediction complexity, and when the value of the confidence bit is the first target value, using the prediction result of loop termination to correct the first prediction result, improving the accuracy of the first prediction result, and avoiding performance loss caused by misprediction.

[0078] To clearly illustrate how to confirm whether the current instruction is a loop branch instruction in the above embodiment, the present disclosure proposes another instruction processing method.

[0079] Figure 3 It is a flowchart of another instruction processing method provided by the embodiment of the present disclosure.

[0080] As Figure 3 shown, the instruction processing method may include the following steps:

[0081] Step 301, in response to the current instruction being a conditional branch instruction, use a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result.

[0082] Among them, the first prediction result is used to indicate whether a jump occurs after the current instruction is executed.

[0083] Step 302, in response to the current instruction having a loop feature, write the current instruction into the instruction queue.

[0084] In the embodiment of the present disclosure, the instruction features of the current instruction are identified, and the instruction features of the current instruction are obtained. Furthermore, it is determined whether the instruction features include a loop feature. When the instruction features include a loop feature, it indicates that the current instruction has a loop feature, and the current instruction is written into the instruction queue.

[0085] Step 303, determine whether the current instruction is a loop branch instruction according to the decoding result of the current instruction.

[0086] In order to further determine whether the current instruction is a loop branch instruction, in the embodiment of the present disclosure, a decoding unit is used to decode the current instruction to obtain the decoding result of the current instruction, and the decoding result is analyzed to determine whether the current instruction is a loop branch instruction.

[0087] Step 304, in response to the current instruction being a loop branch instruction, read the current instruction from the instruction queue.

[0088] As an example for filtering non-loop branch instructions, when the current instruction is a loop branch instruction, the current instruction is read from the instruction queue.

[0089] As another example, when the current instruction is not a loop branch instruction, the current instruction is not read from the instruction queue.

[0090] Thus, it is realized that only when the current instruction is a loop branch instruction, the current instruction is input into the second branch predictor, reducing unnecessary power consumption.

[0091] Step 305, use a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result.

[0092] Furthermore, use a second branch predictor to predict the branch direction of the current instruction read from the instruction queue to obtain a second prediction result.

[0093] Step 306, in response to the second prediction result being different from the first prediction result, use the second prediction result to correct the first prediction result.

[0094] It should be noted that the execution processes of step 301 and step 306 can be implemented in any one of the embodiments of the present disclosure. The embodiments of the present disclosure do not limit this and will not be elaborated further.

[0095] For the instruction processing method of the embodiments of the present disclosure, in response to the current instruction having a loop feature, the current instruction is written into the instruction queue; according to the decoding result of the current instruction, it is determined whether the current instruction is a loop branch instruction; in response to the current instruction being a loop branch instruction, the current instruction is read from the instruction queue; the second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result. Thus, non-loop branch instructions can be effectively filtered, preventing non-loop branch instructions from entering the second branch predictor, reducing unnecessary power consumption, and improving resource utilization.

[0096] In any embodiment of the present disclosure, as Figure 4 shown, taking the first branch predictor as the TAGE predictor and the second branch predictor as the loop termination predictor, and taking the processor in the electronic device executing the instruction processing method as an example, the instruction processing method of the embodiments of the present disclosure can also be implemented based on the following steps:

[0097] 1. When performing branch prediction, when it is found that the current instruction has a loop branch characteristic, the loop branch filter is opened, and the current instruction is written into the instruction queue to filter non-loop branch instructions. Through the decoding result of the current instruction, it is confirmed whether the instruction is a true loop branch instruction;

[0098] 2. If it is a loop branch instruction, the current instruction is read from the instruction queue, and the loop termination predictor is opened to start recording the characteristics of the loop branch instruction, and then a loop termination prediction result is given when the loop terminates;

[0099] 3. The prediction result of the loop termination is used to overwrite the prediction result of the TAGE predictor, so as to achieve the effect of correcting the TAGE prediction result with the loop termination prediction.

[0100] Specifically, as Figure 5 shown, the implementation of the instruction processing method is as follows:

[0101] 1. Instructions are stored in the memory 501. During the execution of the instructions by the processor, the instruction fetch unit 503 accesses the memory 501 through the instruction cache 502 to obtain instructions; among them, the instruction fetch unit 503 includes a branch predictor 504;

[0102] 2. The instruction decoder 505 decodes the instruction and transfers the decoded instruction and the data of the instruction decoding to the instruction execution unit 506;

[0103] 3. The instruction execution unit 506 is used to implement its functions according to specific instructions, such as addition, subtraction, multiplication, division operations, etc.

[0104] 4. The instruction fetch memory unit 507 is used to interact with the memory for data during the execution of the instruction execution unit.

[0105] 5. The instruction write-back unit 508 is used to write the execution result back to the memory after the instruction execution is completed.

[0106] Among them, as Figure 6 shown, the specific steps for the processor to execute instructions are as follows:

[0107] Step 601: When it is found in the instruction fetch stage that the instruction is a conditional branch instruction and the instruction has a loop characteristic, the instruction address of the instruction is pushed into the instruction queue FIFO. This FIFO serves to filter non-loop branch instructions; when it is determined in the instruction decoding stage that the instruction is a loop branch, the instruction address of the instruction is popped from the FIFO. It can be seen that if the instruction pushed into the FIFO is a loop branch instruction, this FIFO has no effect, but if the pushed instruction is not a loop branch instruction, the non-loop branch instruction will stay in the FIFO. When the FIFO is full, it will backpressure the upstream and no longer pour branch instructions with loop characteristics into the FIFO, and at the same time indicate that the previously poured instructions with loop characteristics are actually non-loop branch instructions. Therefore, the FIFO serves to filter non-loop branch instructions, which can ensure that not all branch instructions with loop characteristics enter the loop termination predictor, thereby reducing unnecessary power consumption expenses;

[0108] Step 602: For the loop branch instructions pushed into the FIFO, when the instruction decoding unit determines that it is a loop branch instruction and the TAGE branch predictor predicts incorrectly, the instruction address of the branch instruction is stored in Figure 7 the tag bit in the loop entry in the middle, and at this time it can be understood that the branch instruction is the first termination of the first complete execution process of the innermost loop in a multi-layer nested loop, and the loop count (the first iteration count) of the first complete execution process is obtained;

[0109] Among them, it should be noted that since the TAGE branch predictor performs branch prediction based on historical information, under normal circumstances, the branches within a loop are all jumps, but the conditional branch instruction at the end of the loop does not jump. Therefore, the TAGE can accurately predict the branch instructions within the loop, but generally cannot accurately predict at the end of the loop; when the loop branch instruction is pushed into the FIFO, the iteration count starts to be incremented (iteration count + 1). When a conditional branch instruction with the same instruction address as that in the entry appears again (i.e., the loop branch instruction during the non-first complete execution of the innermost loop), if the TAGE predictor predicts that the branch instruction will jump, and the instruction decoding unit also parses the conditional branch instruction as a jump, then the iteration count (current iteration count) in the entry needs to be incremented by 1; if the TAGE predictor predicts that the branch instruction will jump, but the instruction decoding unit parses the conditional branch instruction as not jumping, it means that the second complete execution of the innermost loop terminates. At this time, the iteration count needs to be assigned to the loop count in the entry to record the loop count of the loop body, and then the iteration count is cleared;

[0110] Among them, it should be noted that the TAGE predictor will predict incorrectly at the end of the first complete execution of the innermost loop. At this time, the processor starts to record the loop count of the loop body; when the loop enters the second complete execution of the innermost loop, the iteration counter is used for counting. When the second complete execution terminates, the TAGE will still predict incorrectly, but the instruction decoding unit will also give the correct jump result (i.e., no jump occurs after the conditional branch instruction at the end of the loop is executed). Since the iteration count records all the times from the previous loop termination to this loop termination, this iteration count is the loop count of this loop.

[0111] Step 603: When a conditional branch instruction with the same instruction address as that in the entry appears again, the iteration count starts to be counted and then compared with the loop count until the iteration count is equal to the loop count. Then, the value of the confidence bit is checked. If the confidence bit is not 1 (the first target value), and the instruction decoding unit parses that the conditional branch instruction does not jump after execution, then the value of the confidence bit is set to 1; otherwise, the value of the confidence bit is set to 0. When the value of the confidence bit is 0, no prediction result is given. If the value of the confidence bit is 1, it is considered that the loop termination has arrived, and a loop termination prediction message is given, that is, it is predicted that no jump occurs after the conditional branch instruction is executed, and this prediction result overwrites the prediction result of the TAGE, thus playing a role in correcting the prediction result of the TAGE with the prediction result of the loop termination predictor;

[0112] Step 604: When the prediction result of the loop termination predictor covers the TAGE prediction result, if the prediction result of the loop termination predictor is consistent with the result parsed by the instruction decoding unit, the aging count starts to accumulate. When the entry is newly allocated, the aging count is 7, and the maximum count value of the counter is 7. When the prediction result of the loop termination predictor is inconsistent with the result parsed by the instruction decoding unit, the count value of the counter decreases. When the count value of the counter decreases to 0, it means that the information recorded in this entry has no value for use, and then the information of this entry is cleared to prepare for the next loop prediction. As Figure 7 shown, setting a certain number (e.g., 4) of entries can achieve the result of loop termination prediction.

[0113] To implement the above embodiments, an instruction processing device is further proposed in the embodiments of the present disclosure.

[0114] Figure 8 FIG. is a schematic structural diagram of an instruction processing device provided in the embodiments of the present disclosure.

[0115] As Figure 8 shown, the instruction processing device 800 includes: a first prediction module 810, a second prediction module 820, and a correction module 830.

[0116] Among them, the first prediction module 810 is configured to, in response to the current instruction being a conditional branch instruction, use a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result, where the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; the second prediction module 820 is configured to, in response to the current instruction being a loop branch instruction, use a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result, where the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; the correction module 830 is configured to, in response to the second prediction result being different from the first prediction result, use the second prediction result to correct the first prediction result.

[0117] As a possible implementation manner, the second prediction result is generated by the following modules: a query module, a judgment module, and a generation module.

[0118] Among them, the query module is used to respond to the current instruction being a loop branch instruction in a multi-level nested loop, and query the current iteration count of the current execution process of the innermost loop in which the current instruction is located in the multi-level nested loop; the judgment module is used to respond to the current iteration count being equal to the target count, and judge whether the value of the confidence bit is the first target value; among them, the target count is determined according to the first iteration count of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process terminates the loop; the generation module is used to respond to the value of the confidence bit being the first target value, and generate a second prediction result for indicating that no jump occurs after the current instruction is executed; among them, the first target value is used to indicate that the current execution process terminates the loop.

[0119] As a possible implementation, the generation module is further used to respond to the value of the confidence bit being the second target value, and generate a second prediction result for indicating that a jump occurs after the current instruction is executed; among them, the second target value is used to indicate that the current execution process does not terminate the loop.

[0120] As a possible implementation, the instruction processing device 800 further includes: a rejection module.

[0121] Among them, the rejection module is used to respond to the current iteration count not being equal to the target count, and reject using the second branch predictor to predict the branch direction of the current instruction; or, respond to the value of the confidence bit being the second target value, and reject using the second branch predictor to predict the branch direction of the current instruction.

[0122] As a possible implementation, the instruction processing device 800 further includes: an assignment module.

[0123] Among them, the assignment module is used to respond to the current instruction being a loop branch instruction in the non-first complete execution process of the innermost loop in the multi-level nested loop, obtain the first iteration count of the first complete execution process; count the iteration count of the non-first complete execution process to obtain the second iteration count of the non-first complete execution process; respond to the second iteration count being the same as the first iteration count, obtain the decoding result of the current instruction; and assign a value to the confidence bit according to the decoding result of the current instruction.

[0124] As a possible implementation, the assignment module is used to respond to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, and determine that the value of the confidence bit is the first target value; respond to the decoding result of the current instruction indicating that a jump occurs after the current instruction is executed, and determine that the value of the confidence bit is the second target value.

[0125] As a possible implementation, the first iteration count is determined by the following modules: the first determination module and the second determination module.

[0126] Among them, the first determination module is configured to determine that the current instruction is the last loop branch instruction in the first complete execution process in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed; the second determination module is configured to determine the first iteration count according to the first loop branch instruction and the last loop branch instruction in the first complete execution process.

[0127] As a possible implementation manner, the values of the loop count, iteration count, and confidence bit of the loop branch instructions in the same multi-layer nested loop are located in the same loop entry.

[0128] As a possible implementation manner, the values of the first iteration count, current iteration count, and confidence bit corresponding to the loop branch instructions in the same multi-layer nested loop are located in the same loop entry. The instruction processing apparatus 800 further includes: an increment module, a decrement module, and a deletion module.

[0129] Among them, the increment module is configured to increment the calculated value of the counter corresponding to the current instruction in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed and the second prediction result indicating that no jump occurs after the current instruction is executed; the decrement module is configured to decrement the count value of the counter corresponding to the current instruction in response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed and the second prediction result indicating that a jump occurs after the current instruction is executed; the deletion module is configured to delete the loop entry corresponding to the current instruction in response to the count value corresponding to the current instruction reaching the set value.

[0130] As a possible implementation manner, the second prediction module 820 is configured to write the current instruction into the instruction queue in response to the current instruction having a loop feature; determine whether the current instruction is a loop branch instruction according to the decoding result of the current instruction; read the current instruction from the instruction queue in response to the current instruction being a loop branch instruction; and predict the branch direction of the current instruction by using the second branch predictor to obtain the second prediction result.

[0131] As a possible implementation manner, the correction module 830 is configured to correct the first prediction result by using the second prediction result in response to the second prediction result indicating that no jump occurs after the current instruction is executed and the first prediction result indicating that a jump occurs after the current instruction is executed.

[0132] The instruction processing device according to an embodiment of the present disclosure, in response to the current instruction being a conditional branch instruction, uses a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein, the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the current instruction being a loop branch instruction, uses a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein, the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; in response to the second prediction result being different from the first prediction result, uses the second prediction result to correct the first prediction result. Thus, the accuracy of the first prediction result is improved, and based on the accurate first prediction result, the performance loss caused by prediction errors can be reduced.

[0133] To implement the above embodiment, the present disclosure also proposes an electronic device, including a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the instruction processing method as described in the foregoing method embodiment.

[0134] To implement the above embodiment, the present disclosure also proposes a chip, the chip includes a processing circuit, and the processing circuit is configured to execute the instruction processing method as described in the foregoing method embodiment.

[0135] To implement the above embodiment, the present disclosure also proposes a computer-readable storage medium, in which computer-executable instructions are stored, and the computer-executable instructions are used to implement the instruction processing method as described in the foregoing method embodiment when executed by a processor.

[0136] To implement the above embodiment, the present disclosure also proposes a computer program product, on which a computer program is stored, and the computer program implements the instruction processing method as described in the foregoing method embodiment when executed by a processor.

[0137] Figure 9 It is a block diagram of an electronic device provided by an embodiment of the present disclosure. For example, the electronic device 900 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0138] Refer to Figure 9 , the electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0139] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0140] The memory 904 is configured to store various types of data to support the operation of the electronic device 900. Examples of such data include instructions for any application or method operating on the electronic device 900, contact data, phone book data, messages, pictures, videos, etc. The memory 904 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disks, or optical disks.

[0141] The power component 906 provides power to various components of the electronic device 900. The power component 906 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0142] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each of the front camera and the rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0143] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 904 or transmitted via the communication component 916. In some embodiments, the audio component 910 further includes a speaker for outputting audio signals.

[0144] The I / O interface 912 provides an interface between the processing component 902 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0145] The sensor component 914 includes one or more sensors for providing status assessments of various aspects of the electronic device 900. For example, the sensor component 914 can detect the on / off state of the electronic device 900, the relative positioning of components, such as the display and keypad of the electronic device 900. The sensor component 914 can also detect a change in the position of the electronic device 900 or a component of the electronic device 900, the presence or absence of user contact with the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and the temperature change of the electronic device 900. The sensor component 914 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 914 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 914 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0146] The communication component 916 is configured to facilitate communication between the electronic device 900 and other devices in a wired or wireless manner. The electronic device 900 can access a wireless network based on a communication standard, such as WiFi, 4G, or 5G, or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0147] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0148] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, and the above instructions can be executed by a processor 920 of the electronic device 900 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0149] Figure 10 is a schematic structural diagram of a chip proposed by an embodiment of the present disclosure. Reference may be made to Figure 10 the schematic structural diagram of the chip 1000 shown, but not limited thereto.

[0150] The chip 1000 includes a processing circuit 1001, and the processing circuit 1001 is configured to execute any of the above methods.

[0151] In some embodiments, the chip 1000 further includes one or more interface circuits 1002. Optionally, the interface circuit 1002 is connected to the memory 1003. The interface circuit 1002 may be used to receive signals from the memory 1003 or other devices, and the interface circuit 1002 may be used to send signals to the memory 1003 or other devices. For example, the interface circuit 1002 may read instructions stored in the memory 1003 and send the instructions to the processing circuit 1001.

[0152] In some embodiments, the interface circuit 1002 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1001 executes other steps.

[0153] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. may be used interchangeably.

[0154] In some embodiments, the chip 1000 further includes one or more memories 1003 for storing instructions. Optionally, all or part of the memories 1003 may be outside the chip 1000.

[0155] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0156] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0157] Any process or method description shown in a flowchart or described in other ways herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0158] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0159] It should be understood that various parts of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0160] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0161] In addition, each functional unit in various embodiments of the present disclosure may be integrated into one processing module, may exist separately as individual physical units, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0162] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A command processing method, characterized in that: include: In response to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; In response to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; In response to the second prediction result being different from the first prediction result, the first prediction result is corrected using the second prediction result.

2. The method according to claim 1, characterized in that The second prediction result is generated by the following steps: In response to the current instruction being a loop branch instruction in a multi-layer nested loop, querying a current iteration number of a current execution process of an innermost loop in which the current instruction is located in the multi-layer nested loop; In response to the current number of iterations being equal to the target number, determining whether the value of the confidence bit is a first target value; wherein the target number is determined based on the first number of iterations of the first complete execution process of the innermost loop, and the value of the confidence bit is used to indicate whether the current execution process is loop terminated; and / or, In response to the confidence bit value being a first target value, a second prediction result is generated for indicating that no jump occurs after the current instruction is executed; wherein the first target value is used to indicate that the current execution process loop is terminated.

3. The method according to claim 2, characterized in that The second prediction result is also generated by the following steps: In response to the confidence bit value being a second target value, a second prediction result is generated for indicating that a jump occurs after the current instruction is executed; wherein the second target value is used to indicate that the current execution process loop has not terminated.

4. The method according to claim 2, characterized in that: The method further comprises: In response to the current number of iterations not being equal to the target number, refusing to use the second branch predictor to predict the branch direction of the current instruction; or, In response to the confidence bit taking a second target value, the second branch predictor is rejected from being used to predict the branch direction of the current instruction.

5. The method according to claim 2, characterized in that: Before the step of judging whether the value of the confidence bit is the first target value in response to the current number of iterations being equal to the target number, the step of: In response to the current instruction being a loop branch instruction in a non-first complete execution process of an innermost loop in a multi-layer nested loop, obtaining a first iteration number of a first complete execution process; Counting the number of iterations of the non-first complete execution process to obtain the second number of iterations of the non-first complete execution process; In response to the second iteration number being the same as the first iteration number, obtaining a decoding result of the current instruction; The confidence bit is assigned a value according to a decoding result of the current instruction.

6. The method according to claim 5, characterized in that The assigning a value to the confidence bit according to the decoding result of the current instruction includes: In response to a decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, determining a value of the confidence bit to be a first target value; In response to the decoding result of the current instruction indicating that a jump occurs after the current instruction is executed, the value of the confidence bit is determined to be a second target value.

7. The method according to claim 5, characterized in that The first number of iterations is determined by the following steps: In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, determining that the current instruction is the last loop branch instruction in the first complete execution process; The first number of iterations is determined according to the first loop branch instruction and the last loop branch instruction in the first complete execution process.

8. The method according to claim 2, characterized in that: The first iteration number, current iteration number, and confidence bit values ​​corresponding to the loop branch instructions in the same multi-layer nested loop are located in the same loop entry.

9. The method according to claim 8, characterized in that The same loop entry also includes the count value of the counter corresponding to the loop branch instruction in the same multi-layer nested loop. After correcting the first prediction result by using the second prediction result, the method further includes: In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that no jump occurs after the current instruction is executed, incrementing the calculated value of the counter corresponding to the current instruction; In response to the decoding result of the current instruction indicating that no jump occurs after the current instruction is executed, and the second prediction result indicating that a jump occurs after the current instruction is executed, decrementing the count value of the counter corresponding to the current instruction; In response to the count value corresponding to the current instruction reaching a set value, the loop entry corresponding to the current instruction is deleted.

10. The method according to claim 1, characterized in that In response to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result includes: In response to the current instruction having a cyclic feature, writing the current instruction into an instruction queue; Determining whether the current instruction is a loop branch instruction according to a decoding result of the current instruction; In response to the current instruction being a loop branch instruction, reading the current instruction from the instruction queue; A second branch predictor is used to predict the branch direction of the current instruction to obtain a second prediction result.

11. The method according to claim 1, characterized in that: The first branch predictor includes a TAGE predictor, and the second branch predictor includes a loop termination predictor.

12. The method according to any one of claims 1 to 11, characterized in that In response to the second prediction result being different from the first prediction result, correcting the first prediction result using the second prediction result includes: In response to the second prediction result indicating that no jump occurs after the current instruction is executed, and the first prediction result indicating that a jump occurs after the current instruction is executed, the first prediction result is corrected using the second prediction result.

13. An instruction processing device, characterized in that: include: A first prediction module, configured to predict the branch direction of the current instruction using a first branch predictor in response to the current instruction being a conditional branch instruction, so as to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; A second prediction module, configured to predict the branch direction of the current instruction using a second branch predictor in response to the current instruction being a loop branch instruction, so as to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; A correction module is used for correcting the first prediction result by using the second prediction result in response to the second prediction result being different from the first prediction result.

14. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 11.

15. A chip, characterized in that: The chip comprises a processing circuit configured to perform the method according to any one of claims 1-12.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 12 when executed by a processor.

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