Digital integrated circuit layout stage buffer insertion prediction method, electronic equipment and storage medium
By adopting a machine learning-based buffer prediction model in the digital integrated circuit layout stage, learning the complex relationship between interconnect line delay and buffer insertion strategy, the problem of poor buffer type and position prediction in the existing technology is solved, and efficient design efficiency and iterative cycle reduction is achieved.
Patent Information
- Application Number
- CN202510262909.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-06-03
AI Technical Summary
The prior art is difficult to optimize the prediction of buffer type and position simultaneously, resulting in poor overall prediction results, and traditional machine learning models are difficult to capture complex timing and physical constraints.
Using a machine learning-based buffer prediction model, the complex relationship between interconnection line delay and buffer insertion strategy is learned from real circuit layout data, and the dependence relationship between circuit units is learned through static timing analysis and self-attention mechanism, combining multi-task learning to predict the type and position of buffers after layout.
It significantly improves design efficiency, reduces the design iteration cycle, and can efficiently complete the buffer type and position prediction of the layout stage, adapting to unknown circuit scenarios.
Smart Images
Figure CN120087316A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for predicting buffer insertion in the layout stage of digital integrated circuits, an electronic device, and a storage medium, belonging to the technical field of electronic design automation. Background Art
[0002] As the core pillar of modern industry, integrated circuits are developing rapidly towards the ultra-large scale direction with the continuous progress of process nodes. The continuous reduction of device size makes the interconnect delay gradually become the key bottleneck affecting timing convergence. The circuit delay mainly consists of two parts: interconnect delay and gate delay. However, with the continuous reduction of the process scale, the proportion of interconnect delay in the total delay has increased significantly. Therefore, optimizing the interconnect delay is of crucial significance for achieving efficient timing convergence.
[0003] The buffer insertion technology is one of the effective means to optimize the interconnect delay. By reasonably adding buffers in specific circuit paths, the interconnect delay of the critical path can be effectively reduced, thereby improving the timing performance of the circuit. In the layout stage of the physical design of digital integrated circuits, buffers are usually inserted frequently to optimize the timing. However, the circuit design in the layout stage is often accompanied by a large number of design iterations, and this frequent buffer insertion operation significantly increases the circuit design cycle and complexity, becoming a major challenge in integrated circuit design.
[0004] In recent years, with the rapid growth of digital technology and the demands of the integrated circuit industry, the traditional design methods have gradually revealed the problem of insufficient efficiency. Although Moore's Law is approaching its physical limit, researchers are still actively exploring new methods to improve the chip design quality. In this context, machine learning technology has shown great potential in the field of electronic design automation.
[0005] However, most of the existing machine learning methods adopt a single-task learning framework, which is difficult to optimize the prediction of buffer types and positions simultaneously, thus affecting the overall prediction effect. In addition, the traditional machine learning models have limited ability to model the global dependence relationship between circuit units and are difficult to capture complex timing and physical constraints. Summary of the Invention
[0006] Objective: In order to overcome the deficiencies existing in the prior art, the present invention provides a method for predicting buffer insertion in the layout stage of digital integrated circuits, an electronic device, and a storage medium. In the problem of predicting buffer insertion in the layout stage, the buffer prediction model based on machine learning can learn the complex relationship between the interconnect delay and the buffer insertion strategy from the real circuit layout data. The buffer prediction model of the present invention can not only efficiently complete the prediction of buffer types and positions in the layout stage, but also adapt to unknown circuit scenarios, thereby significantly improving the design efficiency and helping to achieve faster design convergence.
[0007] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:
[0008] In the first aspect, a method for predicting buffer insertion in the digital integrated circuit layout stage specifically includes:
[0009] Obtain the RTL circuit file, perform logic synthesis on the RTL circuit file to obtain the circuit netlist before layout, and perform backend physical design on the circuit netlist before layout to obtain the circuit netlist after layout.
[0010] Perform static timing analysis on the circuit netlist before layout to obtain the timing report before layout, and extract the physical information and timing information of the circuit units from the circuit netlist before layout and the timing report before layout respectively as the input feature sequence, and extract the type and position of the inserted buffers from the circuit netlist after layout as the label data.
[0011] Preprocess the input feature sequence to obtain the preprocessed input feature sequence, and use the preprocessed input feature sequence and the label data as sample data.
[0012] Use the sample data to train the buffer insertion prediction model in the layout stage to obtain the trained buffer insertion prediction model in the layout stage.
[0013] Input the input feature sequence of the circuit to be predicted into the trained buffer insertion prediction model in the layout stage, and output the type and position of the buffer.
[0014] As a preferred solution, the circuit units include all the circuit gate units between the start point and the end point of the timing path.
[0015] As a preferred solution, the physical information includes, but is not limited to, the number of unit fan-ins, the number of unit fan-outs, pin coordinates, rising capacitance, falling capacitance, and unit type.
[0016] As a preferred solution, the timing information includes, but is not limited to, unit propagation delay, timing margin, rising delay, falling delay, rising transition time, and falling transition time.
[0017] As a preferred solution, the preprocessing of the input feature sequence to obtain the preprocessed input feature sequence specifically includes:
[0018] Map the non-numerical features in the input feature sequence into discrete data.
[0019] Normalize the continuous numerical features in the input feature sequence to obtain normalized data.
[0020] Obtain the half-perimeter wire length between two units in the circuit unit.
[0021] The discrete data, the normalized data, and the half-cycle line length are combined to form a preprocessed input feature sequence corresponding to each circuit unit.
[0022] As a preferred solution, the lengths of the preprocessed input feature sequences corresponding to each circuit unit are the same.
[0023] As a preferred solution, the layout-phase buffer insertion prediction model includes: an encoder network, a buffer type prediction decoder, a buffer position prediction decoder, a first multi-layer perceptron, and a second multi-layer perceptron.
[0024] Among them, the encoder network includes: a word embedding layer, and the output end of the word embedding layer is sequentially connected to three encoders.
[0025] The encoders, the buffer type prediction decoder, and the buffer position prediction decoder have the same structure, and each includes: a first regularization layer, a self-attention mechanism layer, a first splicing layer, a second regularization layer, a feed-forward neural network, and a second splicing layer; the first regularization layer, the self-attention mechanism layer, the first splicing layer, the second regularization layer, the feed-forward neural network, and the second splicing layer are sequentially connected, the input end of the first regularization layer is further connected to the second input end of the first splicing layer, and the output end of the first splicing layer is further connected to the second input end of the second splicing layer.
[0026] The output end of the second splicing layer of the last encoder of the encoder network is respectively connected to the input ends of the first regularization layers of the buffer type prediction decoder and the buffer position prediction decoder.
[0027] The output end of the second splicing layer of the buffer type prediction decoder is connected to the first multi-layer perceptron.
[0028] The output end of the second splicing layer of the buffer position prediction decoder is connected to the second multi-layer perceptron.
[0029] The output end of the second splicing layer of the buffer type prediction decoder is further connected to the second input end of the self-attention mechanism layer of the buffer position prediction decoder.
[0030] In a second aspect, a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements a digital integrated circuit layout-phase buffer insertion prediction method as described in any one of the first aspects.
[0031] In a third aspect, a computer device includes:
[0032] A memory for storing instructions.
[0033] A processor for executing the instructions such that the computer device performs the operations of a digital integrated circuit layout stage buffer insertion prediction method as described in any one of the first aspect.
[0034] Beneficial effects: A digital integrated circuit layout stage buffer insertion prediction method, an electronic device, and a storage medium provided by the present invention. First, the physical design tool and the static timing analysis tool are used to perform physical design and static timing analysis on the circuit, and the timing and physical information of each unit before layout are extracted. Secondly, the dependency relationship between each unit of the circuit is learned through the self-attention mechanism, and combined with multi-task learning, the type and position of buffer insertion after layout are predicted.
[0035] Compared with the heuristic algorithm and the traditional machine learning algorithm, the present invention can efficiently predict the type and position of buffer insertion after layout before layout, so as to provide guidance for the early stage of digital integrated circuit design and significantly reduce the design iteration cycle. Description of the Drawings
[0036] Figure 1 It is a schematic diagram of the framework of the digital integrated circuit layout stage buffer prediction method of the present invention.
[0037] Figure 2 It is the sub-circuit structure diagram extracted by the present invention.
[0038] Figure 3 It is the structure diagram of the deep learning model of the present invention.
[0039] Figure 4 It is the attention module diagram of the deep learning model of the present invention.
[0040] Figure 5 It is the instance acceleration effect diagram provided by the present invention. Detailed Embodiments
[0041] Next, with reference to the drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.
[0042] Next, the present invention will be further described with reference to specific embodiments.
[0043] Embodiment 1:
[0044] This embodiment introduces a digital integrated circuit layout stage buffer insertion prediction method, as Figure 1As shown, the prediction of buffer insertion in the placement stage refers to the prediction of the type and location of buffers to be inserted after the placement stage in the physical design process of the backend of the digital integrated circuit; the method includes the following steps:
[0045] Step S1: Starting from the RTL (register-transistor logic) circuit file, perform logic synthesis through a logic synthesis tool to obtain the circuit netlist before placement, and use the physical design tool of the digital integrated circuit to perform backend physical design on the circuit netlist before placement to obtain the circuit netlist after placement.
[0046] Step S2: Extract circuit data, and perform static timing analysis on the circuit netlist before placement in Step S1 using a static timing analysis tool to obtain the timing report before placement.
[0047] Extract the physical and timing information of the circuit units from the circuit netlist before placement and the timing report before placement as the input feature sequence, and extract the type and location of the inserted buffers from the circuit netlist after placement as the label data. Use the input feature sequence and the label data as sample data.
[0048] Furthermore, the required circuit data is sourced from the sub-circuit in the circuit where buffers are to be inserted, specifically including the combinational path between the start point (register output terminal, driving unit) and the end point (register input terminal, receiving unit) of the timing path as Figure 2 shown, the placement and routing tool will insert buffers on this path according to the timing convergence requirement, and the extracted units include all the circuit gate units between the start point and the end point. Figure 2 The number of start points and end points in is 4. In specific implementation, write a python script to traverse the circuit diagram structure using the depth-first search algorithm.
[0049] The physical information of the circuit unit includes: the number of unit fan-ins, the number of unit fan-outs, pin coordinates, rising capacitance, falling capacitance, unit type.
[0050] The timing information of the circuit unit includes: unit propagation delay, timing margin, rising delay, falling delay, rising transition time, falling transition time.
[0051] The timing information and the physical information form the initial feature sequence, which will be used as the input of the buffer insertion prediction model in the placement stage after data processing. In specific implementation, use the dataframe data structure in the pyhton language to store the initial feature sequence of the circuit unit. The circuit units extracted for use as the input sequence include: the start point and the end point of the circuit path. The circuit units used as the label sequence include all the buffer units used in the sub-circuit.
[0052] Step S3: Preprocess the sample data of the input feature sequence extracted in Step S2. Map all sample non-numerical features into discrete data, and perform normalization on continuous numerical features; calculate and extract the new feature of the semi-perimeter line length based on the original data and add it to the sample data; pad the sample sequences to ensure that all sample sequences have the same length.
[0053] Further, Step S3 specifically includes the following steps:
[0054] Step S31: Map all sample non-numerical features into discrete data. The non-numerical features include the type of the cell, and the non-numerical features are mapped into discrete numerical features by using the one-hot encoding method. In specific implementation, the pandas in python is used to perform discrete mapping and one-hot encoding on the sequence data.
[0055] Step S32: Perform normalization on continuous numerical features. The continuous numerical features include: pin coordinates, rising capacitance, falling capacitance, cell propagation delay, timing margin, rising delay, falling delay, rising transition time, falling transition time. Before performing normalization on continuous numerical features, it is necessary to observe the cleanliness of the data. For missing values, the average value is used for substitution, and for outliers, the strategy of deletion is adopted. The normalization adopts the normal distribution normalization strategy. If a certain continuous numerical feature of the feature sequence is x, and the feature vectors of all samples of this feature in the sequence are X, and X satisfies the normal distribution, and the normal distribution normalization function is Norm, then the calculation formula of the normal distribution normalization function is as follows:
[0056]
[0057] Step S33: Extract the semi-perimeter line length, and the semi-perimeter line length characterizes the relative relationship between the pins of two cells. The calculation formula is as follows:
[0058]
[0059] where a 1 represents the abscissa of the pin of the first cell, b 1 represents the ordinate of the pin of the first cell, a 2 represents the abscissa of the pin of the second cell, b 2 represents the ordinate of the pin of the second cell.
[0060] Step S34: Perform data sequence padding to make the lengths of the input data sequences the same. Set the maximum length of the training set and test set data sequences as max_len. Then, fill the end of the sequences with a length less than max_len with "0" to represent the end symbol, so that the length of the feature sequence is max_len. For the data with a length greater than max_len, only take the part with a length of max_len as the data.
[0061] In specific implementation, max_len is taken as 50, that is, the sum of the starting point and the ending point of the buffer sub-circuit to be inserted is at most 50. Randomly divide 80% of the total buffer insertion sequences extracted from 8 OpenCores benchmark circuits as training data for use in the model training process, and the remaining 20% of the data is used to verify the training effect of the model during the model testing process, including the performance of classification and prediction.
[0062] Step S4: Construct a buffer insertion prediction model for the layout stage. Input the preprocessed data in step S3 into the encoder network, and the encoder extracts feature dependencies as a shared model; send the output of the encoder into the decoder network and the multi-layer perceptron to obtain the prediction result of the buffer type; at the same time, send the output of the encoder and the buffer type prediction result into another decoder network and the multi-layer perceptron to predict the position of the buffer.
[0063] Furthermore, the established neural network model structure is as Figure 3 shown, and step S4 mainly includes the following steps:
[0064] Step S41: Input the preprocessed data into the encoder network. The encoder network is composed of a multi-head attention mechanism, a feed-forward neural network, and additive normalization. The input sequence dimension is (batch_size, max_len), and after passing through the word embedding layer, the output sequence dimension is (batch_size, max_len, d k ), where batch_size represents the number of samples in each batch, max_len represents the sample sequence length, that is, the number of units contained in the sample, and d k represents the feature dimension, where k = 0, 1, 2, 3... represents the k-th feature.
[0065] In specific implementation, batch_size is taken as 64, that is, 64 sample sequences are included in the same batch, max_len is taken as 50, and the sample feature length d k is taken as 128.
[0066] Step S42: The structure of the multi-head attention mechanism is as Figure 4As shown, the output result of word embedding is used as the input of multi-head self-attention and denoted as X. After passing through three groups of trainable parameter matrices W i Q , W i K ,W i V it is transformed into matrices Q i ,K i ,V i , where i = 1, 2, …, h, and h is the number of heads in the multi-head attention mechanism, obtaining h matrices with dimensions (batch_size, max_len, d k / h). Q, K, and V represent query, key, and value respectively. Through the multi-head attention mechanism, the output result of word embedding is represented in multiple different dimensional intervals and the attention dot product operation is performed.
[0067] The calculation formula for the attention dot product operation is as follows: First, perform a dot product operation on the query matrix Q i and the transpose of the key matrix K i , and divide by the square root of the control coefficient d k . The calculation result is normalized through the activation function softmax to become the weight coefficient, and finally multiplied by the matrix V i to obtain the attention result Attention(Q i ,K i ,V i ) expressed as follows:
[0068]
[0069] The attention result physically manifests as the degree of attention to different features after word embedding. In specific implementation, the number of heads h of the multi-head attention mechanism is taken as 4, and the attention dot product calculation is performed from four dimensions.
[0070] Step S43: Combine the results of the multi-head attention. For h matrices with dimensions (batch_size, max_len, d k / h), the result after the multi-head attention operation is denoted as head i . The combination operation combines the h matrices in the feature dimension. The combination function is Concat, and the calculation method is as follows. The result after combination is multiplied by another coefficient matrix W i O to obtain the combined result MultiHead(X) after the multi-head attention, and the expression is as follows:
[0071]
[0072] Step S44: Residual connection and normalization. The result X obtained from word embedding in S41 is subjected to residual connection with the result MultiHead(X) after merging by multi-head attention in S43 to avoid gradient vanishing and gradient explosion. After the action of the normalization function LayerNorm, the output is obtained, and the expression is as follows:
[0073]
[0074] Step S45: Connect the output after normalization by the multi-head self-attention mechanism in Step S44 to a fully-connected feed-forward neural network, where the neurons between adjacent two layers are all fully-connected layers.
[0075] First, a linear transformation is performed on the input, and then through the rectified linear activation function max(0, s), where s is the input of the rectified linear activation function, and finally another linear transformation is performed. Then the output calculation formula of the fully-connected feed-forward neural network is as follows:
[0076]
[0077] Among them, t is the input of the fully-connected feed-forward neural network, and W 1 , b 1 are the weight and bias parameters of the first linear transformation respectively, and W 2 , b 2 are the weight and bias parameters of the second linear transformation respectively.
[0078] In specific implementation, the dimension of the intermediate hidden layer is 256.
[0079] Step S46: The encoder serves as the shared layer of the overall model for overall feature extraction. After extracting the deep relationship representation of the physical and timing information between the circuit units through the above encoder network, this representation will be used for two tasks: buffer type prediction and position prediction. As Figure 3 shown, after the original data features are characterized and passed through the word embedding layer, they will enter the encoder layer, and the specific structure of the encoder layer is as described in S41 - S45. In specific implementation, 3 encoder layers with exactly the same structure are connected in series to form the encoder network.
[0080] The decoder consists of multiple decoder layers. The structure of the decoder layer is roughly the same as that of the encoder, including multi-head attention mechanism, feed-forward neural network, and additive normalization. The decoder for buffer type prediction is denoted as Decoder 1 . The input of the decoder consists of two parts, namely the output Encoder(X) of the encoder and the output Z t-1The result expression of buffer type prediction is as follows:
[0081]
[0082] Among them, Decoder 1 is the buffer type prediction decoder, Encoder(X) is the output of the encoder, and Z t-1 is the output of the decoder at the previous moment.
[0083] As Figure 3 shown in, the encoder network extracts the attention result of the circuit input sequence, and the result obtains the result of buffer type prediction after passing through one layer of the decoder layer.
[0084] The result Z of buffer type prediction, the output of the shared encoder, and the output Y t-1 of the buffer position prediction decoder at the previous moment are used together as the input of the buffer position prediction decoder. The buffer position prediction decoder is denoted as Decoder 2 , and the position prediction result expression is as follows:
[0085]
[0086] Among them, Decoder 2 is the buffer position prediction decoder, Y t-1 is the output of the buffer position prediction decoder at the previous moment, and Z is the result of buffer type prediction.
[0087] As Figure 3 shown in, the attention result of the circuit input sequence extracted by the encoder network is sent to another layer of the decoder to act on the weight matrix W i Q , W i K , and the result of buffer type prediction is sent to the multi-head attention layer to act on the weight matrix W i V .
[0088] The buffer insertion prediction model in the layout stage described above includes: an encoder network, a buffer type prediction decoder, a buffer position prediction decoder, a first multi-layer perceptron, and a second multi-layer perceptron.
[0089] Among them, the encoder network includes: a word embedding layer, and the output end of the word embedding layer is sequentially connected to three encoders.
[0090] The encoder, buffer type prediction decoder, and buffer position prediction decoder have the same structure, all including: a first regularization layer, a self-attention mechanism layer, a first splicing layer, a second regularization layer, a feed-forward neural network, and a second splicing layer; the first regularization layer, self-attention mechanism layer, first splicing layer, second regularization layer, feed-forward neural network, and second splicing layer are connected in sequence, the input end of the first regularization layer is also connected to the second input end of the first splicing layer, and the output end of the first splicing layer is also connected to the second input end of the second splicing layer.
[0091] The output end of the second splicing layer of the last encoder of the encoder network is respectively connected to the input ends of the first regularization layers of the buffer type prediction decoder and the buffer position prediction decoder.
[0092] The output end of the second splicing layer of the buffer type prediction decoder is connected to a first multi-layer perceptron.
[0093] The output end of the second splicing layer of the buffer position prediction decoder is connected to a second multi-layer perceptron.
[0094] The output end of the second splicing layer of the buffer type prediction decoder is also connected to the second input end of the self-attention mechanism layer of the buffer position prediction decoder.
[0095] Step S5: Input the input feature sequence of the circuit to be predicted into the trained buffer insertion prediction model in the layout stage, and output the type of the buffer and the position of the buffer.
[0096] Embodiment 2:
[0097] This embodiment introduces a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a digital integrated circuit layout stage buffer insertion prediction method as described in any one of Embodiment 1.
[0098] Embodiment 3:
[0099] This embodiment introduces a computer device, including:
[0100] A memory for storing instructions.
[0101] A processor for executing the instructions, so that the computer device performs the operations of a digital integrated circuit layout stage buffer insertion prediction method as described in any one of Embodiment 1.
[0102] Embodiment 4:
[0103] This embodiment introduces the verification process of the method of the present invention, specifically as follows:
[0104] For example, at the 28nm process, TT process corner, 1.1V voltage, and 25°C temperature, the physical design of the benchmark circuits of 8 OpenCores after logic synthesis is carried out through the backend placement and routing tool; the experimental conditions are commercial 28nm process node, TT process corner, voltage of 1.1V, and temperature of 25°C. The circuit data are 8 open-source benchmark circuit design files from OpenCores. The clock period is set to 5ns, and the circuit gate-level netlist is obtained using the logic synthesis tool. Subsequently, the circuits before and after placement are obtained through the physical design placement and routing tool, and the static timing analysis tool is used for static timing analysis to obtain the timing report.
[0105] For example, the data is processed using the scripting language python, the sample features are processed and the sequences are filled using the machine learning library sklearn to obtain the sample data, which is randomly divided into training set data and test set data. The loss function of the multi-task model is designed and the model is trained using the training set data, and the test set data is used to verify the prediction accuracy and efficiency of the model.
[0106] The loss functions adopted include the cross-entropy loss function and the relative root mean square error loss function. The cross-entropy loss function is used for the buffer type prediction task, and the relative root mean square error loss function is used for the buffer position prediction task.
[0107] The expression of the cross-entropy loss function CrossEntropyLoss is as follows:
[0108]
[0109] where: q i represents the sample, p i represents the sample probability, i represents the sample serial number, and n represents the number of samples.
[0110] The expression of the relative root mean square error loss function rRMSELoss is as follows:
[0111]
[0112] where: x i and y i represent the horizontal and vertical coordinates of the circuit unit in the layout.
[0113] The expression of the loss function Loss of the overall model is a linear combination of the cross-entropy loss and the relative root mean square loss, as follows:
[0114]
[0115] where: c 1Denote the cross - entropy loss coefficient as c 2 Denote the relative root - mean - square error loss coefficient.
[0116] When starting the training, the parameters are set as follows. The training batch size is 128, the learning rate is 0.001, and the basic simulated annealing algorithm is used to dynamically adjust the learning rate. The optimizers are set as SGD and Adam. Adam is used for early training to quickly fit, and SGD is used to find the interval of the best prediction solution. The combination method of the loss function adopts the dynamic loss function coefficient method. In the first round of training, c1 and c2 are both equal to 1. After one round of model training, the specific values of the cross - entropy loss and the root - mean - square error loss are extracted respectively, and the ratio of the two losses is obtained by dividing them. Before the next round of training, c1 and c2 are set to the reciprocal of the ratio of the loss values. After each subsequent round of training, the combination form of the loss function will be updated in this way.
[0117] The verification effect of the specific implementation case is as Figure 5 shown. On the 8 circuits with different scales provided, the present invention achieves an average acceleration of 11 times compared with the traditional algorithm, and as the circuit scale expands, the acceleration ratio of the present invention compared with the traditional algorithm is larger.
[0118] The present invention uses the Transformer network to learn the deep - level dependency relationships between circuit units and uses multi - task learning to obtain the predicted values of the type and position of the post - layout buffer insertion. Compared with the traditional heuristic algorithm, the present invention can efficiently predict the type and position of the post - layout buffer insertion before layout, thereby helping in the early digital integrated circuit design and reducing the overall design iteration cycle.
[0119] The above - mentioned are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.
Claims
1. A buffer insertion prediction method in a digital integrated circuit layout stage, characterized in that: Specifically include: Obtain the RTL circuit file, perform logic synthesis on the RTL circuit file to obtain the circuit netlist before layout, perform back-end physical design on the circuit netlist before layout to obtain the circuit netlist after layout; Perform static timing analysis on the circuit netlist before layout to obtain a timing report before layout, extract physical information and timing information of the circuit unit from the circuit netlist before layout and the timing report before layout as input feature sequences, and extract the type and position of the inserted buffer from the circuit netlist after layout as label data; Preprocessing the input feature sequence to obtain a preprocessed input feature sequence, and using the preprocessed input feature sequence and label data as sample data; Using the sample data to train the layout phase buffer insertion prediction model to obtain a trained layout phase buffer insertion prediction model; The input feature sequence of the circuit to be predicted is input into the trained layout stage buffer and inserted into the prediction model, and the type of the buffer and the location of the buffer are output.
2. The method for predicting buffer insertion in a digital integrated circuit layout stage according to claim 1, characterized in that: The circuit unit includes all circuit gate units between the starting point and the end point of the timing path.
3. The method for predicting buffer insertion in digital integrated circuit layout stage according to claim 1, characterized in that: The physical information includes, but is not limited to, the number of unit fan-in, the number of unit fan-out, pin coordinates, rising capacitance, falling capacitance and unit type.
4. The method for predicting buffer insertion in a digital integrated circuit layout stage according to claim 1, characterized in that: The timing information includes, but is not limited to, unit propagation delay, timing margin, rise delay, fall delay, rise transition time, and fall transition time.
5. The method for predicting buffer insertion in a digital integrated circuit layout stage according to claim 1, characterized in that: The preprocessing of the input feature sequence to obtain the preprocessed input feature sequence specifically includes: Map non-numerical features in the input feature sequence into discrete data; Normalizing the continuous numerical features in the input feature sequence to obtain normalized data; Obtain the half-circle length of two units in the circuit unit; The discrete data, normalized data and half-circle line length are combined into a preprocessed input feature sequence corresponding to each circuit unit.
6. The method for predicting buffer insertion in digital integrated circuit layout stage according to claim 5, characterized in that: The length of the preprocessed input feature sequence corresponding to each circuit unit is the same.
7. The method for predicting buffer insertion in a digital integrated circuit layout phase according to claim 1, characterized in that: The layout phase buffer insertion prediction model includes: an encoder network, a buffer type prediction decoder, a buffer position prediction decoder, a first multi-layer perceptron and a second multi-layer perceptron; The encoder network includes: a word embedding layer, wherein the output end of the word embedding layer is sequentially connected to three encoders; The encoder, the buffer type prediction decoder and the buffer position prediction decoder have the same structure, and all include: a first regularization layer, a self-attention mechanism layer, a first splicing layer, a second regularization layer, a feedforward neural network and a second splicing layer; the first regularization layer, the self-attention mechanism layer, the first splicing layer, the second regularization layer, the feedforward neural network and the second splicing layer are connected in sequence, the input end of the first regularization layer is also connected to the second input end of the first splicing layer, and the output end of the first splicing layer is also connected to the second input end of the second splicing layer; The output end of the second concatenation layer of the last encoder of the encoder network is connected to the input ends of the first regularization layer of the buffer type prediction decoder and the buffer position prediction decoder respectively; The output end of the second splicing layer of the buffer type prediction decoder is connected to the first multi-layer perceptron; The output end of the second splicing layer of the buffer position prediction decoder is connected to the second multi-layer perceptron; The output end of the second splicing layer of the buffer type prediction decoder is also connected to the second input end of the self-attention mechanism layer of the buffer position prediction decoder.
8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the method for predicting buffer insertion in the layout stage of a digital integrated circuit as claimed in any one of claims 1 to 7 is implemented.
9. A computer device, characterized in that: include: A memory for storing instructions; The processor is used to execute the instructions so that the computer device performs the operation of the buffer insertion prediction method in the digital integrated circuit layout stage as claimed in any one of claims 1 to 7.