Automatic test vector generation method and system based on backtracking path optimization

Abstract

The invention discloses an automatic test vector generation method and system based on backtracking path optimization, and the method comprises the steps: inputting the feature information of each logic gate of a to-be-tested circuit into a trained neural network model, and predicting the state of each logic gate, including success and failure; and performing automatic test vector generation by adopting an ATPG algorithm according to the state of the logic gate, selecting the logic gate to add into a backtracking path for the logic gate with a successful label in the backtracking process, and skipping the logic gate for the logic gate with a failed label. According to the method, backtracking path generation is assisted according to the prediction result, more efficient test vector generation of the ATPG tool is facilitated, and the test time and the backtracking frequency are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testability design, and in particular to an automatic test pattern generation method and system based on backtrace path optimization. Background Art

[0002] With the rapid development of large-scale integrated circuit technology, electronic design automation (EDA) plays an increasingly important role. Nowadays, EDA technology has comprehensively covered all aspects of integrated circuit design, manufacturing, packaging, and testing. By applying EDA technology, the automation of design for testability (DFT) can be realized, which not only improves the circuit development efficiency but also generates high-quality test patterns, thereby improving the test quality and reducing the test cost. For a combinational logic circuit with n inputs, exhaustive testing requires 2 n input vectors. The goal of automatic test pattern generation (ATPG) is to automatically generate the smallest set of test patterns that can detect all faults according to the circuit function and fault model, so as to ensure that the circuit function does not fail during the production process.

[0003] Most of the existing automatic test pattern generation methods rely on a depth backtrace trial-and-error mechanism, such as the D algorithm, the PODEM algorithm, the FAN algorithm, etc. This easily leads to an exponential expansion of the search space, a sharp increase in the number of backtraces, the failure of heuristic decision-making, and the lack of dynamic feedback on global fault coverage, resulting in an increase in the number of backtraces, a large memory overhead, and an unstable coverage rate on large circuits. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to provide an automatic test pattern generation method and system based on backtrace path optimization that reduces the running time and the number of backtraces. The method is characterized by including the following steps: For the circuit to be tested, input the feature information of each logic gate into a trained neural network model to predict the state of each logic gate; the state of the logic gate includes success and failure; according to the state of the logic gate, use the ATPG algorithm to perform automatic test pattern generation. During the backtrace process, for the logic gate labeled as successful, select this logic gate to join the backtrace path, and for the logic gate labeled as failed, skip this logic gate; Among them, the training method of the neural network model includes: using the ATPG algorithm to perform automatic test pattern generation on the circuit, extracting the feature information of each logic gate on the backtrace path, adding a label of success or failure to each logic gate. If the logic gate can generate a test pattern or make an effective decision during the backtrace process, the added label is success, otherwise the added label is failure, and establish a data set; use the data set to train the neural network model.

[0005] Further, the ATPG algorithm includes the D algorithm, the PODEM algorithm, or the FAN algorithm.

[0006] Further, the characteristic information of the logic gate includes the logic gate type, controllability, observability, logic depth, number of logic levels, circuit hierarchy, fan-out number, and minimum input level.

[0007] Further, the neural network model includes an input layer connected in sequence, three hidden layers, and an output layer. The hidden layer uses the ReLU activation function, and the output layer uses the Sigmoid activation function. If the output value of the neural network model is greater than the threshold, the state of the output logic gate is successful, otherwise it is a failure.

[0008] Further, the loss function of the neural network model is the binary cross-entropy function.

[0009] The automatic test pattern generation system based on backtracking path optimization according to the present invention includes: A state prediction module, configured to input the characteristic information of each logic gate in the circuit under test into the trained neural network model to predict the state of each logic gate. The state of the logic gate includes success and failure. Among them, the training method of the neural network model includes: using the ATPG algorithm to perform automatic test pattern generation on the circuit, extracting the characteristic information of each logic gate on the backtracking path, adding a label of success or failure to each logic gate. If the logic gate can generate a test pattern or make an effective decision during the backtracking process, the added label is success, otherwise the added label is failure, and a data set is established; using the data set to train the neural network model. An automatic test pattern generation module, configured to perform automatic test pattern generation using the ATPG algorithm according to the state of the logic gate. During the backtracking process, for the logic gate with a label of success, select the logic gate to join the backtracking path, and for the logic gate with a label of failure, skip the logic gate.

[0010] Further, the ATPG algorithm includes the D algorithm, the PODEM algorithm, or the FAN algorithm; the characteristic information of the logic gate includes the logic gate type, controllability, observability, circuit hierarchy, fan-out number, and minimum input level.

[0011] Further, the neural network model includes an input layer connected in sequence, three hidden layers, and an output layer. The hidden layer uses the ReLU activation function, and the output layer uses the Sigmoid activation function. If the output value of the neural network model is greater than the threshold, the state of the output logic gate is successful, otherwise it is a failure; the loss function of the neural network model is the binary cross-entropy function.

[0012] The electronic device described in the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on backtrace path optimization described above is implemented.

[0013] The computer-readable storage medium described in the present invention stores a computer program. When the computer program is executed by a processor, the automatic test vector generation method based on backtrace path optimization described above is implemented.

[0014] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows: The neural network of the present invention models the characteristics of logic gates and combines a data-driven method to automatically extract key feature information on the backtrace path, improving the prediction accuracy. At the same time, the generation of the backtrace path is assisted according to the prediction result, which is beneficial for the ATPG tool to generate test vectors more efficiently, reducing the test time and the number of backtraces, and improving the circuit simulation efficiency. At the same time, the present invention can be applied to the test of large-scale integrated circuit design, reducing human intervention, improving the degree of automation, and providing an efficient and intelligent backtrace path analysis method for EDA tools. Description of the Drawings

[0015] Figure 1 It is a flowchart of the automatic test vector generation method of the present invention.

[0016] Figure 2 It is a schematic diagram of the feature information of the logic gate in the embodiment of the present invention.

[0017] Figure 3 It is an architecture diagram of the neural network model in the embodiment of the present invention.

[0018] Figure 4 It is an accuracy curve of the neural network model in the embodiment of the present invention.

[0019] Figure 5 It is a loss change curve of the neural network model in the embodiment of the present invention. Detailed Embodiments

[0020] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0021] As Figure 1 shown, the automatic test vector generation method based on backtrace path optimization includes the following steps.

[0022] Step 1, extract the circuit gate feature information to establish a data set.

[0023] This embodiment is illustrated by taking the FAN algorithm as an example. Based on the FAN algorithm, feature extraction is performed on each logic gate on the backtracking path to train a neural network model to predict the gate information on the backtracking path. There are 10 pieces of feature information extracted in this embodiment, including the ID of the gate, the type of the gate (Gate Type), the SCOAP values CC0 and CC1 (indicating the minimum number of input signals required to control a node to 0 or 1; the smaller the value, the easier it is to control the node to the corresponding logic value), the SCOAP observability CO (indicating the minimum number of combinational logic assignments required for the value of a node to propagate to the output terminal; the smaller the value, the easier it is for the value of the node to be propagated to the output terminal), the logical depth from the current gate to the output terminal (Depth fromPO), the fan-out number of the current gate (Num FO), the minimum input level (Min Level of Fanins) (the level number of the gate with the smallest level among all input gates of the current gate), the logical layer number where the current gate is located (Num Level), the circuit layer label (whether it is a decision success point on the backtracking path). Actually, an appropriate number of feature information can be selected according to needs. Then, the label is set to 1 or 0 according to whether a test vector that can detect the fault at the output terminal can be generated or whether a decision can be successfully made on the backtracking path.

[0024] The label setting rules are as follows: During the operation of the ATPG algorithm, the label is set based on whether a test vector that can detect the fault at the output terminal can be successfully generated or whether a decision can be successfully made on the backtracking path. (1) Determine whether it is a decision success point: For a logic gate, first call the dp.isSuccessful method in the original code of the ATPG algorithm to determine whether the gate can successfully form a test path. If dp.isSuccessful returns true, it means that the gate can be used as a decision success point and can successfully promote the generation of the test vector. Then, all the feature information of the gate is listed, and the label Label = 1 is marked (corresponding to the neural network outputting the logic gate state as "Success_TestGen"). If dp.isSuccessful returns false, it means that the gate cannot form an effective test path, and it is initially marked as Label = 0 (corresponding to the neural network outputting the logic gate state as "Failure"). (2) Annotation on the backtracking path: During the operation of the ATPG algorithm, if a situation where backtracking is required is encountered, further judgment is made on all the gates on the backtracking path. If the gates on the backtracking path can successfully form a test path (i.e., dp.isSuccessful returns true), the feature information of all the gates on the backtracking path is marked as Label = 1. If the gates on the backtracking path cannot form an effective test path, the feature information of these gates is marked as Label = 0.

[0025] Through this method, we can systematically collect the characteristic information of all logic gates and their corresponding label values, thereby constructing a high-quality dataset specifically for training neural network models to improve the decision-making efficiency of the FAN algorithm on the backtracking path.

[0026] In terms of data storage, a structured method is adopted for recording to ensure that the data format is clear and parsable. Specifically, the 10 characteristic information of each logic gate uses a comma (,) as a separator to ensure the readability and standardization of the data. Use the standard output stream to write these characteristic information into a CSV-format file item by item according to the field order for subsequent machine learning training or data analysis and processing. This method can not only improve the data storage efficiency but also ensure compatibility with various machine learning frameworks or analysis tools, thus providing a solid data foundation for the FAN algorithm. Figure 2 An example of the finally generated characteristic information is shown.

[0027] Step 2, dataset preprocessing.

[0028] In terms of data processing, it is first necessary to import the necessary library files to support data loading, preprocessing, and the construction of neural networks. Specifically, pandas is used for data reading and processing, numpy for numerical calculations, sklearn provides methods for data preprocessing and training set / test set division, and tensorflow.keras is used to build and train neural networks. Use pandas to read the characteristic data generated by the FAN algorithm, which has been stored in the FAN feature library in CSV format. The data file name is all_features.txt, which contains the characteristic information of multiple logic gates and their corresponding labels. After reading the data, a format check will be performed to ensure that the data can be correctly parsed and used.

[0029] Then select the appropriate feature columns and label columns for neural network training. The feature matrix X contains the input variables for learning, while the label vector y represents the prediction target, that is, the Label column. When preprocessing the data, we use StandardScaler in sklearn to standardize the numerical features. This process calculates the mean μ and standard deviation σ of each feature, and then performs a standardization transformation on the data, that is: = , this standardization method helps to eliminate the numerical magnitude differences between features, make all input variables within a similar range, improve the stability of neural network training, and accelerate the convergence speed of the model, avoiding the training convergence problem caused by too large differences in feature values and improving the generalization ability of the neural network.

[0030] In terms of dataset partitioning, the train_test_split method in sklearn is used to split the data into a training set (80%) and a test set (20%). This can ensure that the model does not overfit to specific data during training and at the same time guarantee its generalization ability on unseen data.

[0031] Step 3: Train a neural network model using the dataset.

[0032] After completing data preprocessing, we construct a neural network model with an input layer, three hidden layers, and an output layer. This model adopts the structure of a fully connected layer (FC) and is implemented using TensorFlow and Keras. Specifically, the input layer contains 64 neurons, responsible for receiving the standardized feature data. Then come three hidden layers, which contain 32, 16, and 8 neurons respectively. Each layer uses the ReLU (Rectified Linear Unit) activation function to enhance the model's non-linear representation ability and prevent the problem of gradient vanishing. Finally, the output layer uses the Sigmoid activation function for binary classification tasks. The Sigmoid function can map the output value to the range (0, 1), representing the probability value of a certain class, thus helping the model make binary classification decisions. Figure 3 Figure shows the architecture diagram of this neural network model.

[0033] In the preparation stage of neural network training, it is necessary to complete data loading and preprocessing work to ensure that the model can learn efficiently and accurately. This process mainly involves forward propagation, that is, the complete calculation process from the input layer through the hidden layers to the output layer. During forward propagation, the calculation of each layer includes two key steps: First is the weighted sum, that is, multiplying the input data by the corresponding weights and summing them; second is the non-linear transformation, which processes the result of the weighted sum through activation functions (such as ReLU, Sigmoid, etc.) so that the model can learn complex non-linear relationships. The core goal of forward propagation is to generate a prediction result and compare it with the actual label to calculate the loss value, providing a basis for subsequent processes.

[0034] During the training process of the neural network, backpropagation plays a crucial role. Its core idea is to calculate the gradient of the loss function with respect to each weight and use these gradients to adjust the weights in the network, so that the loss value of the model gradually decreases. The whole process is similar to finding the lowest point in a complex terrain, and the direction of the gradient guides us towards the direction of the minimum loss. To achieve this process, we adopt the gradient descent algorithm to update the weights according to the calculated gradient information, continuously improving the prediction ability of the network.

[0035] This invention uses the Adam (Adaptive Moment Estimation) adaptive algorithm for the model. This algorithm combines momentum and adaptive learning rate adjustment, and can provide more stable convergence in deep learning tasks. In addition, the choice of loss function is particularly important for binary classification tasks. We use binary_crossentropy (binary cross-entropy) as the loss function, and its mathematical expression is: ;

[0036] where, is the predicted value of the model, is the true label, is the size of the training set. This function can effectively measure the gap between the predicted probability and the true classification label, thereby guiding the direction of the model. During the training process, the number of training epochs is set to 50, and 34 samples are used each time (batch size is 34) for gradient calculation and weight update. Specifically, the training set is used to update the model parameters, while the validation set is used to evaluate the generalization ability of the model to ensure that the network does not overfit during the training process.

[0037] After training is completed, a final evaluation is performed on the test set to detect the performance of the model on unseen data, and further analyze whether there are overfitting or underfitting problems. In the model evaluation stage, the loss and accuracy on the test set are calculated, and Matplotlib is used for visual analysis. Plotting the accuracy curve and loss change curve during the model training process can help visually observe the convergence of the training process. If the loss on the training set continues to decrease while the loss on the test set increases, it indicates that the model may be overfitting and has poor generalization ability; if the losses on both the training set and the test set tend to be stable and the performance of the test set is better, it means that the model has achieved a good learning effect. As Figure 4 and Figure 5 shown, the accuracy curve and loss change curve of the neural network during the training process show the convergence trend of the model, further verifying the training effect of the model.

[0038] Step 4, for the circuit to be measured, extract the gate feature information of the circuit and obtain the prediction result through the neural network model.

[0039] In this step, the state of the circuit gate's feature data is predicted through deep learning methods to achieve the automated evaluation of the performance of circuit components. First, the circuit gate feature data of the circuit under test is loaded and stored in a CSV file. The file content includes the circuit gate ID and multiple feature variables related to the circuit gate state. In this step, data screening is first required, and non-feature columns, namely the label column and the gate ID column, are excluded to ensure that subsequent analysis only focuses on the feature data of the circuit gate.

[0040] In the data preprocessing stage, appropriate transformation processing will be performed on the circuit gate feature data to meet the input requirements of the deep learning model. Specifically, after loading the data using the pandas library, the feature data type is converted to 32-bit floating type (float32), which is the standard input data format of the deep learning framework TensorFlow. This processing step ensures that the numerical range of the feature data conforms to the input specification of the model, thereby improving the data processing efficiency and prediction performance.

[0041] Next, the tf.saved_model.load function of the TensorFlow framework is used to load a pre-trained deep neural network model. The model has learned the mapping rules of the circuit gate state from a large amount of circuit gate feature data during the training process and can effectively infer the feature data of unknown circuit gates. Specifically, the output of the model is a continuous value representing the predicted probability of the circuit gate state. Based on this, by setting a threshold (0.5 in this invention), the output of the model is converted into a discrete label. If the model output value is greater than 0.5, the state of the circuit gate is determined to be "Success_TestGen", indicating, otherwise it is "Failure". In code implementation, this process generates the final classification label by comparing the output value with the threshold, and success and failure correspond to numerical labels 1 and 0 respectively.

[0042] Finally, the prediction results need to be saved in a structured manner. The ID of each circuit gate and its corresponding prediction label are stored in a text file in the format of "Node_ID, Predicted_Label". This data saving method facilitates subsequent result analysis, data sharing, and applications. In addition, the saved prediction file also provides basic data support for further verifying the model effect, analyzing prediction errors, and improving the model.

[0043] Step 5, perform backtracking based on the prediction results and run the ATPG algorithm for automatic test vector generation.

[0044] Based on the state labels of circuit gates predicted by a neural network model (such as "Success_TestGen" or "Failure"), the FAN algorithm selects the backtracking path according to this label information. During the backtracking process, if the predicted label is "Success_TestGen", the FAN algorithm preferentially selects this path for backtracking and generates test vectors; if the predicted label is "Failure", the FAN algorithm will ignore the backtracking path where this gate is located and preferentially select other paths for backtracking and generating test vectors. Through this backtracking mechanism, the FAN algorithm can automatically adjust according to the prediction results, improving the accuracy and efficiency of test pattern generation.

[0045] The method described in the present invention will be described below through experiments.

[0046] Fault simulation is performed using the test vectors generated by the method described in the present invention. The effectiveness and accuracy of the test vectors generated by backtracking are verified through simulation, mainly focusing on several key indicators: fault coverage, simulation running time, and the number of backtracking times. During this process, the fault coverage reflects the ability of the test pattern to detect faults, the simulation running time represents the efficiency of the entire simulation process, and the number of test patterns reflects the simplicity and effectiveness of the generated patterns.

[0047] In this embodiment, four scales of circuits (S208, S510, S9234, S38584) are used for testing, and the simulation results of the method according to the present invention are compared and analyzed with those of the traditional FAN algorithm to evaluate the advantages of this method in terms of fault coverage, test time, number of backtracking times, etc.

[0048] Table 1 Method of the present invention

[0049]

[0050] Table 2 Traditional FAN algorithm

[0051]

[0052] As can be seen from Table 1 and Table 2:

[0053] 1. Optimization of the number of backtracking times: The neural network FAN algorithm is significantly superior to the traditional event stack backtracking method in terms of the number of backtracking times. In the S9234 circuit, the number of backtracking times of the neural network method is 42729, while that of the traditional method is 60162, a reduction of about 28.6%. In the S38584 circuit, the number of backtracking times of the neural network method is 224732, and that of the traditional method is 244491, a reduction of about 8.1%.

[0054] 2. Running Time: The neural network FAN algorithm performs better in terms of running time. In the S510 circuit, the running time of the neural network method is 0.00078, while that of the traditional method is 0.000917, a reduction of approximately 14.94%. In the S9234 circuit, the running time of the neural network method is 0.05463, while that of the traditional method is 0.0986, a reduction of approximately 44.6%. It can be seen that in large-scale circuits, the optimization effect of running time is better.

[0055] 3. Stability of Fault Coverage Rate: The two methods perform the same in terms of fault coverage rate (e.g., both are 97.43% for S208 and 99.14% for S510), indicating that while the neural network method optimizes backtracking, it does not sacrifice test quality.

[0056] In summary, the core advantage of the present invention is to optimize the backtracking path selection through machine learning, thereby reducing ineffective operations and improving operation efficiency. It is particularly applicable to complex circuits (such as S9234, S38584), where the performance of the traditional method deteriorates due to a sharp increase in the number of backtracking times, while the neural network method can effectively alleviate this problem. In extremely simple circuits (such as S208, S510), the performance of the two methods is similar, and the advantage of the neural network may not be obvious. However, as the circuit scale increases, its advantage is significantly manifested.

[0057] The automatic test vector generation system based on backtracking path optimization described in the present invention includes: A state prediction module, configured to input the feature information of each logic gate in the circuit to be tested into a trained neural network model to predict the state of each logic gate; the state of the logic gate includes success and failure; Among them, the training method of the neural network model includes: using the ATPG algorithm to perform automatic test vector generation on the circuit, extracting the feature information of each logic gate on the backtracking path, adding a label of success or failure to each logic gate. If the logic gate can generate a test vector or make an effective decision during backtracking, the added label is success, otherwise the added label is failure, and establishing a data set; using the data set to train the neural network model; An automatic test vector generation module, configured to perform automatic test vector generation using the ATPG algorithm according to the state of the logic gate. During backtracking, for the logic gate with a label of success, this logic gate is preferentially selected to be added to the backtracking path, and for the logic gate with a label of failure, this logic gate is skipped.

[0058] The electronic device described in the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on backtracking path optimization described above is implemented.

[0059] The computer-readable storage medium according to the present invention stores a computer program, and when the computer program is executed by a processor, the automatic test vector generation method based on backtrace path optimization is implemented.

[0060] The computer-readable storage medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory or any other medium that can store program code in the form of instructions or data structures and can be accessed by a computer.

[0061] The processor is configured to execute the computer program stored in the memory to implement each step in the methods described in the above embodiments.

Claims

1. A method for automatic test vector generation based on backtracking path optimization, characterized in that: The steps include: For the circuit to be tested, the characteristic information of each logic gate is input into the trained neural network model to predict the state of each logic gate; the state of the logic gate includes success and failure; the ATPG algorithm is used to automatically generate test vectors according to the state of the logic gate. In the backtracking process, the logic gate with a label of success is selected to add to the backtracking path, and the logic gate with a label of failure is skipped; Among them, the training method of the neural network model includes: using the ATPG algorithm to automatically generate test vectors for the circuit, extracting the characteristic information of each logic gate on the backtracking path, adding a label of success or failure to each logic gate, if the logic gate can generate a test vector or complete an effective decision during the backtracking process, the added label is success, otherwise the added label is failure, and a data set is established; using the data set to train the neural network model.

2. The automatic test vector generation method based on backtracking path optimization according to claim 1 is characterized in that: The ATPG algorithm includes a D algorithm, a PODEM algorithm or a FAN algorithm.

3. The automatic test vector generation method based on backtracking path optimization according to claim 1 is characterized in that: The characteristic information of the logic gate includes logic gate type, controllability, observability, logic depth, number of logic layers, circuit level, fan-out number and minimum input level.

4. The automatic test vector generation method based on backtracking path optimization according to claim 1 is characterized in that: The neural network model includes an input layer, three hidden layers and an output layer connected in sequence, the hidden layer uses a ReLU activation function, and the output layer uses a Sigmoid activation function; if the output value of the neural network model is greater than a threshold, the state of the output logic gate is success, otherwise it is failure.

5. The automatic test vector generation method based on backtracking path optimization according to claim 1 is characterized in that: The loss function of the neural network model is a binary cross entropy function.

6. An automatic test vector generation system based on backtracking path optimization, characterized in that: include: A state prediction module is used to input the characteristic information of each logic gate in the circuit to be tested into the trained neural network model to predict the state of each logic gate; The states of logic gates include success and failure; The training method of the neural network model includes: using the ATPG algorithm to automatically generate test vectors for the circuit, extracting the characteristic information of each logic gate on the backtracking path, adding a label of success or failure to each logic gate, if the logic gate can generate a test vector or complete an effective decision in the backtracking process, the added label is success, otherwise the added label is failure, and a data set is established; using the data set to train the neural network model; The automatic test vector generation module is used to automatically generate test vectors using the ATPG algorithm according to the state of the logic gate. During the backtracking process, for the logic gate labeled as success, the logic gate is selected to be added to the backtracking path, and for the logic gate labeled as failure, the logic gate is skipped.

7. The automatic test vector generation system based on backtracking path optimization according to claim 6, characterized in that: The ATPG algorithm includes a D algorithm, a PODEM algorithm or a FAN algorithm; the characteristic information of the logic gate includes a logic gate type, controllability, observability, circuit level, fan-out number and minimum input level.

8. The automatic test vector generation system based on backtracking path optimization according to claim 6, characterized in that: The neural network model includes an input layer, three hidden layers and an output layer connected in sequence, the hidden layer uses a ReLU activation function, and the output layer uses a Sigmoid activation function; if the output value of the neural network model is greater than a threshold, the state of the output logic gate is success, otherwise it is failure; the loss function of the neural network model is a binary cross entropy function.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the automatic test vector generation method based on backtracking path optimization according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the automatic test vector generation method based on backtracking path optimization according to any one of claims 1 to 5 is implemented.

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