A testing device

Abstract

An embodiment of the present application provides a testing device, which includes a first fixing plate, a second fixing plate, and a circuit board. The first fixing plate and the second fixing plate are arranged at a preset distance in a first direction. The circuit board is disposed on a side of the second fixing plate away from the first fixing plate. The second fixing plate includes a groove, and a plurality of thimbles connected to the circuit board are arranged in the groove. The first fixing plate is used to pick up an integrated circuit under test and move it into the groove. The thimbles are used to electrically connect the integrated circuit under test and the circuit board. The circuit board is used to perform electrical performance testing on the integrated circuit under test. Among them, the first fixing plate includes a conductive layer and a first grounding layer. The conductive layer is disposed adjacent to the second fixing plate, and the first grounding layer is arranged on a side of the conductive layer away from the second fixing plate. The conductive layer is electrically connected to the grounding layer and is used to simulate the shielding effect of the shielding cover on the integrated circuit in the electronic device, so as to eliminate the error caused by the shielding cover between the testing device and the electronic device for the integrated circuit.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a testing device. Background Art

[0002] With the continuous development of the field of electronic device technology, the requirements for the thickness of electronic devices such as mobile phones are getting thinner and thinner. Therefore, the internal space of electronic devices needs to be further compressed. Among them, for the integrated circuit (IC) inside the electronic device, that is, the chip is usually provided with a shielding cover. While the thickness of the electronic device is reduced, the height of the shielding cover also needs to be further reduced, resulting in an increasingly small distance between the shielding cover and the chip, and the components inside the chip will have performance deviation due to the influence of the shielding cover. Among them, the chip is manufactured by a series of steps such as lithography, etching, and doping. In the actual integrated circuit (IC) design and production process, various defects will inevitably occur, and electrical function tests need to be carried out before the product is delivered to customers. Since the chip will be affected by the shielding cover in the electronic device, resulting in a deviation between the performance of the chip in the electronic device and the test results, how to eliminate the test result deviation caused by the shielding cover and improve the chip effect is an urgent problem to be solved. Summary of the Invention

[0003] To solve the foregoing technical problems, an embodiment of this application provides a testing device for eliminating the performance deviation of a chip between the testing device and an electronic device.

[0004] In a first aspect, an embodiment of this application provides a testing device, including a first fixing plate, a second fixing plate, and a circuit board. The first fixing plate and the second fixing plate are arranged at a preset distance interval in a first direction. The circuit board is arranged on a side of the second fixing plate away from the first fixing plate. The second fixing plate includes a groove, and a plurality of thimbles connected to the circuit board are arranged in the groove. The first fixing plate is used to pick up the integrated circuit to be tested and move it into the groove. The thimbles are used to electrically connect the integrated circuit to be tested and the circuit board. The circuit board is used to perform electrical performance tests on the integrated circuit to be tested. Among them, the first fixing plate includes a conductive layer and a first grounding layer. The conductive layer is arranged adjacent to the second fixing plate. The first grounding layer is arranged on a side of the conductive layer away from the second fixing plate. The conductive layer is electrically connected to the grounding layer. The conductive layer is used to shield the integrated circuit to be tested. By providing a conductive layer in the first fixing plate and electrically connecting the conductive layer to the grounding layer, the conductive layer can achieve the shielding effect on the integrated circuit to be tested in the testing device, that is, it can simulate the shielding cover around the integrated circuit when it is arranged in the electronic device, so that when the testing device performs electrical performance tests on the integrated circuit to be tested, it can eliminate the test result deviation caused by the shielding cover in the electronic device.

[0005] Optionally, the first fixing plate includes a main body portion and a grasping portion which are stacked in sequence along the first direction. The first grounding layer is disposed within the main body portion. The grasping portion is disposed opposite to the groove. The grasping portion includes a bottom plate, the conductive layer, and a vacuum tube. The conductive layer and the bottom plate are stacked in sequence along the first direction. The conductive layer is disposed adjacent to the main body portion. The vacuum tube is disposed through the conductive layer and the bottom plate along the first direction. The grasping portion picks up the integrated circuit under test through the vacuum tube.

[0006] By disposing the conductive layer within the grasping portion and controlling the grasping portion to be disposed opposite to the groove, when the grasping portion moves the integrated circuit under test into the groove, the grasping portion covers the groove, so that the conductive layer can cover the integrated circuit under test, and further shields the signal of the integrated circuit under test as an analog shielding cover during the electrical performance test of the integrated circuit under test.

[0007] Optionally, the main body portion further includes a fixing layer which is disposed between the first grounding layer and the grasping portion. The first fixing plate further includes at least one first conductive member, and the second fixing plate further includes at least one second conductive member. The first conductive member is disposed around the grasping portion and partially embedded in the side of the fixing layer adjacent to the second fixing plate. The second conductive member is disposed around the groove and partially embedded in the second fixing plate. The first conductive member and the second conductive member are disposed opposite to each other along the first direction. When the first fixing plate and the second fixing plate are stacked and assembled, the first conductive member abuts against the second conductive member and is electrically connected.

[0008] Optionally, a plurality of conductors are disposed in the fixing layer. The first conductive member, the conductive layer, and the first grounding layer are electrically connected through the conductors. The circuit board includes a second grounding layer. The second conductive member is electrically connected to the second grounding layer. The integrated circuit under test is electrically connected to the second grounding layer through the thimble. When the integrated circuit under test is located in the groove, a grounding loop is formed among the conductive layer, the first conductive member, the second conductive member, and the integrated circuit under test.

[0009] Optionally, the plurality of conductors include at least one first conductor disposed along the first direction and at least one second conductor disposed along the second direction. The first conductor is connected to the first grounding layer and the conductive layer, and the second conductor is connected between the first conductor and the first conductive member, wherein the first direction is perpendicular to the second direction.

[0010] By setting the first conductive member and the second conductive member, when the grasping part moves the integrated circuit under test into the groove, the first conductive member is abutted against the second conductive member, so that the first conductive member, the second conductive member and the conductive layer form a short-distance grounding loop, eliminating the parasitic capacitance between the first grounding layer and the second grounding layer, thereby further improving the conductive effect of the conductive layer.

[0011] Optionally, the conductive layer has a sheet structure or a mesh structure. By setting the conductive layer as a sheet structure, the shielding effect of the conductive layer on the integrated circuit under test can be improved. By setting the conductive layer as a mesh structure, the stability inside the grasping part can be improved.

[0012] Optionally, the testing device further includes an elastic member. The elastic member is disposed between the first conductive member and the second conductive body. The elastic member is electrically connected to the first grounding layer through the second conductive body and the first conductive body, and / or the elastic member is disposed between the second conductive member and the second grounding layer, and the second conductive member is electrically connected to the second grounding layer through the elastic member.

[0013] By disposing an elastic member between the first conductive member and the second conductive body, it is possible to avoid damage to the conductive member caused by excessive pressure when controlling the abutment of the first conductive member and the second conductive member.

[0014] Optionally, the bottom of the groove includes a contact area, and a plurality of the thimbles are arranged in an array in the contact area. The second fixing plate further includes at least one shielding plate, and the shielding plate is arranged between the side wall of the groove and the contact area along the first direction to shield the integrated circuit under test.

[0015] Optionally, the second fixing plate includes four shielding plates, the contact area is rectangular, and the four shielding plates are arranged along the first direction in the groove and are respectively adjacent to the four sides of the contact area to enclose the contact area.

[0016] Optionally, the four shielding plates are connected end to end in the groove to form an accommodating space, and the contact area is located in the accommodating space. By arranging four shielding plates in the groove to form an accommodating space, when the grasping part moves the integrated circuit under test into the accommodating space, the four shielding plates can play a shielding effect on the integrated circuit under test, and are used together with the conductive layer to achieve the effect of simulating a shielding cover.

[0017] Compared with the prior art problems, an embodiment of the present application provides a test device, which is used to arrange a conductive layer and a first conductive member in a first fixing plate, and arrange a second conductive member in a second fixing plate, so that when the grasping part moves the integrated circuit under test into the groove of the second fixing plate, the conductive layer, the first conductive member and the second conductive member form a grounding loop for signal shielding when performing electrical performance testing on the integrated circuit under test, and is used to eliminate the performance deviation between the integrated circuit in the test device and the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of the disassembly structure of an electronic device;

[0020] Figure 2 is Figure 1 a schematic layout diagram of an integrated circuit in the electronic device;

[0021] Figure 3 It is a schematic diagram of the structure of a test device provided in the related art;

[0022] Figure 4 It is a schematic diagram of the structure of a test device provided by an embodiment of the present application;

[0023] Figure 5 is Figure 4 a schematic layout diagram of the first conductive member;

[0024] Figure 6 is Figure 4 a schematic layout diagram of the second conductive member;

[0025] Figure 7 is Figure 4 a schematic layout diagram of the groove;

[0026] Figure 8 Another provided by this embodiment is as Figure 4 a schematic layout diagram of the groove;

[0027] Figure 9 is Figure 4 a schematic diagram of the structure of the test device during testing;

[0028] Figure 10 is Figure 9 a schematic diagram of the circuit architecture of the parasitic capacitance in the test device;

[0029] Figure 11 is Figure 9 Schematic diagram of the ground loop in the test device;

[0030] Figure 12 is Figure 4 Schematic diagram of the planar layout of the fixing plate;

[0031] Figure 13 is Figure 4 Schematic diagram of the split structure of the fixing plate;

[0032] Figure 14 is the schematic diagram of the split structure of another fixing plate;

[0033] Figure 15 is Figure 4 Schematic diagram of the process flow for adjusting the thickness of the bottom plate. Specific implementation manners

[0034] For the convenience of clearly describing the technical solutions of the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. do not necessarily limit to be different.

[0035] Describing with reference to "one embodiment" or "some embodiments" etc. in the specification of the present application means that specific features, structures or characteristics described in combination with the embodiment are included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in the specification of the present application do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "include", "comprise", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] To enable those skilled in the art to more clearly understand the solutions of the present application, the application scenarios of the technical solutions of the present application will be described first below.

[0037] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the split structure of an electronic device.

[0038] Such as Figure 1As shown, the electronic device 200 includes: a display module 201, a middle frame 202, a rear cover 203, a printed circuit board 204, and a battery 205. Among them, the middle frame 202, the printed circuit board 204, and the battery 205 are disposed between the display module 201 and the rear cover 203. The printed circuit board 204 and the battery 205 may be disposed on the middle frame 202. For example, the printed circuit board 204 and the battery 205 are disposed on a surface of the middle frame 202 facing the rear cover 203. In some other embodiments, the printed circuit board 204 and the battery 205 may also be disposed on a surface of the middle frame 202 facing the display module 201.

[0039] The battery 205 may be connected to other devices through a charge and discharge management chip ( Figure 1 not shown in the figure). The charge and discharge management chip may receive the electrical energy output by the battery 205 and supply power to a processor, an internal memory, an external memory, the display module 201, a camera, and a communication module, etc. in the electronic device 200. The charge and discharge management chip may also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). The charge and discharge management chip may also receive externally input electrical energy to charge the battery 205. In some embodiments, the charge and discharge management chip may be integrated into the printed circuit board 204.

[0040] The printed circuit board 204 may be integrated with a control chip, and the control chip includes but is not limited to an application processor (AP), a double data rate synchronous dynamic random access memory (DDR), and a universal flash storage (UFS), etc. It should be noted that the printed circuit board 204 may be a rigid circuit board, a flexible circuit board, or a rigid-flex circuit board. The printed circuit board 204 may include but is not limited to using an FR-4 dielectric board, a Rogers dielectric board, or a hybrid dielectric board of FR-4 and Rogers. Among them, FR-4 is a code for a flame-retardant material grade, and the Rogers dielectric board is a high-frequency board.

[0041] As Figure 2 shown, Figure 2 for Figure 1Schematic layout diagram of an integrated circuit in an electronic device 200. The integrated circuit B is disposed on a printed circuit board 204. The electronic device 200 further includes a shielding cover 206 which covers the integrated circuit B. Among them, the integrated circuit B can be a radio frequency chip, and the shielding cover 206 is used to prevent the signal emitted by the radio frequency chip from being interfered. Among them, the thickness of the radio frequency chip is about 0.6 - 0.8 mm, and the thickness of the shielding cover 206 is usually 1.2 mm. Since the thickness of the electronic device 200 is further reduced, the thickness of the shielding cover 206 is further reduced to about 0.9 mm, resulting in the distance between the shielding cover 206 and the integrated circuit B being about 0.1 mm. Since the distance between the shielding cover 206 and the integrated circuit B becomes smaller, the radio frequency chip will be affected by the shielding cover 206 and its performance will deviate.

[0042] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of a test device provided in the related art.

[0043] As Figure 3 shown, the test device 100 is used to test a radio frequency chip when it leaves the factory, such as FT test or ATE test, etc., to determine whether the chip is a good product. Among them, the test device 100 includes a first fixing plate 10, a second fixing plate 20 and a circuit board 30. The first fixing plate 10 and the second fixing plate 20 are disposed opposite to each other along a first direction F1. The circuit board 30 is stacked on a side of the second fixing plate 20 away from the first fixing plate 10. The first fixing plate 10 includes a main body portion 11 and a grasping portion 12. The grasping portion 12 is disposed on a side of the main body portion 11 facing the second fixing plate 20. The first fixing plate 10 grasps the integrated circuit A to be tested through the grasping portion 12. The second fixing plate 20 is provided with a groove 21, and a plurality of thimble pins 22 are further disposed in the groove 21. Among them, the thimble pins 22 are electrically connected to the circuit board 30.

[0044] The first fixing plate 10 moves the integrated circuit A to be tested to the groove 21 through the grasping portion 12 under the control of an external robotic arm, and applies pressure to the integrated circuit A to be tested to control the electrical connection between the pin feet in the integrated circuit A to be tested and the thimble pins 22 in the groove 21, so that the integrated circuit A to be tested is electrically connected to the circuit board 30 through the thimble pins 22, thereby realizing the test of the integrated circuit A to be tested. After the test is completed, the first fixing plate 10 takes out the integrated circuit A to be tested through the grasping portion 12.

[0045] Among them, the grasping part 12 may include a bottom plate 121 and a vacuum tube 123. The bottom plate 121 is disposed adjacent to the main body part 11. The vacuum tube 123 is disposed in the central area of the bottom plate 121 and partially extends to the first fixing plate 10. During the process of grasping the integrated circuit A to be tested, when the bottom plate 121 faces the integrated circuit A to be tested, the air in the vacuum tube 123 is pumped out to adsorb the integrated circuit A to be tested, thereby realizing the grasping of the integrated circuit A to be tested.

[0046] Due to the performance deviation of the integrated circuit B caused by the influence of the shielding cover 206 in the electronic device 200, and when testing during factory production, the influence factor of the shielding cover is not detected, so the FT test result of the integrated circuit B will deviate from the operation effect in the electronic device 200, which will further affect the operation effect of the integrated circuit B. Based on this, the present application provides a test device for eliminating the problem of deviation in the integrated circuit test result caused by the influence of the shielding cover.

[0047] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a test device provided by an embodiment of the present application.

[0048] As Figure 4 shown, the test device 100 includes a first fixing plate 10, a second fixing plate 20 and a circuit board 30. Among them, the first fixing plate 10 and the second fixing plate 20 are disposed opposite to each other at a preset distance along the first direction F1. The circuit board 30 is disposed on the side of the second fixing plate 20 away from the first fixing plate 10. The first fixing plate 10 is used to pick up the integrated circuit A to be tested and move it to a preset position of the second fixing plate 20, and is electrically connected to the circuit board 30 through the second fixing plate 20. The circuit board 30 is used to perform electrical performance tests on the integrated circuit A to be tested.

[0049] Among them, the first fixing plate 10 includes a main body part 11 and a grasping part 12. The main body part 11 includes a first grounding layer 111 and a fixing layer 112. The first grounding layer 111 and the fixing layer 112 are stacked in sequence along the first direction F1. The main body part 11 further includes at least one first conductive member 113. The first conductive member 113 is disposed adjacent to the grasping part 12 along the second direction F2, and is embedded in the side of the fixing layer 112 adjacent to the second fixing plate 20 and protrudes outward along the first direction F1. A conductor L is also disposed in the fixing layer 112. The first conductive member 113 is electrically connected to the first grounding layer 111 through the conductor L.

[0050] The main body part 11 and the grasping part 12 are stacked in sequence from top to bottom. Among them, the grasping part 12 is arranged on one side of the main body part 11 adjacent to the second fixing plate 20, that is, the grasping part 12 is closer to the second fixing plate 20 than the main body part 11. The first fixing plate 10 picks up the integrated circuit A to be measured through the grasping part 12. Among them, the grasping part 12 includes a bottom plate 121, a conductive layer 122 and a vacuum tube 123. Among them, the bottom plate 121 is stacked on one side of the fixing layer 112 adjacent to the second fixing plate 20. The conductive layer 122 is arranged between the bottom plate 121 and the fixing layer 112 along the second direction F2, or is arranged in the bottom plate 121, and is electrically connected to the first grounding layer 111 and the first conductive member 113 through a conductor L. The vacuum tube 123 is arranged through the fixing layer 112 and the bottom plate 121 along the first direction F1, and is flush with the bottom plate 121 on one side adjacent to the second fixing plate 20. During the process of grasping the integrated circuit A to be measured, when the bottom plate 121 is facing and close to the integrated circuit A to be measured, the air in the vacuum tube 123 is pumped out to realize the adsorption of the integrated circuit A to be measured, so as to realize the grasping of the integrated circuit A to be measured.

[0051] Among them, the conductor L includes at least one first conductor L1 extending along the first direction F1 and at least one second conductor L2 extending along the second direction F2. Among them, the conductive layer 122 is electrically connected to the first grounding layer 111 through the first conductor L1, and the first conductive member 113 is electrically connected to the first conductor L1 through the second conductor L2, so as to be electrically connected to the first grounding layer 111 and the conductive layer 122 through the first conductor L1.

[0052] The second fixing plate 20 includes a groove 21, a thimble 22 and at least one second conductive member 23. Among them, the groove 21 is arranged facing the grasping part 12 along the first direction F1, the thimble 22 is arranged in the groove 21, the second conductive member 23 is arranged adjacent to the groove 21 along the second direction F2, and is arranged facing the first conductive member 113 along the first direction F1. The circuit board 30 includes a second grounding layer 32, and the second conductive member 23 is electrically connected to the second grounding layer 32.

[0053] In this embodiment, the fixing layer 112 can be made of an insulating material or a metal conductive material, and the bottom plate 121 is made of an insulating material, and the insulating material can be a resin material.

[0054] When the test device 100 in this embodiment tests the integrated circuit A to be tested, the first conductive member 113 is electrically connected to the second conductive member 23. Since the first conductive member 113 is electrically connected to the first grounding layer 111 and the conductive layer 122 through the conductor L, and the second conductive member 23 is electrically connected to the second grounding layer 32, that is, a ground loop is formed among the first conductive member 113, the second conductive member 23, and the conductive layer 122, making the conductive layer 122, the first conductive member 113, and the second conductive member 23 equivalent to the shielding case 206 in the electronic device 200. Thus, the influence of the shielding case 206 on the integrated circuit A to be tested can be simulated, and further the problem of test result deviation caused by the influence of the shielding case 206 can be eliminated.

[0055] Please refer to Figure 5 and Figure 6 , Figure 5 which is Figure 4 the layout schematic diagram of the first conductive member 113 in Figure ⑥ and Figure 4 the layout schematic diagram of the second conductive member 23 in Figure 5 As shown in Figure 6 , the test device 100 further includes at least one elastic member 114. The elastic member 114 is disposed between the second conductor L2 and the first conductive member 113, and the elastic member 114 is electrically connected to the first grounding layer 111 through the second conductor L2 and the first conductor L1. As shown in Figure 6 , the elastic member 114 can also be disposed between the second conductive member 23 and the second grounding layer 32, and the second conductive member 23 is electrically connected to the second grounding layer 32 through the elastic member 114. Exemplarily, any one first conductive member 113 and one second conductive member 23 arranged opposite to each other are taken as a group of conductive members. Among them, at least one elastic member is arranged in a group of conductive members, that is, in a group of conductive members, the elastic member 114 abuts against the first conductive member 113 or the second conductive member 23. Or, a group of conductive members includes two elastic members 114, and the first conductive member 113 and the second conductive member 23 respectively abut against the two elastic members 114, so that the first conductive member 113 is electrically connected to the second conductor L2 through the elastic member, and at the same time the second conductive member 23 is electrically connected to the second grounding layer 32 through the elastic member 114. By arranging the elastic member 114 between the first conductive member 113 and the second conductor L2, and / or arranging the elastic member 114 between the second conductive member 23 and the second grounding layer 32, it is possible to avoid damage to the conductive member caused by excessive pressure when controlling the contact between the first conductive member 113 and the second conductive member 23.

[0056] Please refer to Figure 7 and Figure 8 , Figure 7 which is Figure 4 the layout schematic diagram of the groove 21 in Figure 8 Another provided in this embodiment is as Figure 4Schematic layout diagram of the middle groove 21.

[0057] As Figure 7 and Figure 8 shown, the groove 21 includes a contact area 211. The contact area 211 is rectangular in shape. A plurality of thimbles 22 are arranged in an array in the contact area 211. The second fixing plate 20 further includes at least one shielding plate 24. The shielding plate 24 is arranged adjacent to the contact area 211, or the shielding plate 24 is arranged on the inner wall of the groove 21. Exemplarily, the second fixing plate 20 may include four shielding plates 24. The contact area 211 is rectangular in shape. The four shielding plates 24 are respectively arranged around the contact area 211 to form an accommodating space, that is, the contact area 211 is located within the accommodating space. The grasping portion 12 is used to move the integrated circuit A to be tested into the accommodating space so that the integrated circuit A to be tested is connected to the thimbles 22 in the contact area 211. The four shielding plates 24 are used to apply a shielding effect when testing the integrated circuit A to be tested, so as to simulate the effect of the shielding cover 206 in the electronic device. Among them, the four shielding plates 24 are independently arranged. Of course, the four shielding plates 24 can also be connected end to end to form a rectangular accommodating space ( Figure 7 ), which is used to accommodate the integrated circuit A to be tested and is used to further improve the shielding effect of the accommodating space.

[0058] When the integrated circuit A to be tested is located in the accommodating space in the groove 21 for testing, the accommodating space formed by the four shielding plates 24 and the conductive layer 122 in the grasping portion 12 together form a shielding cover with the same structure as that in the electronic device 200. And the conductive layer 122 is electrically connected to the ground layer through the first conductive member 113 and the second conductive member 23, thereby forming a grounding loop, realizing the simulation of the shielding effect of the shielding cover.

[0059] Please refer to Figure 9 , Figure 9 which is Figure 4 the schematic structural diagram of the test device during testing.

[0060] As Figure 9As shown, during the testing process of the integrated circuit A under test by the testing device 100, the grasping part 12 moves the integrated circuit A under test to the groove 21, and applies pressure to the integrated circuit A under test to control the electrical connection between the integrated circuit A under test and the thimble 22 in the groove 21, for performing electrical performance testing on the integrated circuit A under test. At the same time, the first conductive member 113 is electrically connected to the second conductive member 23. Since the first conductive member 113 is electrically connected to the first ground layer 111 through the conductor L, and the second conductive member 23 is electrically connected to the second ground layer 32, that is, a ground loop is formed among the first conductive member 113, the second conductive member 23, the conductive layer 122, the first ground layer 111, and the second ground layer 32, so that when testing the integrated circuit A under test, the influence of the shielding cover 206 on the integrated circuit A under test can be simulated, thereby avoiding the problem of deviation in the test results of the integrated circuit A under test due to the influence of the shielding cover 206 ( Figure 2 ).

[0061] Please refer to Figure 10 , Figure 10 which Figure 9 is a schematic circuit diagram of the parasitic capacitance in the testing device in

[0062] As Figure 10 shown, during the testing process of the integrated circuit A under test by the testing device 100, when the grasping part 12 moves the integrated circuit A under test to the groove 21 and controls the electrical connection between the integrated circuit A under test and the thimble 22 in the groove 21, if the first conductive member 113 is not provided to form a ground loop between the first conductive member 113, the second conductive member 23, and the conductive layer 122, at this time, the conductive layer 122 can only be connected to the first ground layer 111 in the main body part 11 through the conductor L, and the integrated circuit A under test can only be connected to the second ground layer 32 through the thimble 22, that is, the reference ground of the integrated circuit A under test is the second ground layer 32. At this time, the first ground layer 111 is a non-ideal ground, resulting in a parasitic capacitance R between the first ground layer 111 and the second ground layer 32, thereby causing deviation in the final test results.

[0063] Please refer to Figure 11 , Figure 11 which Figure 9 is a schematic diagram of the ground loop in the testing device in

[0064] As Figure 11 shown, by setting the first conductive member 113, the first conductive member 113 is electrically connected to the conductive layer 122 through the conductor L, and at the same time, the first conductive member 113 is connected to the second conductive member 23, so that the integrated circuit A under test can be connected to the conductive layer 122 through the second conductive member 23, the first conductive member 113, and the conductor L, thereby forming a short-distance ground loop, avoiding the parasitic capacitance formed by the overlong ground loop, and thus avoiding the deviation in the test results caused by the parasitic capacitance.

[0065] Please also refer to Figure 12 、 Figure 13 and Figure 14 , Figure 12 which is Figure 4 a schematic diagram of the planar layout of the middle fixing plate in Figure 13 and Figure 4 a schematic diagram of the split structure of the middle fixing plate in Figure 14 and

[0066] As shown in Figure 12 、 Figure 13 and Figure 14 , the fixing layer 112, the conductive layer 122 and the bottom plate 121 are stacked along the thickness direction, i.e., the first direction F1. The fixing layer 112, the conductive layer 122 and the bottom plate 121 have a rectangular cross-section, and the vacuum tube 123 is disposed through the center positions of the fixing layer 112, the conductive layer 122 and the bottom plate 121. A plurality of first conductive members 113 are disposed around the bottom plate 121 and are electrically connected to the first grounding layer 111 through the fixing layer 112. The conductive layer 122 can be a whole-surface metal sheet structure ( Figure 6 ), or a mesh structure ( Figure 10 ).

[0067] Among them, when the conductive layer 122 is simulated as the shielding cover in the electronic device 200, the thickness of the bottom plate 121 can be set according to the distance of the shielding cover 206 ( Figure 2 ), which is used to simulate the distance between the integrated circuit under test A and the shielding cover 206 in the electronic device 200. When the bottom plate 121 is made of a resin material, the dielectric constant of the resin material is somewhat different from that of air, usually between 2 and 4. Therefore, when setting the thickness of the bottom plate 121, calculations need to be made according to the actual situation to reduce errors. For example, taking a 50-ohm microstrip line as an example, according to the microstrip line characteristic impedance calculation formula:

[0068]

[0069] it can be known that when the thickness of the resin with a dielectric constant of 2.5 is about 1.63 mm, it is equivalent to the effect of 1 mm of air medium. At the same time, due to the complex internal circuit of the integrated circuit or the radio frequency circuit, when determining the thickness of the resin material, electromagnetic field simulation between the radio frequency chip and the shielding cover also needs to be carried out to finally determine the thickness of the bottom plate 121.

[0070] Please refer to Figure 15 , Figure 15 which is Figure 4 a schematic diagram of the process flow for adjusting the thickness of the bottom plate 121 in the first fixing plate of the test device in

[0071] As shown in Figure 4As shown, when the test device 100 performs electrical performance testing on the integrated circuit A to be tested, the effect of the shielding cover 206 in the electronic device 200 is simulated through the ground loop formed by the conductive layer 122, the first conductive member 113, and the second conductive member 23. Among them, the distance between the conductive layer 122 and the integrated circuit A to be tested is mainly controlled to simulate Figure 2 the shielding cover 206 in the shown electronic device 200 to achieve the same shielding effect. Therefore, it is necessary to reversely adjust the distance between the conductive layer 122 and the integrated circuit A to be tested according to the distance between the shielding cover 206 and the integrated circuit B. Since there is a bottom plate 121 between the integrated circuit A to be tested and the conductive layer 122 when the grasping part controls the integrated circuit A to be located in the groove 21, and the bottom plate 121 is an insulating layer, the distance between the conductive layer 122 and the integrated circuit A to be tested can be adjusted by adjusting the thickness of the bottom plate 121.

[0072] As Figure 15 shown, during the process of manufacturing the first fixing plate 10 of the test device or when adjusting the thickness of the bottom plate 121 during use, the specific steps include:

[0073] S101, determine the distance between the integrated circuit and the shielding cover in the electronic device, and obtain the first scattering parameter value through simulation.

[0074] When the integrated circuit B ( Figure 2 ) is arranged on the printed circuit board 204 in the electronic device 200, assume that the distance between the integrated circuit B and the shielding cover 206 is 0.1 mm, that is, the medium between the integrated circuit B and the shielding cover 206 is air at this time. Then, the scattering parameters between the integrated circuit B and the shielding cover 206 are determined through simulation, that is, the S parameters, which are also the scattering parameters when the medium between the integrated circuit B and the shielding cover 206 is air, denoted as the first scattering parameter value. Among them, the integrated circuit A to be tested is the integrated circuit during factory testing, and the integrated circuit B is the integrated circuit arranged in the electronic device, and the only difference between the two is the setting position.

[0075] S102, set the preset medium material between the integrated circuit and the shielding cover, and adjust the thickness of the preset medium material, and obtain the second scattering parameter value through simulation.

[0076] Specifically, set the bottom plate 121 between the integrated circuit B and the shielding cover 206 as the preset medium material, for example, it can be set as a resin material, and determine the scattering parameters between the integrated circuit B and the shielding cover 206 through simulation, that is, the scattering parameters when the medium between the integrated circuit B and the shielding cover 206 is the bottom plate 121, denoted as the second scattering parameter value.

[0077] S103. When the difference between the first scattering parameter value and the second scattering parameter value is within a preset range, obtain the thickness of a preset dielectric material and use it as the thickness of the bottom plate in the test device, where the preset dielectric material is the same as the bottom plate material.

[0078] By adjusting the preset dielectric material to a preset thickness, to control the difference between the first scattering parameter and the second scattering parameter within a preset range. Preferably, the first scattering parameter is equal to the second scattering parameter. At this time, the scattering parameter when the medium between the integrated circuit B and the shielding cover 206 is air is equivalent to the scattering parameter when the medium between the integrated circuit B and the shielding cover 206 is the preset dielectric material, and the bottom plate 121 in the test device 100 is also made of the preset dielectric material. Therefore, it can be determined that the scattering parameter when the bottom plate 121 reaches the preset thickness is the same as the scattering parameter between the integrated circuit B and the shielding cover 206 in the electronic device 200, thus realizing the simulation of the shielding effect of the shielding cover 206 in the electronic device. That is to say, the distance between the conductive layer 122 and the integrated circuit A to be tested in the test device can be adjusted by adjusting the thickness of the bottom plate 121, so as to realize the simulation of the shielding effect of the shielding cover 206 in the electronic device 200, and further eliminate the deviation of the integrated circuit between the test device and the electronic device.

[0079] The above-disclosed are only some embodiments of the present application. Of course, the scope of rights of the present application cannot be limited thereby. Those of ordinary skill in the art can understand all or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A testing device, characterized in that, It includes a first fixing plate, a second fixing plate and a circuit board. The first fixing plate and the second fixing plate are arranged at a preset distance from each other along a first direction. The circuit board is disposed on a side of the second fixing plate away from the first fixing plate. The second fixing plate includes a groove, and a plurality of thimbles connected to the circuit board are arranged in the groove. The first fixing plate is used to pick up an integrated circuit under test and move it into the groove. The thimbles are used to electrically connect the integrated circuit under test and the circuit board. The circuit board is used to perform electrical performance tests on the integrated circuit under test. Wherein, the first fixing plate includes a main body portion and a grasping portion which are stacked in sequence along the first direction. The main body portion includes a first grounding layer and a fixing layer. The fixing layer is disposed between the first grounding layer and the grasping portion. The grasping portion is disposed opposite to the groove. The grasping portion includes a bottom plate, a conductive layer and a vacuum tube. The conductive layer and the bottom plate are stacked in sequence along the first direction. The conductive layer is disposed adjacent to the main body portion. The vacuum tube is disposed through the conductive layer and the bottom plate along the first direction. The grasping portion picks up the integrated circuit under test through the vacuum tube; The first fixing plate further includes at least one first conductive member, and the second fixing plate further includes at least one second conductive member. The first conductive member and the second conductive member are disposed opposite to each other along the first direction. The circuit board includes a second grounding layer. The second conductive member is electrically connected to the second grounding layer. When the integrated circuit under test is located in the groove, a grounding loop is formed among the conductive layer, the first conductive member, the second conductive member and the integrated circuit under test to shield the integrated circuit under test during the test of the integrated circuit under test.

2. The test device according to claim 1, characterized in that The first conductive member is disposed around the grasping portion and partially embedded in a side of the fixing layer adjacent to the second fixing plate. The second conductive member is disposed around the groove and partially embedded in the second fixing plate. When the first fixing plate and the second fixing plate are assembled by overlapping each other, the first conductive member abuts against the second conductive member and is electrically connected.

3. The testing device according to claim 2, wherein A conductor is disposed in the fixing layer. The first conductive member, the conductive layer and the first grounding layer are electrically connected through the conductor. The integrated circuit under test is electrically connected to the second grounding layer through the thimble.

4. The test device according to claim 3, wherein The conductor includes at least one first conductor disposed along the first direction and at least one second conductor disposed along a second direction. The first conductor is connected to the first grounding layer and the conductive layer. The second conductor is connected between the first conductor and the first conductive member. Wherein, the first direction is perpendicular to the second direction.

5. The test device according to claim 3, characterized in that, The conductive layer has a sheet structure or a mesh structure.

6. The testing device according to claim 4, characterized in that The test device further includes at least one elastic member, the elastic member is disposed between the first conductive member and the second conductor, the elastic member is electrically connected to the first ground layer through the second conductor and the first conductor, and / or the elastic member is disposed between the second conductive member and the second ground layer, and the second conductive member is electrically connected to the second ground layer through the elastic member.

7. The test device according to claim 6, wherein, The bottom of the groove includes a contact area, a plurality of the thimbles are arranged in an array in the contact area, and the second fixing plate further includes at least one shielding plate, and the shielding plate is arranged between the side wall of the groove and the contact area along the first direction for shielding the integrated circuit under test.

8. The testing device according to claim 7, wherein, The second fixing plate includes four shielding plates, the contact area is rectangular in shape, and the four shielding plates are arranged in the groove along the first direction and are respectively adjacent to four sides of the contact area to enclose the contact area.

9. The test device according to claim 8, characterized in that, The four shielding plates are connected end to end in the groove to form an accommodating space, and the contact area is located in the accommodating space.

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