Flash memory chip testing method

Abstract

The invention discloses a flash memory chip test method. The method comprises the following steps: providing a plurality of flash memory chips; performing dynamic power consumption test on the plurality of flash memory chips during erasing operation to obtain power consumption values corresponding to the flash memory chips; performing outlier statistics according to the power consumption values of the plurality of flash memory chips, and determining outlier flash memory chips; and removing the outlier flash memory chips. According to the scheme, the flash memory chips with some process defects can be removed in the yield testing stage, and the quality of the flash memory chips flowing into a terminal user is guaranteed.

Description

Technical Field

[0001] This application relates to the technical field of flash memory testing, and particularly to a method for testing flash memory chips. Background Art

[0002] As an integrated circuit storage device, flash memory is widely used in electronic products such as portable computers, mobile phones, digital music players, etc. because it has the function of electrically erasable and writable storage of information, and the stored information will not be lost after power-off.

[0003] In the power supply scheme design, multiple charge pumps are usually designed on the flash memory chip to provide corresponding voltages for each storage unit in the flash memory. When the charge pump operates at high frequency, some process defects will cause some devices in the charge pump to fail during frequent use, and then cause device damage, such as burnout of high-voltage NMOS, leakage in the flash memory area, etc. In the existing flash memory yield testing, it is very difficult to simulate the situation of frequent use of the charge pump at the terminal by conventional flash memory function tests such as fine-tuning (trim) of the conventional erase voltage VEE and programming voltage VEP. Once a chip with such defects is shipped as a normal sample and put into the terminal market, during the continuous use of the end user, it may cause the charge pump to fail quickly, and then become a terminal reliability failure event. Summary of the Invention

[0004] Embodiments of this application provide a method for testing flash memory chips to eliminate flash memory chips with some process defects as much as possible during the yield testing stage, and ensure the quality of flash memory chips flowing into end users.

[0005] Embodiments of this application provide a method for testing flash memory chips, and the method includes:

[0006] Providing a plurality of flash memory chips;

[0007] Performing dynamic power consumption testing on the plurality of flash memory chips during an erase operation to obtain power consumption values corresponding to each flash memory chip;

[0008] Performing outlier statistics based on the power consumption values of the plurality of flash memory chips to determine outlier flash memory chips;

[0009] Eliminating the outlier flash memory chips.

[0010] Optionally, the performing dynamic power consumption testing on the plurality of flash memory chips during an erase operation to obtain power consumption values corresponding to each flash memory chip includes:

[0011] Performing dynamic power consumption testing on the plurality of flash memory chips during an erase operation before conventional function testing to obtain power consumption values corresponding to each flash memory chip; and / or

[0012] Performing a dynamic power consumption test during the erasure operation of the multiple flash memory chips after a conventional functional test to obtain the power consumption values corresponding to each flash memory chip.

[0013] Optionally, the method further includes:

[0014] Performing a DC characteristic and parameter trimming test on the multiple flash memory chips before performing the dynamic power consumption test during the erasure operation of the multiple flash memory chips;

[0015] After the test passes, performing the operation of the dynamic power consumption test during the erasure operation.

[0016] Optionally, the conventional functional test includes any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming, and interference test.

[0017] Optionally, the performing a dynamic power consumption test during the erasure operation of the multiple flash memory chips to obtain the power consumption values corresponding to each flash memory chip includes:

[0018] Connecting the power supply terminal of the flash memory chip to the working power supply, applying an erase voltage on all word lines and maintaining it for a certain period of time, and measuring the current flowing through the power supply terminal;

[0019] Calculating the power consumption value of the flash memory chip according to the voltage of the working power supply and the measured current.

[0020] Optionally, the performing outlier statistics based on the power consumption values of the multiple flash memory chips to determine the outlier flash memory chips includes:

[0021] Calculating the mean and standard deviation of the power consumption values of the multiple flash memory chips;

[0022] Determining the outlier flash memory chips according to the mean and standard deviation.

[0023] Optionally, the determining the outlier flash memory chips according to the mean and standard deviation includes: determining the outlier flash memory chips based on the 3-sigma principle according to the mean and standard deviation.

[0024] Optionally, the performing a dynamic power consumption test during the erasure operation of the multiple flash memory chips includes:

[0025] Performing a dynamic power consumption test during the erasure operation of the multiple flash memory chips before the conventional functional test to obtain the first power consumption value corresponding to each flash memory chip;

[0026] Performing a dynamic power consumption test during the erasure operation of the multiple flash memory chips after the conventional functional test to obtain the second power consumption value corresponding to each flash memory chip;

[0027] Performing outlier statistics based on the power consumption values of the multiple flash memory chips to determine outlier flash memory chips includes:

[0028] Performing outlier statistics based on the first power consumption value and the second power consumption value of the multiple flash memory chips respectively to determine outlier flash memory chips.

[0029] Optionally, the flash memory chip includes a memory cell array, the memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells are split-gate flash memory cells; each memory cell includes a floating gate and a bit line; the memory cells in each column share the bit line.

[0030] Optionally, the split-gate flash memory cell includes two memory structures that share a source region and are symmetrically distributed; the memory structure includes a drain region and the source region in a substrate, the drain region is connected to the bit line, a floating gate and a word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on one side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0031] The flash memory chip testing method provided by the embodiments of the present application screens out and eliminates outlier flash memory chips with abnormal power consumption during the yield testing stage through dynamic power consumption testing and outlier statistics during the erasing of the flash memory chips, effectively improving the reliability of the flash memory chips, greatly reducing the risk that flash memory chips with potential problems, especially charge pump leakage, flow into the terminal market and cause terminal failures.

[0032] Further, the dynamic power consumption testing during the erasing of multiple flash memory chips can be performed before the conventional function testing or after the conventional function testing, and the implementation methods are flexible and diverse.

[0033] Further, the dynamic power consumption testing during the erasing of multiple flash memory chips can also be performed before and after the conventional function testing respectively, and outlier statistics are performed based on the results of the two dynamic power consumption tests respectively, so as to fully eliminate outlier flash memory chips with potential problems and ensure the quality of the flash memory chips flowing into the market. Description of the Drawings

[0034] Figure 1 is a flowchart of a flash memory testing method provided by an embodiment of the present application;

[0035] Figure 2 is a schematic structural diagram of a flash memory in an embodiment of the present application;

[0036] Figure 3 is a schematic principle diagram of a flash memory in an embodiment of the present application. Detailed Embodiments

[0037] To make the above objects, features, and beneficial effects of the present application more obvious and understandable, the following will provide a detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

[0038] It should be noted that unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] The terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0040] Through the statistical analysis of some terminal failure samples of flash memory chips in use, it can be known that there are usually the following two commonalities for terminal failures caused by process defects:

[0041] (1) The charge pump of the flash memory chip operates abnormally;

[0042] (2) Some data during the erasure and programming of the flash memory show obvious differences from normal flash memory chips, and this phenomenon is more obvious during the erasure of the flash memory.

[0043] In response to the above problems and based on the statistical analysis of terminal failure samples, the embodiments of the present application provide a flash memory testing method. During the CP (Chip Probing) testing stage, by performing dynamic power consumption testing on the flash memory chip during erasure, outlier analysis is performed on the obtained dynamic power consumption values to screen out outlier samples. Although the anomalies of outlier samples are not all caused by the failure of the charge pump, through this method, flash memory chips with potential risks caused by various process defects can be screened out to a certain extent to avoid shipping them as normal samples.

[0044] CP testing is for uncut wafers, and it is necessary to use probes to contact the test pads on the wafer, and single or multiple Dies (chips) on the wafer can be tested at one time. CP testing generally includes three stages of testing, namely: CP1 tests the basic storage read and write functions and writes certain content into the storage chip; then the wafer undergoes high-temperature baking and then CP2 testing to detect whether the previously written data can be retained; finally, the logic function of the MCU (main control unit) part is tested.

[0045] The main test process of CP1 is as follows:

[0046] (1)DC parameter and trim test:

[0047] DC parameter test mainly includes: short circuit, open circuit, maximum current, leakage current, output drive current, turn-on level and other tests. For example, the open / short test is mainly used to detect whether there is a short circuit between the pins of the chip and whether there is a missing bonding wire during chip packaging; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0048] Trim is the process of adjusting some internal circuit parameters during chip testing. These parameters can be reference voltage, bias current, bandgap voltage, and / or oscillator circuit frequency, etc. Trim test can measure the values of some parameters in the circuit. If the parameter values deviate from the target values, the parameters can also be corrected and adjusted to meet the requirements of the parameter specifications. By trimming the parameters through trim, the yield of the chip can be greatly improved. The trimming of parameters in the chip through trim can be achieved by increasing or decreasing the resistance value of the corresponding resistor network.

[0049] (2)Flash general function test:

[0050] It mainly includes but is not limited to: read test, write test, erase test, logic test, performance test, programming, and interference test, etc. For example, the erase / read test is mainly used to screen out chips that cannot complete basic erase, programming, and read / write operations. During the test, the chip performs erase and programming operations on a single sector or the entire flash memory array at different operating voltages, and then performs a read operation on the chip to determine whether it can pass the test.

[0051] (3)Write a flag to NVR1 and erase the chip

[0052] During this process, all sectors will be erased.

[0053] CP2 test is mainly to perform a function test on the baked chip to detect its data retention ability. Usually, the CP2 test process mainly includes the following steps:

[0054] (1)Open / short test and leakage test

[0055] Similar to the corresponding steps in CP1 test, the open / short test is mainly used to detect whether there is a short circuit between the pins of the chip and whether there is a missing bonding wire during chip packaging; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0056] (2)NVR1 verification

[0057] Used to verify whether the flag written into NVR1 in the CP1 test is correct.

[0058] (3) Data retention ability and endurance test

[0059] Data retention ability refers to the ability of a storage cell to maintain its programmed state within an acceptable time period.

[0060] The endurance test is to characterize the maximum number of program / erase (P / E) cycles that a storage cell can withstand without failure.

[0061] In the flash memory test method provided by the embodiments of the present application, a dynamic power consumption test during erasing of the flash memory chip is added in the CP1 test stage. This test process can be a dynamic power consumption test during erasing of the multiple flash memory chips before the regular functional test to obtain the power consumption values corresponding to each flash memory chip; and / or a dynamic power consumption test during erasing of the multiple flash memory chips after the regular functional test to obtain the power consumption values corresponding to each flash memory chip.

[0062] It should be noted that the specific items and test methods of the regular functional test may vary according to the type of the flash memory chip and the manufacturer, and the embodiments of the present application do not make any limitations in this regard.

[0063] The following combines Figure 1 to make a detailed description of the flash memory test method provided by the embodiments of the present application.

[0064] As Figure 1 shown, it is a flowchart of a flash memory test method provided by the embodiments of the present application, including the following steps:

[0065] Step 101, provide multiple flash memory chips.

[0066] The flash memory chip includes a memory cell array, and the memory cell array includes a plurality of memory cells arranged in a matrix. The memory cell can be a split-gate flash memory cell or a memory cell with other structures related to a charge pump, and the embodiments of the present application do not make any limitations in this regard. Each of the memory cells includes a floating gate and a bit line.

[0067] The flash memory chip can be of NAND type (memory cells connected in series) or NOR type (memory cells connected in parallel, that is, the memory cells in each column are connected to the same bit line), and the embodiments of the present application do not make any limitations in this regard.

[0068] The following takes the split-gate flash memory cell as an example to briefly describe its structure and principle. At the same time, refer to Figure 2 and Figure 3 , where Figure 2 is a schematic structural diagram of a flash memory in the embodiments of the present application, Figure 3It is a schematic diagram of the principle of the flash memory in the embodiments of the present application.

[0069] The flash memory includes a memory cell array, and the memory cell array includes a plurality of memory cells A arranged in a matrix. The memory cells are split-gate flash memory cells; each memory cell includes a floating gate 11 and a bit line 13; the memory cells in each column share one bit line 13. A plurality of split-gate flash memory cells are formed side by side on a semiconductor substrate. The material of the semiconductor substrate can be silicon, germanium, silicon germanium, silicon carbide, etc., or it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or it can also be other materials, such as group III-V compounds such as gallium arsenide.

[0070] In this embodiment, a split-gate flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory cell includes a drain region 15 formed in the semiconductor substrate, a source region 14, and a source line (not shown) formed on the semiconductor substrate and connected to the source region 14. The source line is located above the source region 14. Among them, the drain region 15 is connected to the bit line 13, a word line 21 is formed between the source region 14 and the drain region 15, and two word lines 21 of the same split-gate flash memory cell are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and sidewalls are formed on the semiconductor substrate between the source line and the word line 21. A tunneling oxide layer is formed between the floating gate 11 and the word line 21. The materials of the floating gate 11, the word line 21, and the source line can all be polysilicon. A floating gate tip is formed on one side of the floating gate 11 close to the word line 21. The left memory structure and the right memory structure are symmetrically distributed and share the source line. In this embodiment, the source region 14 and the drain region 15 are both N-type doped, for example.

[0071] When programming this split-gate flash memory cell, the word line 21 serves as a control gate. A high voltage is applied to the source region 14, a voltage that can open the channel is applied to the word line 21, and a constant current is injected through the drain region 15. And the source region 14 is at a high potential. Under the action of the high potential, on the one hand, hot electrons will be generated in the channel, and on the other hand, the high potential will be coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel into the floating gate 11, thereby realizing programming. Programming is also called the write "0" operation.

[0072] As mentioned above, in the flash memory chip test method provided by the embodiments of the present application, the dynamic power consumption test process during the erasure of the flash memory chip can be carried out before the conventional functional test to obtain the power consumption values corresponding to each flash memory chip; and / or after the conventional functional test to obtain the power consumption values corresponding to each flash memory chip.

[0073] Accordingly, in some embodiments, the multiple flash memory chips may be flash memory chips that have passed DC parameters and trim tests but have not yet undergone conventional function tests.

[0074] In other embodiments, the multiple flash memory chips may be flash memory chips that have passed conventional function tests but have not yet written flags to NVR1.

[0075] Step 102, perform dynamic power consumption tests on the multiple flash memory chips during erasure to obtain power consumption values corresponding to each flash memory chip.

[0076] Specifically, connect the power supply terminals of each flash memory chip to the working power supply, apply an erasure voltage to all word lines and maintain it for a certain period of time, and measure the current flowing through the power supply terminals; calculate the power consumption values of each flash memory chip based on the voltage of the working power supply and the measured current.

[0077] In a conventional CP test, the normal erasure voltage VEE applied to the word line is, for example, 12V.

[0078] Refer to Figure 2 and Figure 3 , when erasing the split-gate flash memory cell, apply an erasure voltage VEE to all word lines. The tip of the floating gate reduces the channel voltage of the tunneling effect through the principle of tip discharge, enabling electrons to pass through the tunneling oxide layer from the tip of the floating gate 11 into the word line 21. After the storage unit is erased, the storage bit of the storage unit is in the "1" state, that is, all the storage units of the flash memory are erased and set to "1".

[0079] Since the duration of a complete erasure process is very short, in order to obtain an accurate current measurement value, after applying the erasure voltage, it can be maintained for a period of time (such as 5 - 10 ms) to make the current flowing through the power supply terminal reach stability.

[0080] It should be noted that the above test process can be completed by some existing test machines.

[0081] Step 103, perform outlier statistics based on the power consumption values of the multiple flash memory chips to determine outlier flash memory chips.

[0082] In some embodiments, outlier statistics of the power consumption values can adopt the 3-sigma principle. The 3-sigma principle is based on the normal distribution hypothesis, calculates the deviation values of data points from the mean, and classifies the data points into two categories: outliers and normal values according to the magnitude of the deviation.

[0083] The process of determining outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption values of the multiple flash memory chips; then determine the outlier flash memory chips based on the mean and standard deviation. Specifically, calculate the deviation value of each power consumption value from the mean. For a power consumption value whose deviation value is greater than 3 times the standard deviation, it is determined as an outlier, and the flash memory chip corresponding to this power consumption value is an outlier flash memory chip.

[0084] In some embodiments, other outlier statistical algorithms can also be used to determine outlier flash memory chips, such as: Dixon algorithm, Grubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc. The embodiments of this application do not limit this.

[0085] Step 104, eliminate outlier flash memory chips.

[0086] It should be noted that in specific implementation, the above tests can be performed on all flash memory chips to be tested and the outlier flash memory chips can be eliminated; or all flash memory chips to be tested can be divided into multiple groups, and the above tests are performed on each group respectively and the outlier flash memory chips are eliminated. The embodiments of this application do not limit this.

[0087] In some embodiments, for the same group of flash memory chips to be tested, before performing the conventional function test on them, the dynamic power consumption test during the above-mentioned erasure is performed on these flash memory chips to obtain the first power consumption value corresponding to each flash memory chip, and the outlier flash memory chips are screened out and eliminated according to the first power consumption value. Then, the remaining flash memory chips after eliminating the outlier flash memory chips are subjected to the conventional function test, and the dynamic power consumption test during the above-mentioned erasure is performed on the flash memory chips that pass the test again to obtain the second power consumption value corresponding to each flash memory chip, and the outlier flash memory chips are screened out and eliminated according to the second power consumption value. Through the two dynamic power consumption tests and screening processes, flash memory chips with some process defects can be more fully eliminated in the yield test stage, ensuring the quality of the flash memory chips flowing into the end users.

[0088] The flash memory chip test method provided by the embodiments of this application performs a dynamic power consumption test during the erasure of the flash memory chips in the CP test stage to simulate the dynamic power consumption of the flash memory chips when used in terminal products. Through the outlier statistics of the test results, the flash memory chips with outlier power consumption are screened out and eliminated in the yield test stage, effectively improving the reliability of the flash memory chips and greatly reducing the risk that flash memory chips with potential problems, especially charge pump leakage, flow into the terminal market and cause terminal failures.

[0089] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the front and rear associated objects are in an "or" relationship.

[0090] In the embodiments of the present application, "a plurality of" means two or more than two.

[0091] In the embodiments of the present application, the descriptions such as first and second are only used for indicating and distinguishing the described objects, without any order, and do not represent a special limitation on the number of devices in the embodiments of the present application, and shall not constitute any limitation to the embodiments of the present application.

[0092] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including the above method embodiments: the foregoing storage medium may include: various media such as ROM, RAM, magnetic disk, or optical disc that can store program codes.

[0093] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A flash memory chip testing method, characterized in that: The method comprises: Providing multiple flash memory chips; Performing dynamic power consumption testing on the multiple flash memory chips during an erase operation to obtain power consumption values ​​corresponding to each flash memory chip; Perform outlier statistics according to the power consumption values ​​of the plurality of flash memory chips to determine the outlier flash memory chip; The outlier flash memory chip is removed.

2. The flash memory chip testing method according to claim 1, characterized in that: The dynamic power consumption test when performing the erasing operation on the multiple flash memory chips to obtain the power consumption value corresponding to each flash memory chip includes: Performing a dynamic power consumption test on the multiple flash memory chips during an erase operation before a conventional functional test to obtain a power consumption value corresponding to each flash memory chip; and / or After the conventional functional test, a dynamic power consumption test is performed on the multiple flash memory chips during the erasing operation to obtain the power consumption value of each flash memory chip.

3. The flash memory chip testing method according to claim 1, characterized in that: The method further comprises: Before performing the dynamic power consumption test on the multiple flash memory chips during the erasing operation, performing a DC characteristic and parameter adjustment test on the multiple flash memory chips; After the test passes, the dynamic power consumption test during the erase operation is performed.

4. The flash memory chip testing method according to claim 2, characterized in that: The conventional functional test includes any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming and interference test.

5. The flash memory chip testing method according to claim 1, characterized in that: The dynamic power consumption test when performing the erasing operation on the multiple flash memory chips to obtain the power consumption value corresponding to each flash memory chip includes: Connecting the power supply terminal of the flash memory chip to a working power supply, applying an erase voltage to all word lines for a certain period of time, and measuring the current flowing through the power supply terminal; The power consumption value of the flash memory chip is calculated based on the voltage of the working power supply and the measured current.

6. The flash memory chip testing method according to claim 1, characterized in that: The performing outlier statistics according to the power consumption values ​​of the plurality of flash memory chips to determine the outlier flash memory chip comprises: Calculating the mean and standard deviation of the power consumption values ​​of the plurality of flash memory chips; Outlier flash memory chips are determined based on the mean and the standard deviation.

7. The flash memory chip testing method according to claim 6, characterized in that: Determining the outlier flash memory chip according to the mean and the standard deviation comprises: According to the mean and standard deviation, outlier flash memory chips are determined based on the 3-sigma principle.

8. The flash memory chip testing method according to claim 1, characterized in that: The dynamic power consumption test when performing an erase operation on the multiple flash memory chips includes: Performing a dynamic power consumption test on the multiple flash memory chips during an erase operation before a conventional functional test to obtain a first power consumption value corresponding to each flash memory chip; After the conventional functional test, a dynamic power consumption test is performed on the plurality of flash memory chips during an erasing operation to obtain a second power consumption value corresponding to each flash memory chip; The performing outlier statistics according to the power consumption values ​​of the plurality of flash memory chips to determine the outlier flash memory chip comprises: Outlier statistics are performed according to the first power consumption values ​​and the second power consumption values ​​of the plurality of flash memory chips respectively to determine the outlier flash memory chip.

9. The flash memory chip testing method according to any one of claims 1 to 8, characterized in that: The flash memory chip comprises a memory cell array, which comprises a plurality of memory cells arranged in a matrix, and the memory cells are split-gate flash memory cells; each of the memory cells comprises a floating gate and a bit line; and the memory cells in each column share the bit line.

10. The flash memory chip testing method according to claim 9, characterized in that: The split-gate flash memory unit includes two storage structures that share a source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

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