Digital pre-distortion high-precision phase interpolator with constant input load

Abstract

The invention relates to a digital pre-distortion high-precision phase interpolator with a constant input load. The digital pre-distortion high-precision phase interpolator comprises a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The two pre-filter circuits are used for converting the two full-swing square wave signals into two sine clocks; and the phase interpolation core circuit is used for carrying out nonlinear interpolation on the two paths of sine clocks according to the two paths of weight control codes by using a constant input load, and outputting a small-swing signal. According to the phase interpolator, the interpolation precision is greatly improved, digital pre-distortion of the interpolation weight can be realized by adjusting the control code decoder, the precision of the phase interpolator is further improved, a high-speed and high-precision output clock is realized, and the phase interpolator is suitable for clock generation modules such as a clock data recovery circuit and a phase-locked loop in a high-speed SerDes system.

Description

Technical Field

[0001] The present invention belongs to the technical field of design of mixed-signal integrated circuits, and particularly relates to a digital predistortion high-precision phase interpolator with a constant input load. Background Art

[0002] The increasing demands for communication and high-performance computing drive wired transceivers to operate at higher data rates, and the jitter and accuracy of the local clock directly determine the operating accuracy of the transceivers. Therefore, in order to achieve an efficient and high-speed data link, high-speed, high-precision, small-area, and low-power clock generation circuits have become a research hotspot.

[0003] A phase interpolator (PI) is used to adjust the clock phase in a clock generation circuit. Its working principle is as follows: The phase interpolator uses multiple input clocks with different phases, selects two adjacent input phases, and performs weighted interpolation. By adjusting the weights of the two phases, a clock with any phase can be output. Since the phase interpolator is completely excited by an external input clock and does not require an oscillator, it has better noise performance. Moreover, the phase interpolator directly performs phase feedback instead of frequency feedback, and its locking will be more accurate and stable compared with a voltage-controlled oscillator.

[0004] However, a traditional linear phase interpolator needs to use a triangular wave to achieve a high interpolation accuracy, but it is difficult to obtain an excellent triangular wave clock in an actual circuit, and there are certain offsets in the PI phasor constellation diagram and degradation of linearity in the traditional linear phase interpolator, which further affect the interpolation accuracy of the traditional linear phase interpolator. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a digital predistortion high-precision phase interpolator with a constant input load. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a digital predistortion high-precision phase interpolator with a constant input load, including: a multi-phase clock generation circuit, an input buffer circuit, two-way pre-filtering circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit, wherein,

[0007] The multi-phase clock generation circuit is used to divide the frequency of the input differential clock signal and output a four-phase quadrature clock with a 1 / 2 frequency;

[0008] The input buffer circuit is used to adjust the waveform and duty cycle of the four-phase quadrature clock and output two full-swing square wave signals;

[0009] The control code decoder circuit is used to decode according to the K-Bit binary control code and output a quadrant selection code and two weight control codes;

[0010] The two-channel pre-filter circuit is used to perform pre-interpolation quadrant selection, common-mode level adjustment, signal shaping and filtering on the two full-swing square wave signals in sequence according to the quadrant selection code and the first bias level, and convert the two full-swing square wave signals into two sine clocks;

[0011] The phase interpolation core circuit is used to perform non-linear interpolation on the two sine clocks according to the two weight control codes with a constant input load, and output a small-swing signal;

[0012] The CML2CMOS circuit is used to expand the small-swing signal into a full-swing signal and output it.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] A digital pre-distortion high-precision phase interpolator with a constant input load provided by the present invention, by performing non-linear interpolation on two sine clocks CLK according to two weight control codes WEIGHT with a constant input load, greatly improves the interpolation accuracy and is applicable to clock generation modules such as clock data recovery circuits and phase-locked loop circuits; moreover, the phase interpolator can realize digital pre-distortion of the interpolation weight by adjusting the control code decoder, further improving the accuracy of the phase interpolator and realizing a high-speed and high-precision output clock, which is applicable to clock generation modules such as clock data recovery circuits and phase-locked loops in high-speed SerDes (serializer / deserializer) systems. 0～2K-3 on two sine clocks CLK CML and realizing a high-speed and high-precision output clock, which is applicable to clock generation modules such as clock data recovery circuits and phase-locked loops in high-speed SerDes (serializer / deserializer) systems. Description of the Drawings

[0015] Figure 1 is a schematic circuit diagram of a digital pre-distortion high-precision phase interpolator with a constant input load provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic structural diagram of a multi-phase clock generation circuit provided by an embodiment of the present invention;

[0017] Figure 3 is a schematic structural diagram of a Latch provided by an embodiment of the present invention;

[0018] Figure 4 is a schematic principle diagram of a control code decoder circuit provided by an embodiment of the present invention;

[0019] Figure 5 is a schematic structural diagram of a pre-filter circuit provided by an embodiment of the present invention;

[0020] Figure 6 It is a schematic structural diagram of the phase interpolation core circuit provided by an embodiment of the present invention;

[0021] Figure 7 It is a schematic structural diagram of the phase interpolation unit provided by an embodiment of the present invention;

[0022] Figure 8 It is a performance comparison diagram between a traditional interpolation unit and the phase interpolation unit provided by an embodiment of the present invention. Specific embodiments

[0023] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0024] Embodiment 1

[0025] Please refer to Figure 1 , Figure 1 It is a schematic circuit structure diagram of a digital predistortion high-precision phase interpolator with a constant input load provided by an embodiment of the present invention.

[0026] A digital predistortion high-precision phase interpolator with a constant input load provided in this embodiment includes: a multi-phase clock generation circuit, an input buffer circuit, two-way pre-filtering circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit. The multi-phase clock generation circuit is used to divide the frequency of the input differential clock signal CLK IN to output a four-phase quadrature clock CLK DIV with a frequency of 1 / 2. The input buffer circuit is used to adjust the waveform and duty cycle of the four-phase quadrature clock CLK DIV and output two full-swing square wave signals CLK CORE_IN . The control code decoder circuit is used to decode according to the K-Bit binary control code (K-Bit Code) and output a quadrant selection code SEL 0～1 and two-way weight control codes WEIGHT 0～2K-3 . The two-way pre-filtering circuits are used to perform pre-interpolation quadrant selection, common-mode level adjustment, signal shaping and filtering on the two full-swing square wave signals CLK 0～1 in sequence according to the quadrant selection code SEL and the first bias level VB_CML, and convert the two full-swing square wave signals CLK CORE_IN into two sine clocks CLK CORE_IN . The phase interpolation core circuit is used to perform non-linear interpolation on the two sine clocks CLK CML with a constant input load according to the two-way weight control codes WEIGHT 0～2K-3 and output a small-swing signal CLK CML CORE OUT. The CML2CMOS circuit is used to expand the small swing signal CLK CORE_OUT into a full swing signal CLK OUT and output it.

[0027] In this embodiment, the differential clock signal CLK IN includes: a positive differential clock signal CLK IN，P and a negative differential clock signal CLK IN，N . The four-phase orthogonal clock CLK DIV includes: an I-channel forward clock CLK DIV，IP , an I-channel reverse clock CLK DIV，IN , a Q-channel forward clock CLK DIV，QP , and a Q-channel reverse clock CLK DIV，QN . The two-channel weight control code WEIGHT 0～2K-3 includes: an I-channel weight code WEIGHT I and a Q-channel weight code WEIGHT Q . The duty cycle of the two-channel full swing square wave signal CLK CORE_IN is 50%, and the two-channel full swing square wave signal CLK CORE_IN includes: an I-channel full swing square wave signal CLK CORE_IN，I and a Q-channel full swing square wave signal CLK CORE_IN，Q . The two-channel sinusoidal clock CLK CML includes: an I-channel sinusoidal clock CLK CML，I and a Q-channel sinusoidal clock CLK CML，Q . The two-channel sinusoidal clock CLK CML , the two-channel full swing square wave signal CLK CORE_IN and the small swing signal CLK CORE_OUT are all differential signals. Therefore, they can all be divided into positive differential signals and negative differential signals. Among them, the I-channel weight code WEIGHT I and the Q-channel weight code WEIGHT Q are respectively used to control the interpolation weights of the phase interpolation core circuit for the I-channel sinusoidal clock CLK CML，I and the Q-channel sinusoidal clock CLK CML，Q .

[0028] Please refer to Figure 2 , Figure 2 which is the structural schematic diagram of the multi-phase clock generation circuit provided by the embodiment of the present invention. In this embodiment, the multi-phase clock generation circuit drives two cascaded latches (Latch) through the differential clock signal CLK IN to generate the four-phase orthogonal clock CLK DIV . The multi-phase clock generation circuit includes: a first-stage Latch and a second-stage Latch. Among them, the driving end of the first-stage Latch inputs the positive differential clock signal CLK IN，P, the inverted output of the first - stage Latch is connected to the non - inverted input of the second - stage Latch and outputs the I - path non - inverted clock CLK DIV，IP , the non - inverted output of the first - stage Latch is connected to the inverted input of the second - stage Latch and outputs the I - path inverted clock CLK DIV，IN . The driving terminal of the second - stage Latch inputs the negative differential clock signal CLK IN，N , the non - inverted output of the second - stage Latch is connected to the non - inverted input of the first - stage Latch and outputs the Q - path inverted clock CLK DIV，QN , the inverted output of the second - stage Latch is connected to the inverted input of the first - stage Latch and outputs the Q - path non - inverted clock CLK DIV，QP . The input buffer circuit shapes the waveform of the four - phase quadrature clock CLK DIV into a full - swing square wave and adjusts the duty cycle to 50%.

[0029] Please refer to Figure 3 , Figure 3 which is the schematic structural diagram of the Latch provided by the embodiment of the present invention. In this embodiment, the structures of the first - stage Latch and the second - stage Latch are the same, and both include: transistors M P1 ~M P2 , transistors M N9 ~M N13 . Among them, the gate of transistor M N9 is the non - inverted input terminal. The gate of transistor M N10 is the inverted input terminal. The sources of transistors M N9 , M N10 are connected to the drain of transistor M N13 . The gate of transistor M N13 is the driving terminal, which inputs the differential clock signal CLK IN . The source of transistor M N13 is connected to the ground potential GND, the drains of transistors M N9 , M P1 , and the source of transistor M N12 are connected to the gate of transistor M P2 and output as the non - inverted output terminal. The drains of transistors M N10 , M P2 , M N11 are connected to the gate of transistor M P1 and output as the inverted output terminal. The sources of transistors M P1 , M P2 and the drains of transistors M N11 , M N12 are connected to the power supply potential VDD. In this Latch, transistor M N11 and transistor MN12 The source follower is configured to improve the speed by providing a feed - forward path for the output to minimize the system power consumption. It should be understood that the transistors M P1 ~M P2 are PMOS transistors, and the transistors M N9 ~M N13 are NMOS transistors.

[0030] Please refer to Figure 4 , Figure 4 , which is a schematic diagram of the principle of the control - code decoder circuit provided by the embodiment of the present invention. In this embodiment, the control - code decoder circuit is implemented by a pure combinational logic digital circuit. This embodiment adopts non - linear phase interpolation to decouple the weight control codes of two adjacent clocks, so that they can be adjusted separately. There are NxN available phase points within a single quadrant of the phasor constellation diagram, significantly increasing the design space and providing sufficient choices for N linear phase outputs within the corresponding quadrant. In this embodiment, with the number of I - path openings and the number of Q - path openings as the X - axis and Y - axis respectively, Figure 4 is its phasor constellation diagram. The control - code decoder circuit decodes according to the K - Bit binary control code to obtain the ideal output point coordinates of the interpolator. As Figure 4 shown, the nth ideal output point (interpolation point) of the interpolator is However, most of the ideal output points fall between the lattice points of the available phase points, and it is difficult for the actual circuit to accurately implement the corresponding weights. Therefore, in this embodiment, Matlab is used to calculate the modulus of the distance between the ideal output point and its four adjacent available phase points. The control - code decoder circuit selects the available phase point with the minimum modulus as the approximate output point, and converts the quadrant where the approximate output point is located into a quadrant selection code SEL 0～1 for output, and outputs the corresponding horizontal and vertical coordinates of the approximate output point as the I - path weight code WEIGHT I and the Q - path weight code WEIGHT Q . In use, the digital circuit of the control - code decoder circuit can be adjusted according to the actual test situation to modify the output weight value, obtain higher accuracy, and achieve digital pre - distortion.

[0031] Please refer to Figure 5 , Figure 5 , which is a schematic diagram of the structure of the pre - filter circuit provided by the embodiment of the present invention. The structure of each pre - filter circuit in the two - path pre - filter circuit is the same. One of the two - path pre - filter circuits is used to convert the I - path full - swing square - wave signal CLK CORE_IN，I into the I - path sinusoidal clock CLK CML，I , and the other is used to convert the Q - path full - swing square - wave signal CLK CORE_IN，Q into the Q - path sinusoidal clock CLK CML，Q .

[0032] In this embodiment, each pre-filter circuit includes a quadrant selection sub-circuit and a filter sub-circuit. Among them, the quadrant selection sub-circuit is used to control two full-swing square-wave signals CLK 0～1 to selectively flip according to the quadrant selection code SEL CORE_IN . The filter sub-circuit is connected to the output end of the quadrant selection sub-circuit, and adjusts the common-mode level of the two selectively flipped full-swing square-wave signals CLK CORE_IN according to the first bias level VB_CML, and then performs signal shaping and filtering in sequence to output two sinusoidal clocks CLK CML .

[0033] Furthermore, the quadrant selection sub-circuit includes transmission gates TRAN 1 ~TRAN 4 . The transmission gates TRAN 1 , TRAN 2 , TRAN 3 , TRAN 4 are all controlled by the quadrant selection code SEL 0～1 . The input ends of the transmission gates TRAN 1 , TRAN 2 are used as the reverse input ends, and the input ends of the transmission gates TRAN 3 , TRAN 4 are used as the forward input ends. The output ends of the transmission gates TRAN 1 , TRAN 3 are used as the first output ends, and the output ends of the transmission gates TRAN 2 , TRAN 4 are used as the second output ends.

[0034] In this embodiment, the filter sub-circuit includes an AC coupling module, a CML buffer, and a low-pass filter connected in sequence. Among them, the AC coupling module includes capacitors C 1 , C 2 , resistors R 1 , R 2 . The CML buffer includes transistors M N6 , M N7 , M N8 , resistors R 3 , R 4 . The low-pass filter includes capacitors C 3 , C 4 , resistors R 5 , R 6 . Among them, the first end of the capacitor C 1 is connected to the transmission gate TRAN 1The output terminal and transmission gate TRAN 3 The output terminal of, capacitor C 2 The first terminal of is connected to the transmission gate TRAN 2 The output terminal and transmission gate TRAN 4 The output terminal of, capacitor C 1 The second terminal of is connected to the resistor R 1 The first terminal of and transistor M N6 The gate of, capacitor C 2 The second terminal of is connected to the resistor R 2 The first terminal of and transistor M N7 The gate of, resistor R 1 And R 2 The second terminal of is connected to the third bias level VCM, transistor M N6 And M N7 The source terminal of is connected to the drain terminal of transistor M N8 The gate of transistor M N8 is connected to the first bias level VB_CML, transistor M N8 The source terminal of is connected to the ground potential GND, transistor M N6 The drain terminal of is connected to the resistor R 3 The first terminal of and resistor R 5 The first terminal of, transistor M N7 The drain terminal of is connected to the load resistor R 4 The first terminal of and the filter resistor R 6 The first terminal of, load resistor R 3 And R 4 The second terminal of is connected to the power supply potential VDD, filter resistor R 5 The second terminal of and the filter capacitor C 3 The first terminal of which is connected and used as the reverse output terminal, filter resistor R 6 The second terminal of and the filter capacitor C 5 The first terminal of which is connected and used as the forward output terminal, capacitor C 3 And capacitor C 4 The second terminal of is connected to the ground potential GND. Taking the full-swing square-wave signal CLK of the I channel CORE_IN And the sinusoidal clock CLK of the I channel CML，I As an example, the positive differential signal CLK of the full-swing square-wave signal CLK of the I channel CORE_IN，I Is input from the forward input terminal, the negative differential signal CLK of the full-swing square-wave signal CLK of the I channel CORE_IN，IP Is input from the reverse input terminal, the positive differential signal CLK of the sinusoidal clock CLK of the I channel CORE_IN，I Is output from the forward output terminal, the negative differential signal CLK of the sinusoidal clock CLK of the I channel CORE_IN，IN Is output from the reverse output terminal, the positive differential signal CLK of the sinusoidal clock CLK of the I channel CML，I Is output from the forward output terminal, the negative differential signal CLK of the sinusoidal clock CLK of the I channel CML，IP Is output from the forward output terminal, the negative differential signal CLK of the sinusoidal clock CLK of the I channel CML，I Is output from the reverse output terminal, the negative differential signal CLK of the sinusoidal clock CLK of the I channel CML，INOutput from the reverse output terminal.

[0035] Specifically, the 4 transmission gates in each pre-filter circuit perform clock inversion according to the quadrant selection code SEL 0～1 The first quadrant has positive I and positive Q, the second quadrant has positive I and negative Q, the third quadrant has negative I and negative Q, and the fourth quadrant has negative I and positive Q. Subsequently, through the AC coupling module, the common-mode level of the two full-swing square-wave signals CLK CORE_IN is adjusted to ensure the normal operation of the CML buffer. The CML buffer converts the two full-swing square-wave signals CLK CORE_IN into CML signals that can be processed by the interpolation core. And high-pass filtering is achieved through the AC coupling module, and the CML buffer and the low-pass filter jointly achieve low-pass filtering, so that the entire pre-filter circuit exhibits a band-pass characteristic, converting the input square-wave clock (two full-swing square-wave signals CLK CORE_IN ) into a sine clock (two sine clocks CLK CML ) that is more suitable for non-linear interpolation.

[0036] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of the phase interpolation core circuit provided by an embodiment of the present invention. The phase interpolation core circuit includes: an I-channel phase interpolation circuit and a Q-channel phase interpolation circuit. Among them, the control code input terminal of the I-channel phase interpolation circuit inputs the I-channel weight code WEIGHT I , the differential clock input terminal of the I-channel phase interpolation circuit inputs the I-channel sine clock CLK CML，I , and the current source bias input terminal of the I-channel phase interpolation circuit inputs the second bias level VB_CORE. The control code input terminal of the Q-channel phase interpolation circuit inputs the Q-channel weight code WEIGHT Q , the differential clock input terminal of the Q-channel phase interpolation circuit inputs the Q-channel sine clock CLK CML，Q , and the current source bias input terminal of the Q-channel phase interpolation circuit inputs the second bias level VB_CORE. The output terminals of the I-channel phase interpolation circuit and the Q-channel phase interpolation circuit are connected to jointly output a small-swing signal CLK CORE_OUT .

[0037] In this embodiment, the I-channel phase interpolation circuit and the Q-channel phase interpolation circuit have the same structure, both including: 2 K-2 phase interpolation units and a load resistor R L，CORE . Each phase interpolation unit has a pair of differential clock input terminals, a weight control code input terminal, a current source transistor bias input terminal, and a pair of differential output terminals. The positive differential output terminals of the 2 K-2 phase interpolation units in the I-channel phase interpolation circuit and the 2 K-2The positive differential output terminals of the phase interpolation units are connected to output a positive differential small swing signal CLK CORE_OUT，P , and connect the load resistor R in the Q-path phase interpolation circuit L，CORE One end of the I phase interpolation circuit. K-2 The negative differential output terminal of the phase interpolation unit and the Q-path phase interpolation circuit 2 K-2 The negative differential output terminals of the phase interpolation units are connected to each other to jointly output a negative differential small swing signal CLK CORE_OUT，N , and connect the load resistor R in the I-way phase interpolation circuit L，CORE The load resistor R in the Q-path phase interpolation circuit L，CORE The other end and the load resistor R in the I-way phase interpolation circuit L，CORE The other end of each is connected to the power supply potential VDD. The I-way phase interpolation circuit and the Q-way phase interpolation circuit have a total of 2 K-1 Phase interpolation unit, two weight control codes WEIGHT 0～2K-3 The binary value is input to the weight control code input terminal of the corresponding phase interpolation unit.

[0038] Specifically, the linear interpolation of the traditional phase interpolator has a better interpolation effect when the input clock is a triangle wave, while for nonlinear interpolation, a sine wave input will bring higher interpolation accuracy. Furthermore, for the traditional linear phase interpolator with four-phase input, its two sets of clock interpolation weights (ω I and ω Q ) has ω I +ω Q = N is a constant value. In the two clocks (CLK I and CLK Q ) is a triangle wave:

[0039]

[0040] Among them, θ is the angle between the interpolation point and the y-axis, and the analysis interval is 0 to 2π, which can be simplified as:

[0041]

[0042] From formulas (2) and (3), we can see that CLK I and CLK Q The interpolation result is still a piecewise function, and its waveform and swing amplitude are different under different weight control codes. The zero crossing point of the piecewise function can be expressed as:

[0043]

[0044] Under the condition of linear interpolation, ω I +ω Q=N is a constant value. The zero-crossing approximation can approximately represent the phase of the output waveform at this time. At this time, the sampling point phase of the triangular wave interpolation output clock changes linearly with the clock weight, with high interpolation accuracy and good linearity. However, there is still AM-to-PM (amplitude-to-phase) modulation, the interpolation output phase deviates, and there are defects in the interpolation accuracy.

[0045] For the non-linear phase interpolator with four-phase input, by decoupling the control codes of the two clock weights and selecting the actual weight codes as close as possible to the ideal output phase in the phasor constellation diagram, the weight ω I [n] and ω Q [n] approximately vary sinusoidally with respect to the control code n from 0 to 2 N -1. At this time, by summing the two groups of sinusoidal clocks with different weights ω I [n] and ω Q [n], a clock with a fine phase step can be generated:

[0046]

[0047] where θ 0 is the inherent phase of the input clock, A PI [n] is the swing of the output clock, θ PI [n] is the phase of the output clock, that is, A PI [n] is a constant value, and θ PI [n] varies linearly with the control code n. Therefore, a sinusoidal wave input can obtain a constant output amplitude and a linear phase shift in the non-linear phase interpolation core circuit, achieving higher interpolation accuracy.

[0048] In this embodiment, the input two full-swing square wave signals CLK in the form of a square wave are converted into two sinusoidal clocks CLK in the form of a sinusoidal wave through a pre-filter circuit CORE_IN . And by constructing interpolation units for the two sinusoidal clocks CLK CML respectively, the weight codes for interpolating the two clocks are decoupled into the I-channel weight code WEIGHT CML that controls the interpolation weight of the I-channel phase interpolation circuit and the Q-channel weight code WEIGHT I that controls the interpolation weight of the Q-channel phase interpolation circuit. Interpolation is achieved through non-linear interpolation, significantly increasing the design space and improving the interpolation accuracy. In addition, by adjusting the combinational logic in the control code decoder, pre-calibration of the interpolation weight can be realized, thereby optimizing the interpolation accuracy under different PVTs. Q Please refer to

[0049] See Figure 7 , Figure 7It is a schematic structural diagram of a phase interpolation unit provided by an embodiment of the present invention. In this embodiment, each phase interpolation unit includes: transistor M N1 , transistor M N2 , transistor M N3 , transistor M N4 , transistor M N5 , single-pole double-throw switch S 1 and single-pole double-throw switch S 2 . Among them, the source of transistor M N1 , the source of transistor M N2 , the source of transistor M N3 , the source of transistor M N4 are connected to the drain of transistor M N5 . The gate of transistor M N5 is connected to the second bias level VB_CORE. The source of transistor M N5 is connected to the ground potential GND. The gates of transistor M N1 and transistor M N2 are connected to the positive differential clock input terminal IN P . The gates of transistor M N3 and transistor M N4 are connected to the negative differential clock input terminal IN N . The drain of transistor M N1 is connected to the negative differential output terminal OUT N . The drain of transistor M N2 is connected to the input terminal of single-pole double-throw switch S 1 . The drain of transistor M N4 is connected to the positive differential output terminal OUT P . The drain of transistor M N3 is connected to the input terminal of single-pole double-throw switch S 2 . The first output terminal of single-pole double-throw switch S 1 is connected to the negative differential output terminal OUT N . The second output terminal of single-pole double-throw switch S 1 is connected to the positive differential output terminal OUT P . The first output terminal of single-pole double-throw switch S 2 is connected to the positive differential output terminal OUT P . The second output terminal of single-pole double-throw switch S 2 is connected to the negative differential output terminal OUT N . The control terminals of single-pole double-throw switches S 1 and S 2 are connected to the weight control code input terminal.

[0050] Furthermore, please refer to Figure 8 . Figure 8(a) in it is a comparison schematic diagram of the input swing of traditional linear interpolation and the non-linear interpolation provided by the embodiment of the present invention fluctuating with the input PI Code (K-bit binary control code). It can be seen from the figure that the input load of traditional linear interpolation is not constant, resulting in a large change in the input swing of the phase interpolator and affecting the interpolation accuracy; while the fluctuation amplitude of the input swing of the non-linear interpolation provided by the embodiment of the present invention with the input PI Code significantly decreases, and the circuit improvement effect is remarkable. Figure 8 (b) in it is a comparison schematic diagram of the ideal single-quadrant integral non-linearity of traditional linear interpolation and the non-linear interpolation provided by the embodiment of the present invention. It can be seen from the figure that the interpolation accuracy of the traditional linear interpolation method is relatively low, and the integral non-linearity is 2.890 LSB; while the interpolation accuracy of the non-linear interpolation method provided by the embodiment of the present invention is significantly improved, and the integral non-linearity is only 0.712 LSB.

[0051] When the traditional interpolation unit is turned off, the input pair transistors are turned off, resulting in different numbers of transistors in the clock load under different interpolation weights, that is, the input load of the interpolation core is not constant, reducing the interpolation accuracy. In this embodiment, the gate voltage of the current source transistor (transistor M N5 ) is controlled by the second bias level VB_CORE, so as to achieve that the current in the phase interpolation core circuit remains constant under different process corners, that is, the working state of the phase interpolation core circuit is stable, and the input clock (two-way sinusoidal clock CLK CML ) is connected to two constantly working transistors (M N1 , M N2 or M N3 , M N4 ), and the opening and closing of the interpolation unit are realized by changing the type of signal combination at the output end, instead of changing the working state of the input pair transistors. Specifically, when the two outputs of one clock (the drains of M N1 , M N2 or the drains of M N3 , M N4 ) are connected to the same differential output end, the differential signal is transmitted and the phase interpolation unit is turned on; when the two outputs are connected to two differential output ends, only the common-mode level is transmitted without differential signals, and the phase interpolation unit is turned off. In this embodiment, the input load of the phase interpolation core circuit remains constant, which can effectively improve the interpolation accuracy.

[0052] A digital predistortion high-precision phase interpolator with a constant input load provided by this embodiment, according to two weight control codes WEIGHT 0～2K-3 with a constant input load, for two-way sinusoidal clocks CLK CMLNonlinear interpolation is performed, greatly improving the interpolation accuracy, which is applicable to clock generation modules such as clock data recovery circuits and phase-locked loop circuits; moreover, this phase interpolator can achieve pre-calibration of the interpolation weight by adjusting the control code decoder, further improving the accuracy of the phase interpolator, realizing a high-speed and high-precision output clock, and being applicable to clock generation modules such as clock data recovery circuits and phase-locked loops in high-speed SerDes systems.

[0053] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A digital predistortion high-precision phase interpolator with constant input load, characterized in that: include: Multi-phase clock generation circuit, input buffer circuit, two-way pre-filter circuit, phase interpolation core circuit, CML2CMOS circuit, control code decoder circuit, among which, The multi-phase clock generating circuit is used to divide the frequency of the input differential clock signal and output a four-phase orthogonal clock with 1 / 2 frequency; The input buffer circuit is used to adjust the waveform and duty cycle of the four-phase orthogonal clock and output two full-swing square wave signals; The control code decoder circuit is used to decode the K-Bit binary control code and output the quadrant selection code and the two-way weight control code; The two-channel pre-filter circuit is used to sequentially perform pre-interpolation quadrant selection, common mode level adjustment, signal shaping and filtering on the two-channel full-swing square wave signals according to the quadrant selection code and the first bias level, and convert the two-channel full-swing square wave signals into two-channel sinusoidal clocks; The phase interpolation core circuit is used to perform nonlinear interpolation on the two sinusoidal clocks according to the two weight control codes with a constant input load, and output a small swing signal; The CML2CMOS circuit is used to expand the small swing signal into a full swing signal and output it.

2. The digital predistortion high-precision phase interpolator with constant input load according to claim 1, characterized in that: The two-way weight control code includes: I-way weight code WEIGHT I and Q road weight code WEIGHT Q ; The duty cycle of the two full-rail square wave signals is 50%. The two full-rail square wave signals include: I full-rail square wave signal CLK CORE_IN，I And Q-channel full-rail square wave signal CLK CORE_IN，Q ; The two sinusoidal clocks include: I sinusoidal clock CLK CML，I And Q-way sinusoidal clock CLK CML，Q ; The I-path weight code WEIGHT I and the Q path weight code WEIGHT Q are respectively used to control the phase interpolation core circuit to the I-way sinusoidal clock CLK CML，I and the Q-channel sinusoidal clock CLK CML，Q The interpolation weights.

3. The digital predistortion high-precision phase interpolator with constant input load according to claim 2, characterized in that: The control code decoder circuit is used to decode according to the K-Bit binary control code and output the quadrant selection code and the two-way weight control code, including: The control code decoder circuit obtains the coordinates of the ideal output point of the phase interpolator according to the K-Bit binary control code, selects the available phase point with the smallest distance modulus from the ideal output point as the approximate output point, outputs the quadrant selection code according to the quadrant of the approximate output point, and outputs I-way weight code WEIGHT according to the horizontal coordinate and the vertical coordinate of the approximate output point. I and Q road weight code WEIGHT Q .

4. The digital predistortion high-precision phase interpolator with constant input load according to claim 2, characterized in that: The phase interpolation core circuit includes: an I-phase interpolation circuit and a Q-phase interpolation circuit, wherein: The I-way phase interpolation circuit, the control code input terminal inputs the I-way weight code WEIGHT I , the differential clock input terminal inputs the I-channel sinusoidal clock CLK CML，I , a second bias level is input to the current source bias input terminal; The Q-path phase interpolation circuit inputs the Q-path weight code WEIGHT at the control code input terminal. Q , the differential clock input terminal inputs the Q-way sinusoidal clock CLK CML，Q , a second bias level is input to the current source bias input terminal; The output end of the I-path phase interpolation circuit is connected to the output end of the Q-path phase interpolation circuit to jointly output the small swing signal.

5. The digital predistortion high-precision phase interpolator with constant input load according to claim 4, characterized in that: The I-path phase interpolation circuit and the Q-path phase interpolation circuit have the same structure, both comprising: K-2 A phase interpolation unit and a load resistor R L，CORE , Each of the phase interpolation units has a pair of differential clock input terminals, a weight control code input terminal, a current source tube bias input terminal and a pair of differential output terminals; The I-way phase interpolation circuit 2 K-2 The positive differential output terminal of the phase interpolation unit and the Q-path phase interpolation circuit 2 K-2 The positive differential output terminals of the phase interpolation units are connected to each other to jointly output a positive differential small swing signal CLK CORE_OUT，P , and connect the Q-path phase interpolation circuit to the load resistor R L，CORE one end of The I-way phase interpolation circuit 2 K-2 The negative differential output terminal of the phase interpolation unit and the Q-path phase interpolation circuit 2 K-2 The negative differential output terminals of the phase interpolation units are connected to each other to jointly output a negative differential small swing signal CLK CORE_OUT，N , and connect the load resistor R in the I-way phase interpolation circuit L，CORE one end of The load resistor R in the Q-path phase interpolation circuit L，CORE The other end and the load resistor R in the I-way phase interpolation circuit L，CORE The other ends are connected to the power supply potential VDD.

6. The digital predistortion high-precision phase interpolator with constant input load according to claim 5, characterized in that: Each phase interpolation unit includes: a transistor M N1 , transistor M N2 , transistor M N3 , transistor M N4 , transistor M N5 , single-pole double-throw switch S1 and single-pole double-throw switch S2, where: Transistor M N1 The source of transistor M N2 The source of transistor M N3 The source of transistor M N4 The source of transistor M N5 The drain of transistor M N5 The gate of transistor M is connected to the second bias level. N5 The source of transistor M is connected to the ground potential GND. N1 The gate and transistor M N2 The gate of the positive differential clock input IN is connected P , transistor M N3 The gate and transistor M N4 The gate of the negative differential clock input IN N , transistor M N1 The drain of the negative differential output terminal OUT N , transistor M N2 The drain of the transistor M is connected to the input of the single-pole double-throw switch S1. N4 The drain of the positive differential output terminal OUT P , transistor M N3 The drain of is connected to the input terminal of the single-pole double-throw switch S2; The first output terminal of the single-pole double-throw switch S1 is connected to the negative differential output terminal OUT N The second output terminal of the single-pole double-throw switch S1 is connected to the positive differential output terminal OUT P The first output terminal of the single-pole double-throw switch S2 is connected to the positive differential output terminal OUT P The second output terminal of the single-pole double-throw switch S2 is connected to the negative differential output terminal OUT N , the control ends of the single-pole double-throw switches S1 and S2 are connected to the weight control code input end.

7. The digital predistortion high-precision phase interpolator with constant input load according to claim 1, characterized in that: The differential clock signal includes: a positive differential clock signal CLK IN，P and negative differential clock signal CLK IN，N ; The four-phase orthogonal clock includes: I-way positive clock CLK DIV，IP , I-way reverse clock CLK DIV，IN , Q-way positive clock CLK DIV，QP , Q-way reverse clock CLK DIV，QN ; The multi-phase clock generation circuit includes: a first-stage latch and a second-stage latch, wherein: The driving end of the first-level latch inputs the positive differential clock signal CLK IN，P The reverse output of the first-stage latch is connected to the positive input of the second-stage latch and outputs a positive clock CLK. DIV，IP The positive output of the first-stage latch is connected to the negative input of the second-stage latch and outputs a reverse clock CLK. DIV，IN ; The driver of the second-stage latch inputs the negative differential clock signal CLK IN，N The positive output of the second-stage latch is connected to the positive input of the first-stage latch and outputs the Q-path reverse clock CLK DIV，QN The reverse output of the second-stage latch is connected to the reverse input of the first-stage latch and outputs the Q-path positive clock CLK DIV，QP .

8. The digital predistortion high-precision phase interpolator with constant input load according to claim 2, characterized in that: Each of the two pre-filter circuits has the same structure. One of the two pre-filter circuits is used to convert the I-way full-swing square wave signal CLK CORE_IN，I Convert to I-channel sinusoidal clock CLK CML，I , and the other is used to convert the Q-channel full-swing square wave signal CLK CORE_IN，Q Convert to Q-channel sinusoidal clock CLK CML，Q ; Each pre-filter circuit includes a quadrant selection subcircuit and a filter subcircuit, wherein: The quadrant selection subcircuit is used to control the selective flipping of the two full-swing square wave signals according to the quadrant selection code; The filtering subcircuit is connected to the output end of the quadrant selection subcircuit, performs common-mode level adjustment on the two full-swing square wave signals after selective flipping according to the first bias level, and performs signal shaping and filtering in sequence to output the two sinusoidal clocks.

9. The digital predistortion high-precision phase interpolator with constant input load according to claim 8, characterized in that: The quadrant selection subcircuit includes a transmission gate TRAN1, a transmission gate TRAN2, a transmission gate TRAN3, and a transmission gate TRAN4, wherein: The transmission gates TRAN1, TRAN2, TRAN3 and TRAN4 are all controlled by the quadrant selection code, the input end of the transmission gate TRAN1 and the input end of the transmission gate TRAN2 serve as reverse input ends, the input end of the transmission gate TRAN3 and the input end of the transmission gate TRAN4 serve as forward input ends, the output end of the transmission gate TRAN1 and the output end of the transmission gate TRAN3 serve as first output ends, and the output end of the transmission gate TRAN2 and the output end of the transmission gate TRAN4 serve as second output ends.

10. The digital predistortion high-precision phase interpolator with constant input load according to claim 9, characterized in that: The filtering subcircuit includes an AC coupling module, a CML buffer and a low-pass filter connected in sequence, wherein the AC coupling module includes a capacitor C1, a capacitor C2, a resistor R1, and a resistor R2, and the CML buffer includes a transistor M N6 , transistor M N7 , transistor M N8 , resistor R3, resistor R4, the low-pass filter includes capacitor C3, capacitor C4, resistor R5, resistor R6; The first end of the capacitor C1 is connected to the output end of the transmission gate TRAN1 and the output end of the transmission gate TRAN3, the first end of the capacitor C2 is connected to the output end of the transmission gate TRAN2 and the output end of the transmission gate TRAN4, and the second end of the capacitor C1 is connected to the first end of the resistor R1 and the transistor M N6 The gate of the capacitor C2 is connected to the first end of the resistor R2 and the transistor M N7 The gate of the transistor M is connected to the third bias level VCM. N6 and M N7 The source terminal of transistor M is connected N8 The drain terminal of transistor M N8 The gate of transistor M is connected to the first bias level. N8 The source terminal of transistor M is connected to the ground potential GND. N6 The drain end of the transistor M is connected to the first end of the resistor R3 and the first end of the resistor R5. N7 The drain end is connected to the first end of the load resistor R4 and the first end of the filter resistor R6, the second ends of the load resistors R3 and R4 are connected to the power supply potential VDD, the second end of the filter resistor R5 and the first end of the filter capacitor C3 are connected as a reverse output end, the second end of the filter resistor R6 and the first end of the filter capacitor C5 are connected as a forward output end, and the second ends of the capacitors C3 and C4 are connected to the ground potential GND.

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