Reading circuit, image sensor, chip and control method
By setting up a signal conversion circuit in the CTIA circuit to adjust the high and low voltage of the reset signal, the problem of difficulty in completely eliminating reset noise in the CTIA circuit is solved, and a lower noise level is achieved, which is suitable for the readout circuit of infrared focal plane array.
Patent Information
- Application Number
- CN202510232944.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-06-03
AI Technical Summary
Reset noise in existing CTIA circuits is difficult to completely eliminate, and there is room for further reduction.
The signal conversion circuit is set at the reset signal input end of the CTIA circuit. By adjusting the voltage at the internal source of the inverter, the high-level voltage value of the reset signal and/or the low-level voltage value are increased, thereby reducing the pressure difference between the high and low voltages.
The noise caused by clock feedthrough and charge injection effects in the CTIA circuit is reduced, and the reset noise is further reduced, without changing the original structure of the CTIA circuit.
Smart Images
Figure CN120091234A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of integrated circuits, and particularly relates to a readout circuit, an image sensor, a chip, and a control method. Background Art
[0002] An infrared focal plane array (IRFPA) mainly consists of a two-dimensional detector array and a readout circuit. The detector array is placed on the focal plane of an imaging optical system to detect infrared radiation signals. Among many types of CMOS readout circuits, the capacitor trans-impedance amplifier (CTIA) circuit has become the main application object due to its many advantages such as high injection efficiency, stable detector bias voltage, and good linearity.
[0003] Regarding the reset noise of the CTIA circuit, the correlated double sample (CDS) structure commonly used in the prior art cannot completely eliminate it, and there is still room for further reduction. Summary of the Invention
[0004] A readout circuit, an image sensor, a chip, and a control method proposed in this application are used to reduce the reset noise in the CTIA circuit.
[0005] To achieve the above object, the following technical solutions are proposed in this application: In the first aspect of this application, a readout circuit is provided, including: A capacitor feedback trans-impedance amplifier circuit; A signal conversion circuit, including an inverter, and is arranged at the input terminal of the capacitor feedback trans-impedance amplifier circuit for receiving the reset signal, and reduces the first voltage value and / or increases the second voltage value by adjusting the source terminal voltage of the inverter.
[0006] Wherein, the first voltage value represents the voltage value of the high level in the reset signal, and the second voltage value represents the voltage value of the low level in the reset signal.
[0007] Optionally, the signal conversion circuit includes: A first inverter, composed of a first PMOS transistor and a first NMOS transistor, for receiving the reset signal and converting it into an inverted signal; wherein, the voltage values of the high and low levels of the inverted signal and the reset signal are the same; A second inverter, composed of a second PMOS transistor and a second NMOS transistor, is connected to the output terminal of the first inverter, for converting the inverted signal, and reduces the first voltage value and / or increases the second voltage value by adjusting the first source terminal voltage and / or the second source terminal voltage; Wherein, the first source voltage represents the input voltage of the source terminal of the second PMOS transistor; the second source voltage represents the input voltage of the source terminal of the second NMOS transistor.
[0008] Optionally, the first source voltage is lower than the input voltage of the source terminal of the first PMOS transistor; the second source voltage is higher than the input voltage of the source terminal of the first NMOS transistor.
[0009] Optionally, the first source voltage and the second source voltage include the following limiting conditions: V TH +V O_CLAMP <V RL <V TH +V REF and V TH +V REF <V RH <V DD ; Wherein, V TH represents the threshold voltage of the reset transistor in the capacitive feedback transimpedance amplifier circuit, and the reset transistor is used to receive a reset signal; V O_CLAMP represents the minimum output voltage of the capacitive feedback transimpedance amplifier circuit that conforms to the range of the ADC circuit, and the ADC circuit represents a circuit that converts the output voltage of the capacitive feedback transimpedance amplifier circuit into a pixel value after combining with a source follower; V RL represents the second source voltage; V REF represents the reference voltage in the capacitive feedback transimpedance amplifier circuit; V RH represents the first source voltage; V DD represents the input voltage of the source terminal of the first PMOS transistor.
[0010] Optionally, the signal conversion circuit further includes: A first adjustment circuit, connected to the source terminal of the second PMOS transistor, for adjusting the value of the first source voltage according to a control signal; A second adjustment circuit, connected to the source terminal of the second NMOS transistor, for adjusting the value of the second source voltage according to a control signal.
[0011] Optionally, the first adjustment circuit is composed of a plurality of third PMOS transistors connected in parallel; Wherein, the drain terminals of the third PMOS transistors are all connected to the source terminal of the second PMOS transistor; the gate terminals of the third PMOS transistors are used to receive a control signal to control the connection state of the third PMOS transistors; the source terminals of the third PMOS transistors respectively receive input voltages with different values, and the highest value of the input voltage is lower than the input voltage of the source terminal of the first PMOS transistor.
[0012] Optionally, the second adjustment circuit is composed of multiple third NMOS transistors connected in parallel; Among them, the drain terminals of the third NMOS transistors are all connected to the source terminal of the second PMOS transistor; the gate terminals of the third NMOS transistors are used to receive control signals to control the connection state of the third NMOS transistors; the source terminals of the third NMOS transistors receive input voltages with different values respectively, and the lowest value of the input voltage is higher than the input voltage of the source terminal of the first NMOS transistor.
[0013] In the second aspect of the present application, an image sensor is provided, including: A pixel array including a plurality of pixel units arranged in an array; A pixel readout module including a plurality of column processing units that respectively read voltage signals from each column of pixel units; wherein, each column processing unit includes the readout circuit according to any one of the first aspect.
[0014] In the third aspect of the present application, a chip is provided, and the chip includes the image sensor according to the second aspect.
[0015] In the fourth aspect of the present application, a control method is provided, which is applied to a readout circuit including a capacitive feedback transimpedance amplifier circuit, and the control method includes: Reducing the first voltage value of the reset signal in the capacitive feedback transimpedance amplifier circuit and / or increasing the second voltage value of the reset signal; Wherein, the first voltage value represents the voltage value of the high level in the reset signal, and the second voltage value represents the voltage value of the low level in the reset signal.
[0016] The beneficial effects of the present application are as follows: The present application provides a readout circuit, including: a capacitive feedback transimpedance amplifier circuit; a signal conversion circuit including an inverter, and is arranged at the input terminal of the capacitive feedback transimpedance amplifier circuit for receiving the reset signal, and reduces the first voltage value and / or increases the second voltage value by adjusting the source terminal voltage in the inverter.
[0017] Wherein, the first voltage value represents the voltage value of the high level in the reset signal, and the second voltage value represents the voltage value of the low level in the reset signal.
[0018] Based on the above circuit design, the present application sets a signal conversion circuit at the input terminal of the reset signal to reduce the first voltage value and / or increase the second voltage value, that is, reduces the voltage difference between the high level and the low voltage in the reset signal, thereby reducing the noise brought by the clock feedthrough and charge injection effects in the CTIA circuit, and further reducing the reset noise.
[0019] In addition, compared with the existing schemes for reducing reset noise, the present application does not need to modify the original structure of the CTIA circuit. Instead, by means of signal processing, the differential pressure between the high and low voltages in the reset signal is reduced to reduce the reset noise, effectively improving the adaptability and convenience of the scheme. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of this application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a schematic structural diagram of an existing CTIA circuit provided by the present application; Figure 2 is a schematic structural diagram of another existing CTIA circuit provided by the present application; Figure 3 is a schematic structural diagram of a readout circuit provided by the present application; Figure 4 is a schematic structural diagram of a sampling circuit provided by the present application; Figure 5 is a schematic structural diagram of a signal conversion circuit provided by the present application; Figure 6 is a schematic structural diagram of another signal conversion circuit provided by the present application; Figure 7 is a schematic diagram of the process of reset signal conversion provided by the present application; Figure 8 is a schematic structural diagram of a pixel column readout circuit provided by the present application; Figure 9 is a schematic structural diagram of a reset transistor provided by the present application; Figure 10 is a schematic structural diagram of a resistor string voltage dividing circuit provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application.
[0022] With the development of information technology, infrared optoelectronic imaging technology has gradually played an increasingly important role in fields such as industrial control, medical services, and information detection. The infrared focal plane array (IRFPA), as a key device in infrared optoelectronic imaging technology, mainly consists of two parts: a two-dimensional detector array and a readout circuit. For the readout circuit of the infrared focal plane array, a capacitor trans-impedance amplifier (CTIA) circuit is mainly used for construction.
[0023] See Figure 1 , this application provides a schematic diagram of the structure of an existing CTIA circuit. As Figure 1 shown, the CTIA circuit mainly consists of an integrating capacitor (C HG and C LG ), an operational amplifier, a reset switch, and a gain control switch gain_sel.
[0024] Among them, V RST1 represents the original reset signal input to the reset transistor (i.e., the reset switch); V REF represents the reference signal of the operational amplifier; V DD represents the power supply voltage in the CTIA circuit and serves as the high level of the original reset signal; GND represents the ground and serves as the low level of the original reset signal; CTIA_OUT represents the output signal of the CTIA circuit.
[0025] In Figure 1 the circuit structure shown, the photodiode converts the optical signal into an electrical current signal, which serves as the input signal of the CTIA circuit, and the CTIA circuit converts this electrical current signal into a voltage signal.
[0026] It should be noted that in the technical solution provided in this application, the CTIA circuit is an existing circuit in the prior art, and this application does not limit the specific structure of the CTIA circuit. As Figure 2 shown, this application also provides a schematic diagram of the structure of another existing CTIA circuit, which consists of an integrating capacitor C INT , an operational amplifier, and a reset switch S RESET .
[0027] To meet the higher detection accuracy of the infrared focal plane array, higher requirements are put forward for the noise suppression effect in the readout circuit. Among them, for the reset noise caused by the reset signal in the CTIA circuit, most of the prior art eliminates it by adjusting the circuit structure (such as, adopting a correlated double sampling structure). However, in actual operation, the above method cannot completely eliminate the reset noise, and there is still room for further reduction.
[0028] To further suppress the reset noise in the CTIA circuit, refer to Figure 3 , this application provides a schematic structural diagram of a readout circuit, as shown in Figure 3 , the readout circuit includes: CTIA circuit.
[0029] A signal conversion circuit, including an inverter, is arranged at the input end of the CTIA circuit for receiving the reset signal, and reduces the first voltage value and / or increases the second voltage value by adjusting the source-end voltage of the inverter.
[0030] Wherein, the first voltage value represents the voltage value of the high level in the reset signal, and the second voltage value represents the voltage value of the low level in the reset signal.
[0031] Based on the above circuit design, this application sets a signal conversion circuit at the input end of the reset signal to reduce the first voltage value and / or increase the second voltage value, that is, to narrow the voltage difference between the high level and the low voltage in the reset signal, thereby reducing the noise caused by clock feedthrough and charge injection effects in the CTIA circuit, and further reducing the reset noise.
[0032] In addition, compared with the existing reset noise reduction scheme, this application does not need to modify the original structure of the CTIA circuit, but uses the signal processing method to reduce the reset noise by narrowing the voltage difference between the high and low voltages in the reset signal, effectively improving the adaptability and convenience of the scheme.
[0033] The working principle of the readout circuit provided by this application is described as follows: Taking the Figure 1 shown existing CTIA circuit as an example, in the reset stage, after the reset switch receives the high level of the reset signal, it opens and resets CTIA_OUT to the reference voltage V REF . After that, when the reset switch receives the low level of the reset signal, the reset stage ends and the reset switch closes. At this time, the jump from the high level to the low level in the reset signal will be coupled to the inverting terminal and the output terminal of the operational amplifier through the gate-source and gate-drain capacitances, and the charge injection in the channel will also generate reset noise.
[0034] Taking the Figure 4 shown sampling circuit as an example, the reset noise caused by charge injection and clock feedthrough is described as follows. When a MOSFET (metal-oxide-semiconductor field-effect transistor, that is, the reset transistor or reset switch of this application) is in the on state, there must be a channel at the interface between silicon dioxide and silicon. When the reset switch is turned off, the charge in the channel will flow out through the source and drain terminals, which is called channel charge injection. The charge injected to the right will be deposited on the sampling capacitor C HAs a result, an error is generated in the voltage value stored in the sampling capacitor. Here, Vin represents the input voltage of the MOSFET, CK represents the clock signal, and Vout represents the output voltage of the MOSFET.
[0035] In addition to channel charge injection, in the MOSFET, the transition from high level to low level in the reset signal is also coupled to the sampling capacitor through its gate-drain or gate-source overlapping capacitance, that is, there is a clock feedthrough effect, which also introduces an error to the output voltage.
[0036] Since the magnitudes of the noises generated by charge injection and clock feedthrough are positively correlated with the voltage drop of the transition in the reset signal. Therefore, when the voltage drop of the reset signal becomes smaller, the noises brought by the charge injection effect and the clock feedthrough effect will also decrease, thereby reducing the reset noise.
[0037] In some embodiments, as Figure 5 、 6 shown, the signal conversion circuit provided by the present application includes: A first inverter, composed of a first PMOS (P-Metal-Oxide-Semiconductor) transistor and a first NMOS (N-Metal-Oxide-Semiconductor) transistor, is configured to receive the reset signal V RST1 and convert it into an inverted signal V RSTB . Among them, the voltage values of the high and low levels of the inverted signal and the reset signal are the same. Taking the CTIA circuit structure shown in Figure 3 as an example, the high levels of both the reset signal and the inverted signal are the power supply voltage V DD in the CTIA circuit, and the low levels are both the ground terminal GND.
[0038] A second inverter, composed of a second PMOS transistor and a second NMOS transistor, is connected to the output terminal of the first inverter, and is configured to convert the inverted signal, and by adjusting the first source voltage V RH and / or the second source voltage V RL , to reduce the first voltage value and / or increase the second voltage value, so as to obtain the converted reset signal V RST2 .
[0039] Among them, the first source voltage V RH represents the input voltage of the source terminal of the second PMOS transistor; the second source voltage V RL represents the input voltage of the source terminal of the second NMOS transistor.
[0040] In some embodiments, the first source voltage is lower than the input voltage of the source terminal of the first PMOS transistor, and the second source voltage is higher than the input voltage of the source terminal of the first NMOS transistor. That is, VRH <V DD ,V RL >0. As shown in Figure 7 the figure, Figure 7 it is a schematic diagram of the conversion process of a reset signal provided by this application.
[0041] The readout circuit provided by this application serves as a pre-signal processing circuit in the IRFPA and generally also includes an SF (Source Follower). As shown in Figure 8 the figure, the source follower on the right drives and inputs the output signal of the CTIA circuit into the subsequent ADC (Analog-to-Digital Converter) circuit to obtain pixel values.
[0042] The signal current of a short-wavelength infrared (SWIR) detector is greatly affected by the light source, resulting in the signal current at night being much smaller than that during the day. Using the same integration capacitor is likely to cause a problem of a narrow dynamic range. Therefore, the existing readout circuits for SWIR use two types of integration capacitors, that is, a large capacitor is used as the integration capacitor during the day, and a small capacitor is used as the integration capacitor at night. The two integration capacitors are globally controlled for all pixels through external digital processing.
[0043] However, when using a small capacitor for integration at night, a suddenly appearing high-intensity light source will cause saturation in some parts, reducing the quality of the imaging effect. Specifically, the output signal of the CTIA circuit and the RAMP (ramp voltage signal) are respectively the two inputs of the SSADC (single-slope analog-to-digital converter) circuit. Due to the input range limitation of the ADC circuit, when the CTIA output signal is too low, no output result can be generated or an incorrect result is output. As shown in Figure 8 the figure, the source follower amplifier drives and outputs the output signal of the CTIA circuit. When CTIA_OUT is too low, it will cause the voltage of sf_out to be lower than the quantization range of the ADC circuit, resulting in an incorrect result and affecting the imaging effect.
[0044] To solve the above problems and ensure the imaging effect of the IRFPA, in the readout circuit provided by this application, on the basis of satisfying that the first source terminal voltage is lower than the input voltage of the source terminal of the first PMOS transistor and the second source terminal voltage is higher than the input voltage of the source terminal of the first NMOS transistor, the signal conversion circuit can be used to adjust the converted reset signal V RST2The high level and low level. When the optical signal provided by the light source is too strong, the signal at the output end of the CTIA is clamped by the voltage of the RST transistor VRL, thus avoiding the continuous decrease of the voltage. That is, by adjusting the high level or low voltage of the reset signal through the signal conversion circuit, the clamping of the output signal of the CTIA circuit is achieved, and the voltage of sf_out is prevented from falling below the quantization range of the ADC circuit.
[0045] The principle of the above voltage clamping is described as follows: See Figure 9 , Figure 9 which is a schematic structural diagram of a reset transistor provided by this application. As Figure 9 shown, the reset transistor is an NMOS transistor, and V IN represents the input signal of the reset transistor, V DD represents the high level voltage value of the reset signal, and V TH represents the threshold voltage of the reset transistor.
[0046] For Figure 9 the NMOS transistor shown, the known cut-off condition is V GS < V TH . When the drain end of the NMOS transistor is connected to the input signal of V IN , the source end is connected to the output signal of Vout, and the gate end is connected to the reset signal of V DD , we get V GS = V DD , V DS = V DD . From this, it can be deduced that V DS > V GS - V TH , the NMOS transistor operates in the saturation region, charges the load capacitor, the output voltage rises, and the source-drain voltage drops; when Vout = V DD - V TH , that is, V GS = V DD - Vout = V TH , the channel is pinched off at the source and the NMOS transistor is cut off, so there is a threshold loss when the NMOS transistor transmits a high level.
[0047] Regarding the phenomenon of threshold loss when the NMOS transistor transmits a high level, when the reset signal is at the low level V RL and the output signal of the CTIA circuit is too low, the reset transistor conducts. Due to the clamping limit of the low level V RL voltage inside the reset transistor, the continuous decrease of the voltage is avoided.
[0048] In addition, due to the high level V RH and low level V RLAdjustable, so that the influence ratio of charge injection and clock feedthrough can be reasonably reduced, and the output voltage value of the appropriate CTIA circuit can be selected.
[0049] In some embodiments, the signal conversion circuit further includes: A first adjustment circuit, connected to the source terminal of the second PMOS transistor, for adjusting the value of the first source terminal voltage according to a control signal; A second adjustment circuit, connected to the source terminal of the second NMOS transistor, for adjusting the value of the second source terminal voltage according to a control signal.
[0050] As Figure 6 shown, the first adjustment circuit is composed of a plurality of third PMOS transistors connected in parallel, and the second adjustment circuit is composed of a plurality of third NMOS transistors connected in parallel.
[0051] Among them, the drain terminals of the third PMOS transistors are all connected to the source terminal of the second PMOS transistor; the gate terminals of the third PMOS transistors are used to receive a control signal to control the connection state of the third PMOS transistors; the source terminals of the third PMOS transistors receive input voltages with different values, and the highest value of the input voltage is lower than the input voltage of the source terminal of the first PMOS transistor.
[0052] The drain terminals of the third NMOS transistors are all connected to the source terminal of the second PMOS transistor; the gate terminals of the third NMOS transistors are used to receive a control signal to control the connection state of the third NMOS transistors; the source terminals of the third NMOS transistors receive input voltages with different values, and the lowest value of the input voltage is higher than the input voltage of the source terminal of the first NMOS transistor.
[0053] In Figure 6 the circuit structure shown, V RH1 、V RH2 to V RHN respectively represent the input voltages of the source terminals of different third PMOS transistors, corresponding to the voltage value of the high level of the reset signal V RST2 , that is, the first source terminal voltage of the present application. Hsel<1>, Hsel<2> to Hsel <n>Are respectively represented as control signals for the gate terminals of different third PMOS transistors, as the high-level voltage value V RH Of the voltage selection switch. Among them, N represents the total number of the input voltage of the source terminal or the control signal of the gate terminal of the third PMOS transistor.
[0054] Similarly, V RL1 , V RL2 To V RLM Are respectively represented as the input voltages of the source terminals of different third NMOS transistors, corresponding to the low-level voltage value of the reset signal V RST2 That is, the second source terminal voltage of this application. Lsel<1>, Lsel<2> to Hsel <m>Control signals respectively represented as gate terminals of different third NMOS transistors, as low-level voltage value V RL of the voltage selection switch. Among them, M represents the total number of input voltages or gate control signals at the source terminal of the third PMOS transistor.
[0055] For different input voltages in the first adjustment circuit and the second adjustment circuit, in the technical solution provided by the present application, it can be achieved by means of resistor string voltage division or a sliding resistor. As Figure 10 shown, the present application provides a schematic structural diagram of a resistor string voltage division circuit. This circuit connects multiple resistors in series, and the voltages at both ends are the power supply V DD and the ground terminal GND respectively. And the voltage taps are respectively connected to the ports of each source terminal in the first adjustment circuit and the second adjustment circuit, and multiple output voltages can be used as voltage values of different high and low levels respectively.
[0056] Referring to Figure 6 the voltage conversion circuit shown, appropriate voltages can be selected as the input voltage at the source terminal of the second inverter in the conversion circuit through the control signals Hsel<N:1> and Lsel<M:1>.
[0057] For example, when the control signal Hsel<5:1> is 11110, V RH is the V RH1 voltage; when vrh_sel<5:1> is 01111, VRH is the VRH5 voltage. Taking vrh_sel<5:1> being 11110 as an example, at this time only the VRH1 voltage passes through the control transistor as the VRH voltage. When the inverted signal VRSTB is GND, the PMOS transistor conducts, and VRST2 is VRH; when VRSTB is VDD, the NMOS transistor conducts, and VRST2 is VRL. Thus, the conversion of the reset signal can be completed.
[0058] In some embodiments, the first source voltage and the second source voltage include the following limiting conditions: V TH + V O_CLAMP < V RL < V TH + V REF , and V TH + V REF < V RH < V DD ; Among them, V TH represents the threshold voltage of the reset transistor in the CTIA circuit, and the reset transistor is used to receive the reset signal; V O_CLAMP represents the minimum CTIA circuit output voltage that meets the range of the ADC circuit, and the ADC circuit represents a circuit that converts the CTIA circuit output voltage into a pixel value after combining with a source follower. RL represents the second source voltage; V REF represents the reference voltage in the CTIA circuit; V RH represents the first source voltage; V DD represents the input voltage at the source of the first PMOS transistor.
[0059] Specifically, when the reset transistor receives a low level V RL , it has a clamping function and no additional circuit is required. After the reset is completed, the reset transistor is turned off. At this time, it is necessary to satisfy V RL < V TH + V REF . When the current signal generated by the photodiode is too large, CTIA_OUT is too low to make the reset transistor V GS (i.e., V RL - CTIA_OUT)> VTH, and it is turned on again. At this time, the output end of the CTIA circuit is clamped by the reset switch. Therefore, the range of the clamping voltage V RL also needs to be determined by the quantization range of the ADC circuit, that is, VRL > V TH + V O_CLAMP .
[0060] For V RH , in the technical solution provided in this application, on the one hand, it needs to be high enough to ensure the conduction of the reset transistor, that is, V RH > V TH + V REF , on the other hand, it also needs to be reduced as much as possible to limit the voltage difference between the high and low levels of the reset signal to reduce the reset noise. In actual use. It is necessary to flexibly adjust the values of V RH and V RL to adapt to the specific circuit and working scenario.
[0061] In some embodiments, the image sensor of this application includes: a pixel array including a plurality of pixel units arranged in an array.
[0062] a pixel readout module including a plurality of column processing units that respectively read voltage signals from each column of pixel units. Among them, each column processing unit includes the above-mentioned readout circuit.
[0063] In some embodiments, this application also provides a chip including the above-mentioned image sensor.
[0064] In some embodiments, this application also provides a control method applied to a readout circuit including a CTIA circuit. The control method includes: reducing the first voltage value of the reset signal in the CTIA circuit and / or increasing the second voltage value of the reset signal.
[0065] Among them, the first voltage value represents the voltage value of the high level in the reset signal, and the second voltage value represents the voltage value of the low level in the reset signal.
[0066] In the technical solution provided by this application, for the implementation methods of reducing the first voltage value and increasing the second voltage value, including but not limited to, replacing the reset signal with a lower first voltage value and / or a higher second voltage value, and re-inputting it into the CTIA circuit. Or directly change the high level and / or low level of the original reset signal, such as adjusting the original reset signal based on the signal conversion circuit provided by this application.
[0067] Based on the above processing, this application reduces the voltage difference between the high level and the low voltage in the reset signal by reducing the first voltage value and / or increasing the second voltage value, thereby reducing the noise brought by clock feedthrough and charge injection effects in the CTIA circuit, and further reducing the reset noise.
[0068] In addition, compared with the existing reset noise reduction solutions, this application does not need to modify the original structure of the CTIA circuit, but uses signal processing methods to reduce the reset noise by reducing the voltage difference between the high and low voltages in the reset signal, effectively improving the adaptability and convenience of the solution.
[0069] The above embodiments are only used to illustrate the technical solutions of this application, rather than to limit it; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of this application.< / m> < / n>
Claims
1. A readout circuit, characterized in that: include: Capacitive feedback transimpedance amplifier circuit; A signal conversion circuit, comprising an inverter, and arranged at an input end of the capacitive feedback transimpedance amplifier circuit for receiving a reset signal, and adjusting a source terminal voltage in the inverter to reduce a first voltage value and / or increase a second voltage value; The first voltage value represents a high-level voltage value in the reset signal, and the second voltage value represents a low-level voltage value in the reset signal.
2. The readout circuit according to claim 1, characterized in that The signal conversion circuit comprises: A first inverter, composed of a first PMOS tube and a first NMOS tube, is used to receive a reset signal and convert it into an inverted signal; wherein the high and low level voltage values of the inverted signal and the reset signal are the same; A second inverter, composed of a second PMOS transistor and a second NMOS transistor, connected to the output end of the first inverter, used for converting the inverted signal, and reducing the first voltage value and / or increasing the second voltage value by adjusting the first source terminal voltage and / or the second source terminal voltage; The first source terminal voltage represents the input voltage of the source terminal of the second PMOS tube; the second source terminal voltage represents the input voltage of the source terminal of the second NMOS tube.
3. The readout circuit according to claim 2, characterized in that: The first source terminal voltage is lower than the input voltage of the first PMOS tube source terminal; the second source terminal voltage is higher than the input voltage of the first NMOS tube source terminal.
4. The readout circuit according to claim 3, characterized in that: The first source terminal voltage and the second source terminal voltage include the following limiting conditions: V TH +V O_CLAMP <V RL <V TH +V REF and V TH +V REF <V RH <V DD ; Among them, V TH represents the threshold voltage of the reset transistor in the capacitive feedback transimpedance amplifier circuit, wherein the reset transistor is used to receive the reset signal; V O_CLAMP V represents the minimum output voltage of the capacitive feedback transimpedance amplifier circuit in the range of the ADC circuit, and the ADC circuit represents a circuit that converts the output voltage of the capacitive feedback transimpedance amplifier circuit into a pixel value after combining with a source follower; V RL Represents the second source terminal voltage; V REF Represents the reference voltage in the capacitive feedback transimpedance amplifier circuit; V RH Represents the voltage of the first source terminal; V DD Represents the input voltage of the source terminal of the first PMOS tube.
5. The readout circuit according to claim 2, characterized in that: The signal conversion circuit also includes: A first regulating circuit, connected to the source end of the second PMOS tube, and used for adjusting the value of the voltage at the first source end according to the control signal; The second regulating circuit is connected to the source end of the second NMOS tube and is used to adjust the value of the second source end voltage according to the control signal.
6. The readout circuit according to claim 5, characterized in that: The first regulating circuit is composed of a plurality of third PMOS tubes connected in parallel; Among them, the drain end of the third PMOS tube is connected to the source end of the second PMOS tube; the gate end of the third PMOS tube is used to receive a control signal to control the connectivity state of the third PMOS tube; the source end of the third PMOS tube receives input voltages of different values, and the highest value of the input voltage is lower than the input voltage of the source end of the first PMOS tube.
7. The readout circuit according to claim 5, characterized in that: The second regulating circuit is composed of a plurality of third NMOS tubes connected in parallel; Among them, the drain end of the third NMOS tube is connected to the source end of the second PMOS tube; the gate end of the third NMOS tube is used to receive a control signal to control the connectivity state of the third NMOS tube; the source end of the third NMOS tube receives input voltages of different values, and the lowest value of the input voltage is higher than the input voltage of the source end of the first NMOS tube.
8. An image sensor, characterized in that: include: A pixel array, comprising a plurality of pixel units arranged in an array; A pixel readout module comprises a plurality of column processing units for respectively reading voltage signals from each column of pixel units; wherein each column processing unit comprises the readout circuit described in any one of claims 1-7.
9. A chip, characterized in that: The chip includes the image sensor as claimed in claim 8.
10. A control method, characterized in that: Applied to a readout circuit including a capacitive feedback transimpedance amplifier circuit, the control method comprises: Reducing a first voltage value of a reset signal in a capacitive feedback transimpedance amplifier circuit and / or increasing a second voltage value of the reset signal; The first voltage value represents a high-level voltage value in the reset signal, and the second voltage value represents a low-level voltage value in the reset signal.