Self-adaptive FFT (Fast Fourier Transform) processor module for large data volume processing

Abstract

The invention belongs to the technical field of FFT (Fast Fourier Transform) calculation acceleration, and particularly relates to a self-adaptive FFT operation processor module for processing large data volume, which comprises an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT calculation module and a control module, the FFT calculation module comprises m rows of radix-2kMDC modules which are arranged side by side; the data rearrangement unit comprises a read-write data storage module and a data preprocessing module; the read-write data storage module consists of a plurality of memories; the data preprocessing module is composed of a plurality of parallel branch switching circuits and a plurality of shuffling units with different depths; the twiddle factor storage module is used for storing fixed constant twiddle factors and realizing repeated utilization of the constant twiddle factors according to the calculated points; the address generation module is used for generating an address sequence for data reading / writing by using a program counter, the control module is used for controlling and executing FFT calculation, and different FFT calculation requirements can be met. And the utilization rate of the butterfly operation unit and the calculation throughput rate of the whole architecture are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of FFT calculation acceleration, and in particular relates to an adaptive FFT operation processor module for processing large amounts of data. Background Art

[0002] Fast Fourier Transform (FFT) is an efficient algorithm that can convert signals from the time domain to the frequency domain. It has extremely wide applications in the field of modern science and technology. In recent decades, the demand for processing large-scale data has continued to increase. For example, image processing needs to process data of up to 2M, while high-performance SAR real-time processing platforms must process data of up to 128K to generate high-resolution images. Therefore, an FFT operation processing module that can process large amounts of data is needed for application fields with large amounts of data computing requirements. The hardware implementation technology of FFT has been deeply studied and mainly developed into two categories. One is a pipeline architecture characterized by high throughput; the other is a storage architecture, which has advantages in hardware area and resource usage.

[0003] The traditional multi-path delay commutator (MDC) architecture is as follows: Figure 1 As shown in the figure, data is allowed to be input into the butterfly unit in parallel, which is suitable for scenarios with high throughput. However, this architecture has the problem that as the number of processed data points increases, the internal buffer will also expand accordingly and the computing resources will increase, which will use more hardware FIFO resources and ordinary multiplication units (ordinary multiplication units correspond to the symbol in the figure In a specific implementation, if the number of butterfly units (a butterfly unit consists of a subtraction and addition unit) is Then the number of points to be processed is in the range This means that when the actual number of points to be processed Unable to fully utilize all butterfly computing units, resulting in This reflects that the pipeline architecture designed for large points has low resource utilization when performing small-point FFT calculations.

[0004] However, the storage-based FFT structure is suitable for resource-constrained scenarios. The salient feature of this structure is that it consists of a group of memories and multiple processing elements (PEs). Its calculation method is to repeatedly transfer data from the storage element to the PE for processing, and write the processing results back to the storage element. Although this method reduces the occupied area of ​​the circuit, repeated data iteration will result in long calculation time and low throughput. At the same time, in order to ensure a stable data calculation flow when iteratively updating data in the memory, conflict-free data access technology should be used to solve the problem of data access contention. In addition, related studies have also introduced permutation circuits that can rearrange the data read from the memory and input it into the FFT processing unit. However, these circuits cannot be applied to high-speed, continuous stream and larger FFT scale applications. Summary of the invention

[0005] The present invention aims to provide an adaptive FFT operation processor module for processing large amounts of data, which can adapt to FFT calculation requirements with different numbers of points, different degrees of parallelism, and constant bases, and improve the utilization rate of the butterfly operation unit and the calculation throughput of the overall architecture.

[0006] The adaptive FFT operation processor module for processing large amounts of data in the present invention comprises an address generation module, a data rearrangement unit, a rotation factor storage module, an FFT calculation module and a control module;

[0007] The FFT calculation module includes m rows of radix-2 k MDC module;

[0008] The data rearrangement unit includes a read-write data storage module and a data preprocessing module;

[0009] The read-write data storage module consists of multiple memories, each row is based on 2 k The MDC module corresponds to a specific memory, which is used to store data for input into the MDC module according to the settings;

[0010] The data preprocessing module is composed of multiple parallel branch switching circuits and multiple shuffle units of different depths. A shuffle unit contains two multiplexers and two cache units of the same depth, which are used to receive the intermediate calculation data from the read-write data storage module and further adjust the arrangement position of the data to make it conform to the MDC module input data layout of the next FFT calculation stage;

[0011] The rotation factor storage module is used to store fixed constant rotation factors and reuse the constant rotation factors according to the number of calculated points;

[0012] The address generation module is used to generate an address sequence for data reading / writing using a program counter;

[0013] The control module is used to control the above modules / units to perform FFT calculations according to the following strategies:

[0014] In the pipeline architecture mode, according to the number of FFT points to be processed and the parallelism P<m, multiple groups of P-row MDC modules are cascaded through the data rearrangement unit by writing the input data or the calculation output of the P-row MDC module of the previous level into the memory corresponding to the P-row MDC module of the next level;

[0015] In the storage architecture mode, according to the number of FFT points to be processed, the parallelism P<m, the data calculated by the P-row MDC modules in this stage is processed by the data rearrangement unit, and then input back to the group of P-row MDC modules in the next stage for FFT calculation.

[0016] Furthermore, in the data rearrangement unit, the following strategy is adopted to adjust the arrangement position of the data:

[0017] Let N = 2 f is the number of points to be processed by FFT, P is the parallelism, and for any cardinality k, the index calculation formula for each sample in a sample sequence is where x i represents the i-th bit dimension, x i ∈{0,1}, the bit dimension change σ is defined as changing each bit dimension position of the original by applying the same transformation rule. The detailed mathematical formula is as follows:

[0018] σ(x f-1 x f-2 …x 0 )=x σ(f-1) x σ(f-2) …x σ(0) (1)

[0020] where x σ(f-1) Represents the bit value at the f-1 position after the transformation;

[0021] A row of MDC modules corresponds to a FFT algorithm calculation stage with a maximum cardinality of k. The N-point FFT is calculated in stages, where Indicates the rounding up operation, the actual cardinality of each stage is k s , s∈{0,1,…,S-1}, is defined as follows:

[0022] k 1 =fk(S-1),k 2 =…=k s =k (2)

[0024] In the sth stage, a row of MDC modules will calculate data blocks, each of which contains The input sample data to be processed are arranged as follows The matrix symbol It represents the u-th input block in the s-th stage, that is, u is the index number of the data block, as shown in the following formula:

[0025]

[0026] Element b r,c The subscripts r and c represent the row and column indices of the data to be processed, respectively. 0,0 = x(u), then we need The other elements and index u in the matrix must satisfy b r,c =x(u+d) constraint, so as to operate on the correct sample pairs in MDC, the expression of variable d is as follows:

[0027]

[0028] The value range of u in different stages s is as follows:

[0029]

[0030] And the increment symbol ε s Defined as:

[0031]

[0032] Where {a:i:b} represents a sequence starting from integer a and increasing to b with a step size of i;

[0033] symbol In the sth stage, the process of changes in the data rearrangement unit is defined as and It can be composed of three consecutive bit dimension changes, and its mathematical definition formula is as follows:

[0034]

[0035] in, Indicates the change of the last bit of the address when reading data from the memory. represents the parallel branch transformation in the data preprocessing module, Represents a series of shuffle unit transformations in the data preprocessing module.

[0036] Furthermore, in the strategy, the sequence is initially stored in 2P memories, and the sampled data is placed in natural order, that is, in the qth memory, the data is arranged in the order of index q(N / 2P), q(N / 2P)+1, …, (q+1)(N / 2P)-1;

[0037] First, the read and write transformation of the memory address The position of each indexed point can be expressed as:

[0038]

[0039] where p = log 2 2P, parallel sequence (a n-1 ,…,a n-p ) indicates the memory identification number, and the serial sequence determines the specific arrangement position of the data in the memory. The specific expression is:

[0040]

[0041] The function Cat([u:v],[c:d]) represents the concatenation of two bit sequences, one ranging from u to v and the other ranging from c to d, and the operation R{.} represents the bit reversal operation; It is a variable parameter, indicating the position to be reversed, including:

[0042]

[0043] Further, the control module is configured to control the memory to perform read / write operations using the following strategy:

[0044] If the memory is full of intermediate data, it needs to be loaded into the next row of MDC units. The read address pointer RD loads data from the memory according to the position pointed to by the value after the inversion of the specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data;

[0045] In the next round of data update process, the read / write operation of the same address position needs to be performed in a step-by-step manner according to the original address;

[0046] In each subsequent round of data reading / writing, the read / write operation at the same address position is performed alternately according to the bit-reversed address or the original address.

[0047] Furthermore, the parallel branch switching circuit is used to implement the second bit dimension transformation All bits of the parallel dimension are reversed; after the data is read out from the memory, the parallel branches of the circuit are changed to redirect the data flow to different shuffle unit ports. The corresponding transformation is described by the formula:

[0048]

[0049] Furthermore, dimension transformation This is accomplished by the shuffle unit, acting on both the parallel dimension and the serial dimension. Further, in the rotation factor storage module, according to the configured parameters k, N, a base of 2 is pre-stored. k The constant rotation factor, the trivial rotation -j, and the required non-trivial rotation factor of the partial base related to the number of calculation bits N are used for each basis -2 in the FFT calculation k The MDC module is called repeatedly as needed. Further, the specific configuration of the non-trivial rotation factor includes: N is the rotation factor, the superscript n is the time index, and η is the frequency index; first, perform k+1-dimensional linear mapping decomposition on n and η: Assume that N points are calculated and mixed basis is needed at the same time and base-2 k Algorithm, k 1 ≤k, then: In the first stage of computing the N-point FFT, the last multiplication unit requires a non-trivial twiddle factor with base N is pre-stored; in the second stage of calculating the N-point FFT, the last multiplication unit only needs to be multiplied with the base The rotation factor is stored in advance; when performing the third stage calculation, the rotation factors that need to be stored in advance are And so on, until the last stage, the rotation factors that need to be stored in advance are It belongs to a constant rotation factor. Further, the data rearrangement unit also includes a read / write address bit inversion module, which is used to invert the specified number of bits of the read / write address of the memory given by the address generation module according to the setting. Further, it also includes an output data buffer module, which is used to output the result generated by the FFT calculation module to an external cache unit. The advantage of the present invention is that an FFT operation processor module for adaptively processing large amounts of data is proposed, and its calculation parallelism, calculation points, and calculation cardinality are configurable, showing a high degree of flexibility and scalability. The present invention adopts a segmented rearranged MDC unit design, and in order to meet the calculation requirements of the fast Fourier transform (FFT), a data rearrangement unit is added between each isomorphic MDC unit. These data rearrangement units are suitable for any number of points and are responsible for gathering the scattered data points in the storage unit. After passing through the preprocessing unit, they are sent to each MDC unit in an orderly manner for processing according to the correct interval order of the FFT operation. It can significantly reduce the FIFO buffer depth inside the traditional MDC pipeline when processing a large number of data points. This not only improves the flexibility of the system architecture, but also ensures that all resources can be reused efficiently when performing small point calculations. At the same time, the data sorting task originally undertaken by the MDC internal buffer is now completed by the external data preprocessing module. The MDC architecture with segmented rearrangement can flexibly configure different computing modes, make full use of idle MDC units, and realize multi-channel parallelism under the pipeline architecture. The segmented rearrangement unit can also be used in the storage architecture to re-input the data processed by the MDC unit into the original memory. The above two points fully demonstrate the flexibility of this architecture.

[0050] In some embodiments of the present invention, a conflict-free access mechanism is proposed. The data rearrangement unit contains a complete set of address generation rules for memory read and write operations, so that the MDC unit in the previous row can write data to the storage unit while the MDC unit in the next row can read data from the storage unit, and the read and write operations can be completed simultaneously in the same memory area. Under the condition of satisfying the external minimum storage resource constraint, from the perspective of the same batch of data, the writing and reading order of a batch of data are opposite, and from the perspective of the same time point, the transformation mechanism of the read and write pointers is the same; it is ensured that the simultaneous conflict-free read and write address access mechanism is realized in the same register. Accordingly, a set of address bit change models are proposed, aiming to accurately calculate the number of changes in the address bits in accessing each row of storage units under different fast Fourier transform input point conditions, so that the in-situ transformation can be realized to reduce the consumption of storage units, and a set of shuffling units with different depths are designed to ensure the correct arrangement of data points, so that the data generated by each MDC unit can be reordered by the data rearrangement unit, and the data pairs are accepted by the next row of MDC units in the correct interval order.

[0051] In some embodiments of the present invention, an improved base-2 k The decomposition algorithm divides the twiddle factors into three categories: constant twiddle factors, non-trivial twiddle factors, and trivial twiddle factors. This allows the MDC unit to be compatible with radix-2 in the same set of hardware resources. k-1 , Base-2 k-2 , ..., base-2 2 The algorithm fully reduces the complexity of hardware resources and improves the utilization rate of the complex multiplication unit.

[0052] In some embodiments of the present invention, based on the configured parameters k, N, a base of 2 is pre-stored. k The constant rotation factors, trivial factors, and the required non-trivial rotation factors of the partial base and the number of calculation bits N are used for each basis-2 in the FFT calculation k The MDC module is called repeatedly as needed, so it is necessary to reduce the number of twiddle factors stored in ROM in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic diagram of a traditional MDC pipeline in the background technology of the present invention;

[0054] Figure 2 Schematic diagram of the overall architecture of the adaptive FFT processor module in an embodiment of the present invention;

[0055] Figure 3 Schematic diagram of the MDC pipeline architecture using segmented rearrangement in an embodiment of the present invention;

[0056] Figure 4 is the base-2 in the embodiment of the present invention k Schematic diagram of the MDC pipeline architecture;

[0057] Figure 5 Schematic diagram of the pipeline computing mode and the storage computing mode in the embodiment of the present invention;

[0058] Figure 6 A schematic diagram of a read / write scheme for non-conflicting read / write address conversion in an embodiment of the present invention;

[0059] Figure 7 The base-2 used in the embodiment of the present invention 5 Schematic diagram of the changes in the data flow of 4096 points during algorithm operation. DETAILED DESCRIPTION

[0060] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0061] The structure of the FFT operation processor module in this example is basically as follows Figure 2 As shown, it includes an address generation module, a data rearrangement unit, a rotation factor storage module, an FFT calculation module, an output data buffer module and a control module.

[0062] Under this pipeline architecture, the processor module adopts Figure 3 The segmented rearrangement pipeline architecture shown in the figure divides the traditional serial MDC structure into multiple MDC modules of the same structure in its core module, the FFT calculation module, and all MDC modules are interconnected through the data rearrangement unit. The data rearrangement unit provides data to each MDC module respectively, and is responsible for processing the data generated by the previous MDC module according to the pre-given rearrangement setting, ensuring that the intermediate results can be passed to the next MDC module given in the setting in the correct index order. In the above operation process, the data rearrangement unit plays the role of switching, and can expand the MDC module according to different points in the pipeline structure.

[0063] If working under the storage architecture, the data generated by MDC will be rewritten into the original memory, realizing the alternating transformation of data in the same memory area.

[0064] The MDC module in this example uses Figure 4 The high-radix MDC architecture shown in the figure uses a radix-2 k The algorithm is constructed using k (k ≥ 2)-dimensional linear indexes, so the number of ordinary complex multiplication units can be reduced, and 2 can be processed at the same time. k The FFT data of the point; the high-radix MDC architecture adds multiplication units with different attributes, namely constant multiplication units (corresponding to the symbol in the figure ), trivial multiplication unit (corresponding to the symbol in the figure) ), non-trivial multiplication unit (corresponding to the symbol in the figure ), wherein the trivial multiplication unit can realize the function of imaginary part multiplication through circuit transformation. Figure 4 The architecture diagram of the MDC module is shown. Figure 4 (a) Describe the case where the cardinality is an odd number, and the Figure 4 (b) presents a structure with an even cardinality.

[0065] Figure 5 The following example shows the possible rearrangement of the MDC module and the data rearrangement unit in the FFT calculation module. The FFT calculation module in the figure consists of m rows of radix-2 k The data rearrangement unit is composed of MDC modules, and each MDC module is directly or indirectly connected to the data rearrangement unit.

[0066] Figure 5 The rearrangement in (a) enables m rows of MDC modules to process consecutive 2 k Point sampling sequence, each row of MDC modules independently processes a group of 2 k point sequence.

[0067] Figure 5 The rearrangement method in (b) is to cascade multiple MDCs containing P MDCs in parallel in each level. The P MDCs in the same level exchange data with each other in the data rearrangement unit. P is called the degree of parallelism. This method increases the number of MDCs in each level. The resulting computing unit can read 2P data at the same time. For the same scale of FFT points, the throughput of the architecture is significantly improved at the cost of occupying P times the number of butterfly units. The cascade of only one MDC in each level is a special case of P = 1. For details on the data exchange within each level of MDC when P > 1, please refer to the literature [4]. The corresponding number of MDCs can be cascaded according to the specific number of FFT points to be processed. Similarly, multiple groups of MDCs can be cascaded independently to process multiple groups of FFT calculations in parallel.

[0068] Figure 5 (c) indicates that all m rows of MDC modules are cascaded into a group, and only one group with an upper limit of 2 can be processed at the same time mk The sampling sequence.

[0069] It is not difficult to find that Figure 5 (a) and Figure 5 The rearrangements in (c) can all be understood as Figure 5 A special case of the rearrangement in (b).

[0070] The above rearrangement methods can be collectively referred to as pipeline architecture mode, that is, the FFT calculation does not involve the repeated use of the same set of MDCs. Figure 5 (d) shows that when the number of input data points exceeds the processing capacity limit of m rows of MDC modules cascaded in sequence, the m-channel execution mode based on the storage architecture will be adopted. In this mode, the data will be repeatedly processed in each row of MDC modules.

[0071] In addition, the single-row MDC unit uses an improved base-2 k Decomposition algorithm, which is also backward compatible with radix-2 k-1 , Base-2 k-2 , ..., base-2 2 To perform calculation, it is only necessary to bypass the redundant butterfly units through the selector.

[0072] It can be seen that the adaptive architecture proposed in this example can be parameterized for any number of points N, parallelism P, and cardinality k by changing the number of butterfly operation units actually enabled in the MDC module (k value) and the cascade mode and number of MDC modules.

[0073] In order to ensure that the intermediate results can be passed to the next row of MDC modules given in the setting in the correct index order, the data rearrangement unit includes a read-write data storage module, a data preprocessing module, and a read-write address bit inversion module;

[0074] The read-write data storage module is composed of multiple memories. In this example, each MDC module corresponds to two memories. In the pipeline architecture, the data results calculated by the previous row of MDC modules will be stored in the memory corresponding to the next row of MDC modules according to the rearrangement settings. In the memory architecture, the data calculated by the MDC modules in this row are processed by the data rearrangement unit and rewritten into the MDC modules in this row.

[0075] The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffle units of different depths. A shuffle unit contains two multiplexers and two cache units of the same depth. The function of the data preprocessing module is to accept the intermediate calculation data from the read-write data storage module and further adjust the arrangement position of the data to make it conform to the input data layout of the next-level MDC module.

[0076] In order to illustrate the specific read and write address transformation and shuffle change rules, this example introduces a bit dimension transformation representation method for detailed explanation.

[0077] A sample sequence contains N (N = 2 f ) sampling points, the index calculation formula for each sample is where x i represents the i-th bit dimension, x i ∈{0,1}, can be simplified to The symbol ≡ represents the expression of index binary, and the bit dimension change σ is defined as changing the original bit dimension position by applying the same transformation rule. The detailed mathematical formula is as follows:

[0078] σ(x f-1 x f-2 …x 0 )=x σ(f-1) x σ(f-2) …x σ(0) (3)

[0080] where x σ(f-1) Represents the bit value at the f-1 position after the transformation.

[0081] According to the architecture in this example, a row of MDC modules corresponds to a FFT algorithm calculation stage with a maximum cardinality of k. Calculate N-point FFT (N = 2 f ),in Indicates the rounding up operation, the actual cardinality of each stage is k s , s∈{0,1,…,S-1} is defined as follows:

[0082] k 1 =fk(S-1),k 2 =…=d S =k (4)

[0084] In the sth stage, a row of MDC modules will calculate data blocks, each of which contains The input sample data to be processed are arranged as follows The matrix symbol represents the u-th input block in the s-th stage, that is, u is the index number of the data block, as shown in formula (3):

[0085]

[0086] Element b r,c The subscripts r and c represent the row and column indices of the data to be processed, respectively. 0,0 = x(u), then we need The other elements and index u in the matrix must satisfy b r,c =x(u+b) so that the correct sample pairs can be operated in MDC. The expression of variable d is as follows:

[0087]

[0088] In each calculation stage s, there are a total of The butterfly blocks arrive in consecutive time periods and are fed into the MDC unit in sequence. These blocks are connected by the leading element d in the upper right corner. 0,0 = x(u) to distinguish, once the index u is determined, the indexes of other elements in the block can be derived by formula (4). In addition, considering the additional condition k 0 =0, the value range of u in different stages s is as follows:

[0089]

[0090] And the increment symbol ε s Defined as:

[0091]

[0092] Where {a:i:d} represents a sequence starting from integer a and increasing to b with a step size of i.

[0093] On the other hand, the symbol Indicates the output block after the MDC unit calculation in the sth stage. In order to follow the calculation rules of the FFT algorithm and ensure the correctness of the final calculation result, the calculation result of the previous stage should be satisfied. After passing through the external data rearrangement unit, it becomes the input data of the next stage MDC unit The process of changes in the data rearrangement unit is defined as and It can be composed of three consecutive bit dimension changes, and its mathematical definition formula is as follows:

[0094]

[0095] Indicates the change of the last bit of the address when reading data from the memory. represents the parallel branch transformation in the data preprocessing module, Represents a series of shuffle unit transformations in the data preprocessing module.

[0096] The sequence is initially stored in 2P memories, where P represents the degree of parallelism. Initially, the sampled data is placed in natural order, that is, in the qth memory, the data is arranged in the order of index q(N / 2P), q(N / 2P)+1,…,(q+1)(N / 2P)-1.

[0097] First, the read and write transformation of the memory address The data rearrangement unit in this example also includes a read / write address bit inversion module, which is used to invert the last number of designated bits of the address for reading / writing the memory given by the address generation module according to settings.

[0098] The position of each index point can be expressed as:

[0099]

[0100] where p = log 2 2P, parallel sequence (a n-1 ,…,a n-p ) represents the memory identification number, and the serial sequence determines the specific arrangement position of the data in the memory. It is not difficult to find that when P = 1, only 2 memories are needed, with 1 bit for identification, and the read-write conversion The specific expression is:

[0101]

[0102] The function Cat([u:v],[c:d]) represents the concatenation of two bit sequences, one ranging from u to v and the other ranging from c to d. The operation R{.} represents the bit reversal operation and the permutation operation It is defined as reversing the latter part of the serial address sequence when the condition np-1≥w is met; otherwise, the entire serial address sequence will be reversed.

[0103] It is a variable parameter, indicating the position that needs to be reversed, and its value is determined by the number of points, the number of stages, and the cardinality. A complete mathematical modeling analysis of the FFT calculation data process is performed, and the calculation formula that can be applied to any number of points N, any stage s, any parallelism P, and any cardinality k is as follows:

[0104]

[0105] Therefore, the read / write address bit inversion module in this example is used to perform the required bit inversion operation on the serial sequence according to formulas (9) and (10). Then, in order to more efficiently complete the adjustment of each data arrangement position, a conflict-free read / write address access scheme is proposed in the read / write data storage module in this example. Figure 6 This scheme is demonstrated in the example of a 3-bit address, as follows:

[0106] Assuming that the memory is fully loaded with intermediate data at this time, it needs to be loaded into the next row of MDC units. First, the address generation module sends an increasing address sequence (the exemplary address 0b000-0b111 in the figure) to the read-write address bit inversion module. Figure 6 As shown in (a), the read address pointer RD loads data from the memory (Bank) according to the location pointed to by the value after the 3 bits at the end of each address are inverted; at the same time, new data needs to be stored, and the write address pointer WT also stores the new data in a 3-bit inverted manner, that is, the order of new data write / old data read address is 0b000→0b100→0b010→0b110...; continue according to Figure 6 The reverse read and reverse write processes shown in (a) are executed until the original data in the memory is completely replaced by the new data, and the new data is stored in the bank by reversing the address bits.

[0107] In the next round of data update process, you need to follow Figure 6 (b) shows the original address for read and write operations in a step-by-step increment manner, that is, the order of new data writing / old data reading is 0b000→0b001→0b010→0b011…; in each subsequent round of data reading / writing, Figure 6 (a) with Figure 6 The operations of (b) are performed alternately, that is, for the same batch of data, the writing and reading orders are opposite, thereby effectively realizing the aggregation of the same group of data. In order to realize the above process, a read-write address bit inversion module is provided in the data rearrangement unit to generate the inverted memory access and memory write addresses.

[0108] The data preprocessing module includes a variety of parallel branch switching circuits configured in different modes and a series of shuffle units connected with different cache depths. Each shuffle unit includes two multiplexers and two cache units with the same depth.

[0109] The parallel branch switching circuit is used to realize the second bit dimension transformation Specifically, the parallel dimension in formula (8) is acted on, and all bits of the parallel dimension are reversed; after the data is read out from the memory, the parallel branch of the circuit is changed to redirect the data flow to different shuffle unit ports. The corresponding transformation can be described by the following formula:

[0110]

[0111] Next, the third dimension is transformed It acts on both the parallel dimension and the serial dimension in formula (8) and is the final permutation step before entering the MDC calculation. It is mainly used to change the block The internal index data order is introduced to determine the permutation between the parallel branches of the i-th row and the i+h-th row, where h∈[0,P]. Another parameter l represents the length of the delay FIFO. The third bit dimension transformation is achieved by exchanging the l′=log 2 l bit and the h′th bit of the parallel sequence = log 2 h bit is implemented, and the specific parameters are as follows:

[0112]

[0113] The hardware required to implement this permutation includes two FIFOs of length l and two multiplexers, connected to the parallel branches of row i and row i+h, respectively. The transformation is not enough The output data is transformed into input data that meets the requirements Therefore, in the first After the transformation, a series of shuffle circuits need to be added. This example constructs a mathematical model to determine the number of shuffle units in the combination and the specific values ​​of i and h in each permutation. Finally, it is concluded that the number of transformations in the third bit dimension can range from 0 to 6 times, expressed as

[0114] To explain the third dimension transformation in detail, Table 1 lists N=2 f When the point FFT is executed in the first stage (s=1) with parallelism P=1 and cardinality k=5, a series of shuffle circuit parameter configurations are required. In the table, the symbol "\" indicates that the corresponding shuffle circuit does not need to be executed, and the symbol % indicates taking the remainder.

[0115] Table-1

[0116]

[0117] In summary, Used to generate addresses according to formula (9) to read data from the memory, then, Used to exchange parallel branches. Then, a series of The combination of is used to adjust the index order to meet the input calculation requirements of the MDC. Finally, the output data is transferred to the adjacent memory in the parallel architecture or the original memory in the memory architecture to be used as the input of the corresponding MDC.

[0118] Figure 7 This example shows a 4096-point data sequence x using base 2. 5 When the MDC unit is configured, each detailed processing step in the data storage module and the data preprocessing module is performed. Initially, 4096 data points are stored in the data storage module according to the layout in block 7.1. By reading the data storage module and shuffling the data preprocessing module, the data input to the MDC unit each time can conform to the FFT basis-2. 5 The data calculation layout.

[0119] 4096 points of data are executed in a pipeline architecture with a parallelism of 1. 5 When using the FFT algorithm, a total of 3 rows of MDC modules are required, so s∈{1,2,3}. According to formula (3), when s=1,u=0, b 0,0 =x(0) is used as the first element of the data block. According to formulas (3) and (4), the index values ​​of the remaining elements can be inferred:

[0120] a 0,1 =x(u+d)=x(u+1024×(0×2+1))=x(1024)

[0121] a 1,0 =x(u+d)=x(u+1024×(1×2+0))=x(2048)

[0122] a 1,1 =x(u+d)=x(u+1024×(1×2+1))=x(3072)

[0123] At this time, the first row MDC receives a time domain sample block headed by index m=0, arranged as follows:

[0124]

[0125] Corresponding attachment Figure 7 The data marked by the dotted box in Figure 7.2.

[0126] When s = 2, b 0,0 =x(0) is used as the first calibration element of the data block. According to formulas (3) and (4), we have:

[0127] b 0,1 =x(u+d)=x(u+32×(0×16+1))=x(32)

[0128] b 0,2 =x(u+d)=x(u+32×(0×16+2))=x(64)

[0129] b 0,3 =x(u+d)=x(u+32×(0×16+3))=x(96) ...

[0131] b 0,15 =x(u+d)=x(u+32×(0×16+15))=x(480)

[0132] b 1,1 =x(u+d)=x(u+32×(1×16+1))=x(544)

[0133] b 1,2 =x(u+d)=x(u+32×(1×16+2))=x(576)

[0134] b 1,3 =x(u+d)=x(u+32×(1×16+3))=x(608) ...

[0136] b 1,15 =x(u+d)=x(s+32×(1×16+15))=x(992)

[0137] At this time, the first input matrix of the second row of MDC is:

[0138]

[0139] Corresponding attachment Figure 7 The data marked by the dotted box in Figure 7.5.

[0140] By analogy, we can get that when i=3, the first input matrix of the third row MDC is:

[0141] Corresponding attachment Figure 7 The data marked by the dotted box in Figure 7.9.

[0142] It is not difficult to find that Figure 7 The 4096-point input data stored in the input buffer of the data storage module represented by blocks 7.1, 7.3 and 7.6 do not meet the input requirements of the next-level MDC, so the aforementioned address inversion reading scheme is used with the external shuffle unit to adjust the order of the input data. Substituting into formulas (2) and (10), it can be seen that when the 4096-point calculation is completed, k 1 =2, k 2 =5, k 3 =5. At this time Substituting into formula (9), we can see that before the serial sequence sends data from the input buffer to the first row of MDC units in the first stage of calculation, The last 11 bits of the address need to be inverted. Figure 7 The four data marked by the dashed boxes in block 7.2 include the 0th, 1024th, 2048th and 3072th data points in the input sequence. Before the second stage of the calculation, the serial sequence sends the data from the input buffer to the second row of MDC units, The last 6 bits of the address need to be reversed, corresponding to the attached Figure 7 In block 7.4 of the middle figure; however, after reading the data in the manner of reversing the latter part of the address, it still does not meet the requirements. Therefore, in this example, an additional external shuffle unit is used to adjust the local order between data. Figure 7 As shown in block 7.5 in the figure, the data points are rearranged after passing through a delayed commutation shuffle unit with a cache depth of 16. In summary, the data rearrangement unit uses the address back-end bit inversion to read the memory and the function of the multi-stage shuffle unit, so that the disordered data pairs can be sent to the MDC unit at specific intervals. It is worth noting that in the above example, since the parallelism P = 1, the parallel branch exchange circuit does not actually play a role.

[0143] It can be seen that by performing the aforementioned address bit inversion data reading / writing and row transformation, it is possible to ensure that the sampled data points that meet the calculation requirements of a single butterfly unit are effectively concentrated in the same area, and then the final input order is adjusted within the area through the shuffle unit, so that the shuffle depth can be reduced as much as possible, thereby reducing the length of the FIFO and reducing the hardware resource requirements.

[0144] The twiddle factors required in the FFT calculation can be stored in the ROM of the twiddle factor storage module in advance, and then read into the specific multiplication component for use when needed. However, in some PFGA-based embodiments, in the calculation mode of the pipeline architecture, due to the limited Bram and Uram resources in the FPGA, when the base k is greater than 4, it is assumed that the number of points N calculated is greater than 2. 3k When the ROM is used, it is impossible to allocate multiple storage spaces for storing N data and each data occupies 64 bits. Therefore, it is necessary to reduce the number of rotation factors stored in the ROM in advance.

[0145] On the other hand, the known radical-2 k The algorithm can be derived from a discrete Fourier transform (DFT) of length N using the following equation,

[0146]

[0147] Where W N is the rotation factor, the superscript n is the time index, and η is the frequency index.

[0148] Specifically, taking k=5 as an example, firstly, n and η are decomposed by k+1=6-dimensional linear mapping:

[0149]

[0150] Substituting the variables of formula (17) into formula (16) yields:

[0151]

[0152] The decomposition expression of the rotation factor is:

[0153]

[0154] Further expansion of formula (19) yields:

[0155]

[0156] The rotation factor merging method described in formula (20) is adopted, and the rotation factors are divided into three categories, namely constant rotation factors, non-trivial rotation factors and trivial rotation factors, where is a constant twiddle factor that can be pre-stored in ROM, W N is a non-trivial rotation factor related to N, and -j represents a trivial rotation factor. The rotation factor storage module in this example only saves the required part of the non-trivial rotation factor W related to N in advance N , and transmit the data to the complex multiplier after the last butterfly unit in the MDC, and perform complex multiplication operations on the non-trivial rotation factors and the intermediate calculation results of the butterfly unit, as follows:

[0157] Base-2 k The configuration mode of the multiplication components of each butterfly unit in the MDC module is closely related to the parity of the base, such as Figure 4 As shown in (a), when the cardinality is odd, the first butterfly unit uses a constant twiddle factor multiplication unit, and the second butterfly unit that follows it uses a trivial twiddle factor multiplication unit. The third butterfly unit again uses a constant twiddle factor multiplication unit, which is consistent with the first unit. This alternating configuration pattern continues in sequence until the last butterfly unit. It is worth noting that the last butterfly unit uses a non-trivial twiddle factor multiplication unit. Relatively speaking, Figure 4 As shown in (b), when the radix is ​​even, the configuration sequence presents a different starting pattern. The first butterfly unit uses a trivial twiddle factor multiplication component, followed by a constant twiddle factor multiplication component in the second butterfly unit. The third butterfly unit again uses a trivial twiddle factor multiplication component. This alternating configuration of two twiddle factors with different properties continues until the last butterfly unit. Regardless of whether the radix is ​​odd or even, the last butterfly unit uses a non-trivial twiddle factor multiplication component, which also makes the radix-2 based twiddle factor multiplication component k The twiddle factor multiplication component in the MDC module of the algorithm can be performed in a "reduced basis" k 1 <k, algorithm (bypass the previous kk through the multiplexer 1 Butterfly units) are used directly, such as radix-2 5 MDC unit executable base-2 4 , Base-2 3 , Base-2 2 algorithm.

[0158] Assume that N points are calculated and mixed basis is needed at the same time and base-2 k Algorithm, k 1 ≤k, then in the first stage of calculating the N-point FFT, the base is the time index n and the frequency index η is decomposed into k 1 +1 linear dimension, the last multiplication unit needs to multiply by a non-trivial rotation factor with base N Then in the second stage of the calculation, the N-point FFT can be decomposed into multiple smaller Point FFT, and then decompose the base k into k+1 linear dimensions, so the last multiplication unit of the second stage only needs to be multiplied with the base Multiply the rotation factors, that is: By analogy, it can be inferred that the rotation factors that need to be stored in advance during the third stage calculation are Since, until the last stage (the mth stage), the rotation factors that need to be stored in advance are belongs to the constant rotation factor; therefore, the ROM occupied by storing only the constant rotation factor and the non-trivial rotation factor is much smaller.

[0159] For example, the above rotation factor multiplexing method is described in detail by taking the basis k=5 and calculating N=512K point data as an example. It can be seen that the mixed basis-2 is required to perform a complete 512K calculation. 4 and base-2 5 The algorithm (k 1 =4, k 2 =k 3 =k 4 =5), therefore, the last multiplication unit in stage 1 needs to be multiplied by a non-trivial rotation factor with a base of 512K After adopting the decomposition method of formula (20), the 512K point FFT can be simplified to a smaller 512K / 16=32K point FFT. Therefore, in the second stage of the 512K calculation, the last multiplication unit only needs to multiply with the non-trivial rotation factor with a base of 32K, that is: By analogy, it can be inferred that the rotation factor in the third stage is The rotation factors in the fourth stage are It is a constant twiddle factor.

[0160] Compared with the previous allocation scheme, the storage of rotation factors in the second stage is reduced by 4 times, and in the third stage by 9 times. By observing the data flow of the last butterfly unit in the second and third stages, and comparing it with the 32K point FFT data flow and the 1024 point FFT data flow, it can be found that the rotation factors are reused in blocks as the smallest unit, and each block contains 2 k For any number of points N and any base k, the read address generation algorithm of the multiplexed rotation factor memory is as follows:

[0161]

[0162] The main function of the control module in this example is to generate control signals, selectively activate the MDC unit inside the FFT calculation module, activate the data rearrangement unit, and generate the correct memory read and write addresses, ensuring that the data can be correctly loaded and processed during the entire program operation and the results can be calculated correctly.

[0163] The function of the address generation module is to generate addresses for the data rearrangement unit, the rotation factor storage module and the output data buffer module respectively using the program counter.

[0164] The output buffer module is responsible for outputting the results generated by the FFT calculation module to the external cache unit.

[0165] The aforementioned base-2 5 The FFT adaptive architecture with m=4 is compared with other storage architectures and pipeline architectures. Compared with references [1], [2], and [3], the architecture proposed in this example can perform FFT operations at a higher radix, and can support up to radix-2. 5 , which is suitable for processing large-scale data. The obvious advantage of this architecture is that it can support FFT calculations of up to 1M points, while the maximum point processing limit of other research works is significantly less than 1M.

[0166] Table 2 shows the proposed cardinality-2 5 , the difference between the FFT adaptive architecture with m=4 and P=4 and other storage architectures in hardware overhead and computing performance when using storage structure. Compared with previous studies, the number of iterations is reduced by 40% and the parallelism of the FFT processor is increased. FFT calculations can be performed in 8 parallel input branches at the same time, which improves the throughput of the architecture. When processing the same number of points, the storage architecture proposed in this example is superior to existing work because of the use of higher cardinality and parallelism, and ultimately, the execution time is reduced by 70% or more.

[0167] Table-2

[0168]

[0169] Table 3 lists the differences in average hardware resource utilization between the pipeline structure of this architecture and other pipeline architectures. In order to ensure the fairness of the experimental results, it is assumed that the computing resources are allocated equally when completing 512K point operations. 5 In the pipeline architecture, twenty butterfly units are used, one of which is idle. This computing resource configuration is the same as the literature. It can be seen from the table that most of the hardware resources are idle when performing small-scale FFT operations. In contrast, the pipeline architecture proposed in this work increases parallelism and activates idle hardware resources, ultimately increasing the utilization rate by 2 or 4 times within the same point processing range, achieving high-performance hardware design.

[0170] Table-3

[0171]

[0172] References:

[0173] [1]A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling, Pei-YunTsai, Chung-Yi Lin, et al. "IEEE Trans.Very Large Scale Integr.Syst.", Volume 19, Issue 12, Pages 2290-2302, 2011.

[0174] [2] Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage, Z. Kaya et al., IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 70, No. 8, pp. 3084-3088, August 2023.

[0175] [3]Scheduling of data access for the radix-2k FFT processor using single-port memory, J. Wang et al., IEEE Trans. Very Large Scale Integration (VLSI) Syst., Vol. 28, No. 7, pp. 1676-1689, July 2020.

Claims

1. An adaptive FFT operation processor module for processing large amounts of data, characterized in that: It includes an address generation module, a data rearrangement unit, a rotation factor storage module, an FFT calculation module and a control module; The FFT calculation module includes m rows of radix-2 k MDC module; The data rearrangement unit includes a read-write data storage module and a data preprocessing module; The read-write data storage module consists of multiple memories, each row is based on 2 k The MDC module corresponds to a specific memory, which is used to store data for input into the MDC module according to the settings; The data preprocessing module is composed of multiple parallel branch switching circuits and multiple shuffle units of different depths. A shuffle unit contains two multiplexers and two cache units of the same depth, which are used to receive the intermediate calculation data from the read-write data storage module and further adjust the arrangement position of the data to make it conform to the MDC module input data layout of the next FFT calculation stage; The rotation factor storage module is used to store fixed constant rotation factors and reuse the constant rotation factors according to the number of calculated points; The address generation module is used to generate an address sequence for data reading / writing using a program counter; The control module is used to control the above modules / units to perform FFT calculations according to the following strategies: In the pipeline architecture mode, according to the number of FFT points to be processed and the parallelism P<m, multiple groups of P-row MDC modules are cascaded through the data rearrangement unit by writing the input data or the calculation output of the P-row MDC module of the previous level into the memory corresponding to the P-row MDC module of the next level; In the storage architecture mode, according to the number of FFT points to be processed, the parallelism P<m, the data calculated by the P-row MDC modules in this stage is processed by the data rearrangement unit, and then input back to the group of P-row MDC modules in the next stage for FFT calculation.

2. The FFT operation processor module according to claim 1, characterized in that: In the data rearrangement unit, the following strategy is used to adjust the arrangement position of the data: Let N = 2 f is the number of points to be processed by FFT, P is the parallelism, and for any cardinality k, the index calculation formula for each sample in a sample sequence is where x i represents the i-th bit dimension, x i ∈{0, 1}, the bit dimension change σ is defined as changing each bit dimension position of the original by applying the same transformation rule. The detailed mathematical formula is as follows: σ(x f-1 x f-2 …x0)=x σ(f-1) x σ(f-2) …x σ(0) (1) where x σ(f-1) Represents the bit value at the f-1 position after the transformation; A row of MDC modules corresponds to a FFT algorithm calculation stage with a maximum cardinality of k. The N-point FFT is calculated in stages, where Indicates the rounding up operation, the actual cardinality of each stage is k s , s∈{0, 1, …, S-1}, is defined as follows: k1=f-k(S-1),k2=…=k S =k (2) In the sth stage, a row of MDC modules will calculate data blocks, each of which contains The input sample data to be processed are arranged as follows The matrix symbol It represents the u-th input block in the s-th stage, that is, u is the index number of the data block, as shown in the following formula: Element b r，c The subscripts r and c represent the row and column indices of the data to be processed, respectively. 0，0 = x(u), then we need The other elements and index u in the matrix must satisfy b r，c =x(u+d) so that the correct sample pairs can be operated in MDC. The expression of variable d is as follows: The value range of u in different stages s is as follows: And the increment symbol ε s Defined as: Where {a:i:b} represents a sequence starting from integer a and increasing to b with a step size of i; symbol In the sth stage, the process of changes in the data rearrangement unit is defined as and It can be composed of three consecutive bit dimension changes, and its mathematical definition formula is as follows: in, Indicates the change of the last bit of the address when reading data from the memory. represents the parallel branch transformation in the data preprocessing module, Represents a series of shuffle unit transformations in the data preprocessing module.

3. The FFT operation processor module according to claim 2, characterized in that: In the strategy, the sequence is initially stored in 2P memories, and the sampled data is placed in natural order, that is, in the qth memory, the data is arranged in the order of index q(N / 2P), q(N / 2P)+1, ..., (q+1)(N / 2P)-1; First, the read and write transformation of the memory address The position of each index point can be expressed as: Where p = log22P, parallel sequence (a n-1 , …, a n-p ) indicates the memory identification number, and the serial sequence determines the specific arrangement position of the data in the memory. The specific expression is: The function Cat([u:v], [c:d]) represents the concatenation of two bit sequences, one ranging from u to v and the other ranging from c to d, and the operation R{.} represents the bit reversal operation; It is a variable parameter, indicating the position to be reversed, including:

4. The FFT operation processor module according to claim 3, characterized in that: The control module is configured to control the memory to perform read / write operations using the following strategy: If the memory is full of intermediate data, it needs to be loaded into the next row of MDC units. The read address pointer RD loads data from the memory according to the position pointed to by the value after the inversion of the specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data; In the next round of data update process, the read / write operation of the same address position needs to be performed in a step-by-step manner according to the original address; In each subsequent round of data reading / writing, the read / write operation at the same address position is performed alternately according to the bit-reversed address or the original address.

5. The FFT operation processor module according to claim 4, characterized in that: Parallel branch switching circuit is used to realize the second bit dimension transformation All bits of the parallel dimension are reversed; after the data is read out from the memory, the parallel branches of the circuit are changed to redirect the data flow to different shuffle unit ports. The corresponding transformation is described by the formula:

6. The FFT operation processor module according to claim 5, characterized in that: Dimension Transformation This is accomplished by the shuffle unit, acting on both the parallel and serial dimensions.

7. The FFT operation processor module according to claim 1, characterized in that: In the rotation factor storage module, according to the configured parameters k, N, a base of -2 is pre-stored. k The constant rotation factor, the trivial rotation -j, and the required non-trivial rotation factor of the partial base related to the number of calculation bits N are used to provide each basis -2 in the FFT calculation k The MDC module is called repeatedly as needed.

8. The FFT operation processor module according to claim 1, characterized in that: The specific configuration of the non-trivial rotation factor includes: N is the rotation factor, the superscript n is the time index, and η is the frequency index; First, perform k+1-dimensional linear mapping decomposition on n and η: Assume that to calculate N points, we need to use mixed basis at the same time - And the base-2k algorithm, k1≤k, then: In the first stage of computing an N-point FFT, the last multiplication unit requires a non-trivial twiddle factor of base N. is pre-stored; In the second stage of computing the N-point FFT, the last multiplication unit only needs to be multiplied by the base The rotation factor is pre-stored; When performing the third stage calculation, the rotation factors that need to be stored in advance are And so on, until the last stage, the rotation factors that need to be stored in advance are It is a constant twiddle factor.

9. The FFT operation processor module according to claim 4, characterized in that: The data rearrangement unit also includes a read / write address bit inversion module, which is used to invert the designated number of bits in the rear section of the read / write address for the memory provided by the address generation module according to the setting.

10. The FFT operation processor module according to claim 1, characterized in that: It also includes an output data buffer module, which is used to output the result generated by the FFT calculation module to an external cache unit.

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