Layout graph OPC detection and early warning method for process capability exceeding problem

Abstract

According to the OPC detection and early warning method for the layout graph exceeding the process capability problem, when DRC check is completed and an error is reported, the following detection is carried out: a graph at an error reporting position of design rule check is marked and is used as a graph with a large risk class; and performing regular classification on the risk large-class graphs according to the graph features to divide the risk large-class graphs into first-class graphs and second-class graphs. The first-class graphs are high-risk graphs exceeding the process capability, and when the first-class graphs exist, the first-class graphs are fed back to the layout design end. The second type of graphs are potential risk graphs, when the second type of graphs exist, second screening is carried out on the second type of graphs, and the second screening comprises the step of carrying out local OPC correction to obtain the first layout layer. And adopting an OPC AEI model to carry out local OPC to judge whether a defect risk graph exists or not, and feeding back the defect risk graph to a layout design end when the defect risk graph exists. According to the method and the device, the defect problem caused by the problem layout graph exceeding the process capability can be quickly and comprehensively screened, so that the publishing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to an optical proximity correction (OPC) detection and early warning method for a layout pattern with problems exceeding process capability. Background Art

[0002] In the development of chip manufacturing technology, it is usually necessary to design a large number of layout test structures, and to perform some experimental designs that violate the design rules on the layout's graphic period, graphic size, and the alignment relationship between the upper and lower layers. By specially designing a large number of layout test structures, the corresponding process condition offsets and extreme conditions can be simulated to achieve monitoring and analysis of the process window, help discover process weaknesses, and find the optimal process window conditions.

[0003] Since the impact of OPC correction is not considered during layout design, and the capability limit of the lithography process and subsequent process risks cannot be accurately known, many risky layout graphics that exceed the process capability are usually designed, which can easily cause actual process defects and must be eliminated. However, after a complete OPC operation, only some problems may be found, and there is a risk of missing defects. Even if all problems are found, the layout must be modified and reworked, which not only wastes OPC operation resources, but also delays the entire mask publishing plan due to the time spent in the layout modification process, greatly reducing the timeliness of technology development.

[0004] like Figure 1 As shown, it is a publication flow chart for processing existing layout design problems, including the following steps:

[0005] Step S101, experimental layout design, the layout design will obtain the corresponding layout.

[0006] In some experimental designs, graphics that violate design rules are introduced into the layout.

[0007] Step S102: Design rule check (DRC), namely, DRC check.

[0008] An error will be reported when there are graphics in the layout that violate the design rules.

[0009] In the existing method, no matter whether the DRC check reports an error or not, the subsequent step S103 will be performed.

[0010] Step S103, OPC correction operation. In the OPC correction operation, the contour figure obtained by simulating the OPC model will be compared with the target figure, so as to achieve correction by continuous iteration. The OPC model simulates the photochemical reaction of the photoresist and is the OPC ADI model.

[0011] Step S104: Traditional OPC inspection: Similar to the existing method, the traditional OPC inspection is to conduct a comprehensive inspection on the graphics of the layout, and the OPC model used is the OPC ADI model.

[0012] If the OPC check finds a defect risk, the process returns to step S101 to modify the layout.

[0013] If no defect risk is found during the OPC check, the subsequent step S106 is performed.

[0014] Step S105: publishing, i.e. publishing to form the final layout.

[0015] However, in the existing methods, even if the OPC check does not find the risk of defects, there is still a risk of missed detections. First, the number of OPC checks is large, and there may be missed detections; second, the OPC check itself may not be able to find defects. For example, the OPC check model cannot find defective graphics. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide an OPC detection and early warning method for problem layout graphics that exceed process capabilities, which can quickly and comprehensively screen the defects caused by problem layout graphics that exceed process capabilities, thereby improving publishing efficiency.

[0017] In order to solve the above technical problems, the present invention provides an OPC detection and early warning method for problem layout graphics exceeding process capabilities. When the design rule check of the design layout is completed and an error is reported, the following steps are used to detect the problem layout graphics exceeding process capabilities:

[0018] The graphics of the error positions of the design rule check are marked and used as risk category graphics.

[0019] According to the graphic features, the risk category graphics are classified into the first category graphics and the second category graphics.

[0020] The first type of graphics are high-risk graphics that exceed the process capability. When the first type of graphics exist, the first type of graphics are fed back to the layout design end.

[0021] The second type of graphics is a potential risk graphics. When the second type of graphics exists, the second type of graphics is screened for the second time to find defect risk graphics. The second screening includes:

[0022] A local OPC correction is performed to obtain a first layer, and an object of the local OPC correction is a local area including the second type of graphics.

[0023] A local OPC check is performed, wherein the local OPC check determines whether the first layout layer has the defect risk pattern by performing AEI simulation prediction on the first layout layer using an OPC AEI model, and when the defect risk pattern is present, the defect risk pattern is fed back to the layout design end.

[0024] A further improvement is that the graphic feature values ​​of the rule classification include: the circumference, size, interval, and upper and lower layer relationships of the graphic.

[0025] A further improvement is that the rule classification includes: classifying the high-risk graphics whose graphic characteristic values ​​exceed the design rules by more than 10% to 20% as the first-category graphics.

[0026] A further improvement is that the rule classification further includes: classifying the risky graphics whose graphic characteristic values ​​exceed the design rules by 10% to 20% as the second-category graphics.

[0027] A further improvement is that the local OPC correction includes the following sub-steps:

[0028] Selecting an area of ​​10 micrometers to 50 micrometers centered on the error reporting position of the second type of graphics as the local area and forming a local marking layer corresponding to the local area;

[0029] The first layer is obtained by performing OPC correction on the graphics in the local mark layer.

[0030] A further improvement is that the modeling data of the OPC AEI model is data of the pattern after the etching process;

[0031] The OPC AEI model is a special OPC AEI model; the special OPC AEI model is established using a limit graph, the limit graph is a graph that violates the design rules, and the data corresponding to the post-etching graph with defect problems in the modeling data of the special OPC AEI model is marked as a limit small CD size that violates the design rules;

[0032] A first threshold is set according to the limit small CD size, and the first threshold is greater than or equal to the limit small size.

[0033] A further improvement is that the minimum CD size is a limit size at which photoresist stripping occurs or the groove cannot be opened after photolithography.

[0034] A further improvement is that the AEI simulation prediction includes:

[0035] Using the special OPC AEI model to simulate the first layer and obtain simulation values ​​of each graphic in the first layer;

[0036] The graphic of the first layer corresponding to the simulation value smaller than the first threshold is marked as the defect risk graphic.

[0037] A further improvement is that when the first type of graphics is not detected and the defect risk graphics are not detected in the second type of graphics, the following steps are also included:

[0038] Perform comprehensive OPC correction on the design layout;

[0039] Perform a comprehensive OPC inspection.

[0040] A further improvement is that after the comprehensive OPC inspection is passed, it also includes:

[0041] Publish to form the final version.

[0042] After the design rule check is completed, the present invention does not need to perform a comprehensive OPC correction on the entire layout. Instead, the graphics at the error position are first marked as risky graphics, and then the risky graphics are classified according to rules. The first category of graphics is high-risk graphics, which can be directly fed back to the layout design end without OPC correction and inspection; the second category of graphics is potential risk graphics, and defect risk graphics can be selected from the second category of graphics through a second screening. The second screening does not require a comprehensive OPC correction and inspection, but only requires a local OPC correction and inspection of the local area including the second category of graphics. Therefore, compared with the existing method that requires a comprehensive OPC correction and inspection, the present invention greatly reduces the number of graphics that require OPC correction and inspection, and can quickly and comprehensively screen defect problems caused by problematic layout graphics that exceed process capabilities, thereby improving publishing efficiency, that is, it can improve the efficiency of testing layout design and layout publishing during new process development.

[0043] In addition, in the local OPC inspection of the present invention, the OPC ADI model used in the existing OPC inspection is not used for inspection, but the OPC AEI model is used for inspection. The OPC AEI model can well detect the defect risk graph that the OPC ADI model cannot simulate when the lithography process capability limit is exceeded. Therefore, the present invention can well detect the defect risk graph and prevent the risk of false reporting and missed detection in the existing method.

[0044] In addition, since the number of graphics that need to be corrected and checked by OPC is greatly reduced in the present invention, the error rate is reduced, and the risk of error reporting and missed detection in the existing method can be further prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0046] Figure 1 It is a publication flow chart for handling existing layout design issues;

[0047] Figure 2A It is a flow chart of a method for OPC detection and early warning of a layout graphic with a problem of exceeding process capability according to an embodiment of the present invention;

[0048] Figure 2B It is a published flow chart of a method for detecting and early warning a layout graphic OPC problem exceeding process capability according to an embodiment of the present invention;

[0049] Figure 3A is an example of a DRC violation pattern;

[0050] Figure 3B is another example of a DRC violation graph;

[0051] Figure 4 It is a schematic diagram of the predictive capability of the embodiment of the present invention and the existing OPC model for the graph of the pitch violating DRC;

[0052] Figure 5A-Figure 5C It is a schematic diagram of the structure after etching of various potential risk graphics;

[0053] Figure 6 is a schematic diagram of selecting a graph for establishing an OPC AEI model from a plurality of graphs in a method according to an embodiment of the present invention;

[0054] Fig. 7A It is a kind of pich super-limit layout graphic;

[0055] Figure 7B Is to use the existing OPC model Fig. 7A The graphics obtained by simulating the layout graphics;

[0056] Figure 7C The OPC AEI model in the method of the embodiment of the present invention is used for Fig. 7A The graphics obtained by simulating the layout graphics. DETAILED DESCRIPTION

[0057] like Figure 2A As shown, it is a flow chart of the method for OPC detection and early warning of layout graphics with problems exceeding process capability according to an embodiment of the present invention; Figure 2BAs shown, it is a published flow chart of the method for detecting and warning the OPC of the layout graphics with the problem of exceeding the process capability according to the embodiment of the present invention; the method for detecting and warning the OPC of the layout graphics with the problem of exceeding the process capability according to the embodiment of the present invention is completed when the design rule check of the design layout is completed and an error is reported. Figure 2B In step S302 in the above example, if an error occurs, Figure 2B In the example, the design layout is obtained through layout design as in step S301, and step S301 is experimental layout design.

[0058] like Figure 2A As shown, the following steps are taken: Figure 2B Step S303 in the above is to detect problematic layout patterns that exceed the process capability:

[0059] Step S201: Mark the graphics of the error positions of the design rule check and use them as risk category graphics.

[0060] Step S202: classify the risk category graphics into first category graphics and second category graphics according to the graphic features.

[0061] The first type of graphics are high-risk graphics that exceed the process capability. When the first type of graphics exist, the first type of graphics are fed back to the layout design end.

[0062] The second type of graphics is potential risk graphics.

[0063] In the embodiment of the present invention, the graphic feature values ​​of the rule classification include: the circumference, size, interval, and upper and lower layer relationship of the graphic.

[0064] In some embodiments, the rule classification includes: classifying the high-risk graphics whose graphic characteristic values ​​exceed the design rules by more than 10% to 20% as the first-category graphics.

[0065] The rule classification further includes: classifying the risky graphics whose characteristic values ​​exceed the design rule by 10% to 20% as the second-category graphics.

[0066] When the second type of graphics is present, the second type of graphics is screened for the second time to find defect risk graphics, and the second screening includes:

[0067] Step S203, performing local OPC correction, wherein the local OPC correction obtains a first plate layer, and the object of the local OPC correction is a local area including the second type of graphics.

[0068] In some embodiments, the local OPC correction includes the following steps:

[0069] An area of ​​10 micrometers to 50 micrometers centered on the error reporting position of the second type of graphics is selected as the local area and a local marking layer corresponding to the local area is formed.

[0070] The first layer is obtained by performing OPC correction on the graphics in the local mark layer.

[0071] Step S204, performing a local OPC check, wherein the local OPC check determines whether the first layout layer has the defect risk pattern by performing AEI simulation prediction on the first layout layer using an OPC AEI model, and when the defect risk pattern is present, the defect risk pattern is fed back to the layout design end.

[0072] In the embodiment of the present invention, the modeling data of the OPC AEI model is data of a pattern after an etching process.

[0073] The OPC AEI model is a special OPC AEI model; the special OPC AEI model is established using a limit graph, the limit graph is a graph that violates the design rules, and the data corresponding to the post-etching graph with defective problems in the modeling data of the special OPC AEI model is marked as the limit small CD size that violates the design rules, that is, the limit small CD size can be determined based on the data corresponding to the post-etching graph with defective problems. In some embodiments, the limit small CD size is the limit size at which photoresist stripping occurs or the groove cannot be opened after photolithography.

[0074] A first threshold is set according to the limit small CD size, and the first threshold is greater than or equal to the limit small size.

[0075] The AEI simulation forecast includes:

[0076] The first layer is simulated using the special OPC AEI model to obtain simulation values ​​of each graphic in the first layer.

[0077] The graphic of the first layer corresponding to the simulation value smaller than the first threshold is marked as the defect risk graphic.

[0078] like Figure 2B As shown, when the first type of graphics is not detected and the defect risk graphics are not detected in the second type of graphics, the following steps are also included:

[0079] Step S304, performing comprehensive OPC correction on the design layout; Figure 2B In the present invention, the comprehensive OPC correction is also the OPC correction operation. In the existing method, the OPC correction is usually a comprehensive correction of all graphics of the layout.

[0080] Step S305: Perform a comprehensive OPC inspection. Figure 2B In the present invention, the comprehensive OPC inspection is also the traditional OPC inspection. Like the existing method, the traditional OPC inspection is a comprehensive inspection of the graphics of the layout, and the OPC model used is the OPC ADI model, and the OPC AEI model is not used.

[0081] After the comprehensive OPC inspection is passed, it also includes:

[0082] Step S306: Publish to form the final layout.

[0083] After the design rule check is completed, the embodiment of the present invention does not need to perform a comprehensive OPC correction on the entire layout. Instead, the graphics at the error position are first marked as risky graphics, and then the risky graphics are classified according to rules. The first category of graphics is high-risk graphics, which can be directly fed back to the layout design end without OPC correction and inspection; the second category of graphics is potential risk graphics, and defect risk graphics can be selected from the second category of graphics through a second screening. The second screening does not require a comprehensive OPC correction and inspection, but only requires a local OPC correction and inspection of the local area including the second category of graphics. Therefore, compared with the existing method that requires a comprehensive OPC correction and inspection, the embodiment of the present invention greatly reduces the number of graphics that require OPC correction and inspection, and can quickly and comprehensively screen defect problems caused by problematic layout graphics that exceed process capabilities, thereby improving publishing efficiency, that is, improving the efficiency of testing layout design and layout publishing during new process development.

[0084] In addition, in the local OPC inspection of the embodiment of the present invention, the OPC AEI model is not used for inspection as used in the existing OPC inspection. The OPC AEI model can well detect the defect risk graph that cannot be simulated by the OPC ADI model when the lithography process capability limit is exceeded. Therefore, the embodiment of the present invention can well detect the defect risk graph and prevent the risk of false reporting and missed detection in the existing method.

[0085] In addition, since the number of graphics that need to be corrected and checked by OPC is greatly reduced in the embodiment of the present invention, the error rate is reduced, and the risk of error reporting and missed detection in the existing method can be further prevented.

[0086] The OPC detection and early warning method for problem graphics exceeding process capability in the embodiment of the present invention can warn of defects caused by unreasonable layout design, can discover design problem graphics in advance, and save OPC resources for rework calculations caused by design problems.

[0087] The embodiment of the present invention defines graphic judgment through rules, selects problem graphics that potentially exceed process capabilities, performs local OPC correction on them, and then simulates the layout (Mask) of the potential problem graphics after normal OPC correction by using a special OPC model established by extreme graphic data to determine whether defects will occur. According to the detection results, early warning is given to the problem graphics.

[0088] The embodiments of the present invention can accurately determine the actual risk of problematic graphics exceeding process capabilities, issue early warnings for confirmed problematic graphics, and retain effective test key splits as much as possible, thereby guiding the design of layout test structures and avoiding defects caused by exceeding process capabilities. This can save design and OPC resource waste caused by rework due to design problems, and improve the efficiency of test layout design and mask publishing during new process development.

[0089] The embodiment of the present invention realizes early detection and early warning through OPC for the problem layout graphics exceeding the process capability, and thus can realize feedback modification. The method of the embodiment of the present invention is further described below:

[0090] In some experimental layouts, graphics that violate design rules are often introduced. Figure 3A The figure shows an example of a DRC violation pattern; the patterns 102 in area 101a are all bars and meet the design rules; for testing purposes, the pattern 102 in area 101a needs to be transformed to obtain the pattern 102 in area 101b. The pattern 102 in area 101b will violate the design rules, for example, the spacing between adjacent patterns 102 will be smaller than the spacing specified by the design rules, and the width of some patterns 102 is smaller than the width specified by the design rules. The pattern in area 101b has the risk of defects.

[0091] like Figure 3B As shown in FIG. 1 , it is an example of a DRC violation pattern; patterns 104 and 105 in region 103b are obtained by transforming patterns 104 and 105 in region 103a. Patterns 104 and 105 are patterns of different layers. For example, pattern 105 is a through hole and pattern 104 is a metal line. The setting of patterns 104 and 105 in region 103b violates the design rules. However Figure 3B The graph in area 103b does not have a defect risk and is a non-risk graph.

[0092] Therefore, it is necessary to Figure 3A The risk graphics in area 101b are used for detection and warning.

[0093] In the method of the embodiment of the present invention, for graphics reporting DRC errors, a data processing flow is firstly added to mark graphics violating DRC as a major category of potential risk graphics.

[0094] For graphics with high risk of design rule errors, we first use the rules to classify the graphics. Graphics that exceed the design rules by more than 10% to 20% are classified as the first category. High-risk graphics that exceed the process capability are directly fed back to modify the layout design.

[0095] Graphics that exceed the design rules by 10% to 20% are classified as the second type of potential risk graphics. For graphics that may have potential risk problems, they are first subjected to local, normal OPC corrections to obtain the Mask layer, and then the special OPC AEI model established with extreme graphics is used to perform AEI simulation prediction on the Mask to determine the actual risk.

[0096] like Figure 4 , which is a schematic diagram of the predictive capability of the embodiment of the present invention and the existing OPC model for the graph with pitch violating DRC; Figure 4 1 shows two different steps of the graph 102, namely pitch1 and pitch2, where pitch2 is larger.

[0097] When classifying rules, the spacing of the center lines of the figure 102, i.e., the stepping, can be selected for comparison with pitch 1 and pitch 2. If the center line spacing is smaller than pitch 1, these figures are selected and classified as the first type of figures, and are directly marked as defective figure E1 and fed back.

[0098] If the centerline spacing is greater than or equal to pitch1 and less than pitch2, these graphics are selected and classified as the second type of graphics. After that, the second type of graphics are expanded outward by a certain range D to generate a marker (Marker) DM, where D is the selected distance. The marker DM is used to select the local risk graphic area of ​​the entire layout, namely the local marker layer, and only the risk graphics in the selected local area are corrected normally by OPC to obtain the local risk graphic Mask layer, namely the first version layer.

[0099] After that, a special OPC AEI model is required for local OPC inspection. Figure 4 As shown, for the second type of graphics, the embodiment of the present invention uses a special OPC AEI model, that is, a specially established extreme condition OPC AEI model 201 to predict risks, while the normal published OPC model 202 cannot accurately predict risks.

[0100] In the embodiment of the present invention, it is necessary to use the etching results of the potential risk pattern on the test mask to build a special OPC AEI model, such as Figure 5A-Figure 5C The above is a schematic diagram of the structure after etching of various potential risk graphics; Graphic 301a corresponds to the graphic after the etching process when the critical dimension (CD) exceeds the limit, such as exceeding the limit of the photolithography process, Graphic 301b corresponds to the graphic after the etching process when the pitch exceeds the limit, and Graphic 301c corresponds to the graphic after the etching process when the pitch exceeds the limit too much.

[0101] The ADI graph cannot fully reflect whether there is a defect problem in the final AEI result. The modeling data of the critical CD or Pitch graph is the AEI size of the graph after the etching process. In particular, for the post-etching graph with defect problems, its data is marked as the extreme small CD size that violates the design rules, such as sub-rule -20%, and OPCAEI modeling is performed to obtain an OPC model that can be used to predict the AEI risk of sub-rule graphs.

[0102] That is, in the process of establishing a special OPC AEI model, you need to select the required graphics, such as Figure 6 , which is a schematic diagram of selecting a graph for establishing an OPC AEI model from a plurality of graphs in a method according to an embodiment of the present invention; Figure 6 It includes multiple graphics. The left side of line AA corresponds to the graphics obtained by performing ADI test on the corresponding layout graphics after completing the lithography process. The right side of line AA corresponds to the graphics obtained by performing AEI test on the corresponding layout graphics after completing the lithography process. It can be seen that when the graphics of the layout do not exceed the limit, the lithography process can still be completed correctly, and the ADI test graphics can also be observed. At this time, the existing OPC ADI model can be directly used to predict defects. As the CD of ADI decreases, when the graphics exceed the limit, the lithography process cannot transfer the graphics correctly, and the ADI test graphics will not be able to reflect the layout graphics. Therefore, the OPC ADI model cannot be used to predict defects; however, when the size of the graphics exceeds the limit, the AEI graphics can still be resolved to a certain extent, so that it can be used as a model graphic for defect prediction. Figure 6 In the figure, the layout graphics corresponding to the dotted boxes 401a and 401b are the same, the dotted box 401a cannot be distinguished, but the dotted box 401b can be distinguished, so the AEI graphics in the dotted box 401b can be used as the modeling graphics of the OPC AEI model of the corresponding layout graphics. Similarly, the AEI graphics in the dotted box 402b are used as the modeling graphics of the OPC AEI model of the layout graphics corresponding to the ADI graphics in the dotted box 402a.

[0103] When the special OPC AEI model is used to simulate the Mask, the normal OPC model predicts that there is no pattern and no alarm will be issued. However, when the specially established OPC AEI model is used, the simulation result is an error size that is smaller than the design rule, so that the actual defect problem graphics can be discovered and fed back to the design end for modification.

[0104] like Fig. 7A As shown, it is a pich super-limit layout pattern. It can be seen that the layout 501 has multiple bar patterns that can be distinguished on the layout.

[0105] like Figure 7B As shown, the existing OPC model is used to Fig. 7A It can be seen from the graphics obtained by simulating the layout graphics of that no graphics can be distinguished in the ADI graphics 502.

[0106] like Figure 7C As shown, the OPC AEI model in the method of the embodiment of the present invention is used for Fig. 7A It can be seen from the figure obtained by simulating the layout figure of the AEI figure 503 that there are multiple bar figures that can be distinguished on the layout. Therefore, the OPC AEI model used in the embodiment of the present invention can overcome the problem that the existing OPC model machine OPC ADI model cannot detect the problem layout figures that exceed the process capability.

[0107] The method of the embodiment of the present invention optimizes the data processing flow, pre-classifies DRC-violating graphics, corrects local OPC of high-risk graphics, and establishes a special OPC AEI model simulation early warning method, so as to more accurately control the defect problems of the problematic layout graphics that exceed the process capability, thereby improving the security and efficiency of development layout processing.

[0108] The embodiment of the present invention is an OPC detection and early warning method for layout graphics with problems exceeding process capabilities. DRC errors are used as risk markers, and then the spacing between lines in the graphics is classified. Graphics exceeding process capabilities are selected, and local normal OPC corrections are performed on them to obtain a Mask layer. A special OPC AEI model established using extreme graphics is used to perform AEI simulation on the Mask to determine whether defect problems will occur. Risk problem graphics are warned and corrected through the design end. This method can accurately determine the actual risk of graphics with problems exceeding process capabilities, warn of problematic graphics, and retain development test graphics as much as possible. It can be used to guide layout test structure design, avoid defect problems caused by exceeding process capabilities, save design and OPC resource waste caused by rework due to design problems, and improve the efficiency of test layout design and mask publishing when developing new processes.

[0109] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for detecting and warning the OPC of a layout graphic that exceeds the process capability, characterized in that: When the design rule check of the design layout is completed and an error is reported, the following steps are used to detect the problematic layout graphics that exceed the process capability: Marking the graphics of the error positions of the design rule check as risk category graphics; According to the graphic features, the risk category graphics are classified into the first category graphics and the second category graphics; The first type of graphics is a high-risk graphics that exceeds the process capability. When the first type of graphics exists, the first type of graphics is fed back to the layout design end; The second type of graphics is a potential risk graphics. When the second type of graphics exists, the second type of graphics is screened for the second time to find defect risk graphics. The second screening includes: Performing local OPC correction, wherein the local OPC correction obtains a first layer, and the object of the local OPC correction is a local area including the second type of graphics; A local OPC check is performed, wherein the local OPC check determines whether the first layout layer has the defect risk pattern by performing AEI simulation prediction on the first layout layer using an OPC AEI model, and when the defect risk pattern is present, the defect risk pattern is fed back to the layout design end.

2. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 1, characterized in that: The graphic feature values ​​of the rule classification include: the circumference, size, interval, and upper and lower layer relationships of the graphic.

3. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 2, characterized in that: The rule classification includes: classifying the risky graphics whose characteristic values ​​exceed the design rules by more than 10% to 20% as the first category of graphics.

4. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 2, characterized in that: The rule classification further includes: classifying the risky graphics whose characteristic values ​​exceed the design rule by 10% to 20% as the second-category graphics.

5. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 1 is characterized in that: The local OPC correction includes the following steps: Selecting an area of ​​10 micrometers to 50 micrometers centered on the error reporting position of the second type of graphics as the local area and forming a local marking layer corresponding to the local area; The first layer is obtained by performing OPC correction on the graphics in the local mark layer.

6. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 1 is characterized in that: The modeling data of the OPC AEI model is the data of the graphics after the etching process; The OPC AEI model is a special OPC AEI model; the special OPC AEI model is established using a limit graph, the limit graph is a graph that violates the design rules, and the data corresponding to the post-etching graph with defect problems in the modeling data of the special OPC AEI model is marked as a limit small CD size that violates the design rules; A first threshold is set according to the limit small CD size, and the first threshold is greater than or equal to the limit small size.

7. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 6 is characterized in that: The minimum CD size is a limit size at which photoresist stripping or trench opening cannot occur after photolithography.

8. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 6 is characterized in that: The AEI simulation forecast includes: Using the special OPC AEI model to simulate the first layer and obtain simulation values ​​of each graphic in the first layer; The graphic of the first layer corresponding to the simulation value smaller than the first threshold is marked as the defect risk graphic.

9. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 1, characterized in that: When the first type of pattern is not detected and the defect risk pattern is not detected in the second type of pattern, the following steps are also included: Perform comprehensive OPC correction on the design layout; Perform a comprehensive OPC inspection.

10. The OPC detection and early warning method for a layout graphic with a problem exceeding process capability as claimed in claim 9, characterized in that: After the comprehensive OPC inspection is passed, it also includes: Publish to form the final version.

Images