Warping-inhibiting packaging structure, packaging method and packaging mode determining method

Abstract

The invention relates to the field of chip packaging, in particular to a packaging structure for restraining warping, a packaging method and a packaging mode determining method. Comprising the steps that a first groove is formed in a solder mask layer of a substrate, and the first groove penetrates through an electric connection layer of the substrate; the annular reinforcing ribs are connected to the edge area of the substrate and used for restraining buckling deformation of the substrate. The arrangement position of the first groove corresponds to the mounting position of the annular reinforcing rib; the connection welding layer is fixed between the annular reinforcing rib and the electric connection layer of the substrate through welding, and the Young modulus of the connection welding layer is larger than a first preset hardness value. According to the packaging structure, the substrate and the annular reinforcing rib are fixedly connected in a welding mode, and the Young modulus of the welding flux forming the connecting welding layer is larger than that of the connecting glue layer. According to the packaging structure, the Young modulus of the connecting welding layer is larger, so that the connecting layer has higher hardness. And the buckling deformation of the substrate can be better inhibited.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a packaging structure, a packaging method and a packaging method determination method for suppressing warping. Background Art

[0002] In the emerging demands such as the Internet of Things, artificial intelligence, high-computing computing, and big data, a large amount of data transmission and transfer is required, which also places higher and higher requirements on processor performance. However, the traditional single chip design can no longer meet the growing demand. In order to meet this challenge, the existing GPU (Graphics Processing Unit), NPU (Neural network Processing Unit) and other chips are also developing in the direction of multi-contact, multi-chip, modularization and three-dimensionalization, and the corresponding large-size 2.5D system-level packaging has become the mainstream trend of advanced packaging of such chips. At the same time, since the system-level packaging involves a variety of heterogeneous materials, each material will shrink or expand according to its own characteristics under the influence of external pressure and temperature changes during chip reflow and surface mounting. However, since the deformation characteristics of each material are different, each material will deform according to its own expansion characteristics, which will cause the materials to squeeze and pull each other, and correspondingly bring a series of stress and warping problems. Especially for the pinless packaging method, warpage control is more important. The logic chip is made of silicon, with a CTE (Coefficient of thermal expansion) of 3-4ppm / ℃, while the substrate is made of organic matter and metal, with a CTE of 13-20ppm / ℃. Since the CTE of the two differs by 3-5 times, the degree of deformation between them is also quite different. As a result, the substrate will sink downward to form a smiley face shape or bulge upward to form a crying face shape under the influence of temperature, such as Figure 3 Excessive substrate warpage may cause reliability issues such as solder ball short circuit, open circuit, transfer board bump cracking, substrate cracking, and single silicon wafer breakage during chip mounting.

[0003] To solve the above problems, mainstream advanced packaging often uses flip chip (FC), multi-chip module (MCM) or 2.5D CoWoS / EMIB process for packaging. Specifically, a circle of harder stainless steel or copper reinforcement ribs (ring) is arranged around the substrate to control the warping problem of the substrate during the packaging reflow, mounting and use of the chip.

[0004] The related art uses ribs to suppress warping, which requires the size of the ribs to be increased to provide greater suppression. However, based on the chip packaging space, there is not enough space to prevent larger ribs. At the same time, as the thickness of the ribs increases, the resistance of the logic chip to transfer heat to the system-level heat dissipation module will increase, thereby reducing the chip's heat dissipation capacity. Therefore, the solution in the related art has limited ability to suppress substrate warping and cannot meet the warping suppression requirements of higher-performance chips. Summary of the invention

[0005] In view of this, the present invention provides a packaging structure and packaging method for suppressing warping, which at least partially solves the problem that the prior art has limited ability to suppress substrate warping and cannot meet the needs of higher performance chips for suppressing warping.

[0006] According to one aspect of the present invention, there is provided a packaging structure for suppressing warpage, comprising:

[0007] A substrate, wherein a first groove is formed on the solder resist layer of the substrate, and the first groove penetrates to the electrical connection layer of the substrate;

[0008] A warping suppression component is connected to the edge area of ​​the substrate and is used to suppress warping deformation of the substrate; the setting position of the first groove corresponds to the installation position of the warping suppression component;

[0009] The connecting solder layer is fixed between the warping suppression component and the electrical connection layer of the substrate by welding, and the Young's modulus of the connecting solder layer is greater than a first preset hardness value, and the first preset hardness value is greater than the maximum Young's modulus of the glue that can form the connecting glue layer.

[0010] Furthermore, the first groove penetrates to the grounding electrical connection metal layer of the substrate; and the warping suppression component is an annular reinforcement rib or a heat dissipation cover.

[0011] Furthermore, the warping suppression component is an annular reinforcing rib, and the width of the first groove is less than or equal to the width of the annular reinforcing rib.

[0012] Furthermore, the solder material forming the connection solder layer includes SAC305.

[0013] Furthermore, the thickness of the connecting welding layer is 0.05 mm.

[0014] Furthermore, it also includes:

[0015] Logic chip: the logic chip is fixedly connected to the central area of ​​the substrate through bump solder balls.

[0016] Furthermore, the specifications of the logic chip, the bump solder balls, the substrate, the annular reinforcement ribs and the connecting solder layer meet the following conditions:

[0017]

[0018] .

[0019] As a second aspect of the present invention, a packaging method for suppressing warpage is also provided, which is used to prepare any one of the above-mentioned packaging structures for suppressing warpage; comprising:

[0020] A first groove is formed on the substrate at a mounting position of the warpage suppression component so as to expose the electrical connection layer of the substrate;

[0021] Printing solder for forming a connection solder layer in the annular groove and performing solder paste inspection;

[0022] If the solder paste inspection passes, the warpage suppression component is mounted to the target area and optically inspected;

[0023] If the optical inspection passes, the warpage suppression component is soldered to the substrate by reflow soldering in a nitrogen environment.

[0024] Furthermore, the minimum temperature of the reflow soldering is 30°C, and the maximum temperature of the reflow soldering is 240°C.

[0025] As a third aspect of the present invention, a method for determining a packaging method of a substrate and an annular reinforcement rib is provided, which is used to determine the packaging method of a substrate and an annular reinforcement rib in a target packaging structure, wherein the specifications of a logic chip, a bump solder ball, a substrate and an annular reinforcement rib in the target packaging structure meet the following conditions:

[0026]

[0027]

[0028] The method for determining the packaging method of the substrate and the annular reinforcement rib includes the following steps:

[0029] According to the maximum allowable high-temperature warpage value G of the substrate in the target package structure Q And the maximum allowable value of low temperature warpage D Q , generate the connection thickness coefficient H of the connection layer between the base plate and the annular reinforcement; H satisfies the following conditions:

[0030] H=min(h 1 ,h 2 );

[0031] Among them, h 1 G Q The corresponding connection thickness value, h 1 Meet the following conditions: G Q =11333h 1 4 -7533.3h 13 +1791.7h 1 2 -268.17h 1 -147;

[0032] h 2 D Q The corresponding connection thickness value, h 2 Meet the following conditions: D Q =-4000h 2 4 +2933.3h 2 3 -870h 2 2 +166.67h 2 +124.5; and h 1 and h 2 All belong to [0.03mm, 0.25mm];

[0033] If H<0.05, then the packaging method of the substrate and the annular reinforcement rib in any one of the above packaging structures for suppressing warping is determined as the target packaging method.

[0034] The technical solution of the present invention has at least the following beneficial effects:

[0035] The packaging structure of the present invention uses welding to fix the substrate and the warpage suppression component, and the Young's modulus of the solder forming the connection welding layer is greater than the Young's modulus of the connection adhesive layer. Since the Young's modulus of the connection welding layer of this packaging structure is greater, the connection layer will have a greater hardness. Correspondingly, the fixing method of the connection welding layer will have a better inhibitory effect on the warpage deformation of the substrate than the existing fixing method of connecting the substrate and the warpage suppression component by gluing.

[0036] At the same time, since the Young's modulus of the connecting solder layer itself is much larger than that of the adhesive layer, the connecting solder layer can provide greater warping suppression than the connecting adhesive layer of the same thickness. In addition, for the connecting adhesive layer, since its hardness is very small, the greater the thickness, the lower the corresponding warping suppression ability. In order to prevent the adhesive layer from cracking due to the decrease in adhesion, the connecting adhesive layer needs to maintain a certain thickness. At the same time, since capacitors are usually arranged on the substrate, in order to improve the warping suppression ability in actual use, the thickness of the warping suppression component can only be increased, thereby increasing the risk of heat dissipation of the packaging system. The structure of the present invention can obtain higher warping suppression ability with a lower connecting solder layer, and can also reduce the thickness of the warping suppression component, thereby improving the heat dissipation capacity of the existing packaging structure and reducing the risk of heat dissipation of the packaging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 This is a top view schematic diagram of a packaging structure for suppressing warping in one embodiment of the present application;

[0039] Figure 2 It is a schematic diagram of a side cross-sectional structure of a packaging structure (annular reinforcement rib) for suppressing warping in another embodiment of the present application;

[0040] Figure 3 It is a schematic diagram of a side cross-sectional structure of a packaging structure using a connecting adhesive layer in another embodiment of the present application;

[0041] Figure 4 It is a schematic diagram of a side cross-sectional structure of a packaging structure for suppressing warping in another embodiment of the present application;

[0042] Figure 5 This is a schematic diagram of a side cross-sectional structure of a packaging structure (heat dissipation cover) for suppressing warping in another embodiment of the present application;

[0043] Figure 6 Schematic diagram of substrate warping corresponding to the connecting adhesive layer and the connecting solder layer in a high temperature environment (left) and a low temperature environment (left) in another embodiment of the present application;

[0044] Figure 7 Schematic diagram of substrate warping corresponding to different thicknesses of connecting adhesive layers in a high temperature environment (left) and a low temperature environment (left) in another embodiment of the present application; in the left figure, the thickness of the connecting adhesive layer corresponding to the curves from top to bottom decreases successively; in the right figure, the thickness of the connecting adhesive layer corresponding to the curves from top to bottom increases successively;

[0045] Figure 8 Schematic diagram of substrate warping corresponding to different thicknesses of connecting solder layers in a high temperature environment (left) and a low temperature environment (left) in another embodiment of the present application; the thickness of the connecting adhesive layer corresponding to the curves from top to bottom in the left figure increases successively; the thickness of the connecting adhesive layer corresponding to the curves from top to bottom in the right figure decreases successively;

[0046] Fig. 9 This is a diagram showing the relationship between the warping of connecting adhesive layers of different thicknesses and the substrate in a high temperature environment (left) and a low temperature environment (left) in another embodiment of the present application.

[0047] Reference numerals

[0048] 1. Substrate; 10. Solder resist layer; 11. Electrical connection layer; 12. First groove; 2. Annular reinforcement rib; 21. Heat dissipation cover; 30. Connecting solder layer; 31. Connecting adhesive layer; 4. Logic chip; 5. Bump solder ball; 6. Heat conduction part. DETAILED DESCRIPTION

[0049] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] It should be noted that the following embodiments and features in the embodiments may be combined with each other in the absence of conflict; and, based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making any creative work are within the scope of protection of the present disclosure.

[0051] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0052] As an embodiment of the present invention, Figures 1 to 4 As shown, a packaging structure for suppressing warping is provided, and the packaging structure includes: a substrate 1, a warping suppressing component and a connecting solder layer 30.

[0053] The substrate 1 is used to install the logic chip 4. The substrate 1 in this embodiment can be the substrate 1 used in the existing high-performance chip, and the logic chip 4 (also known as Die) can be an existing GPU, NPU or other chip. The connection between the substrate 1 and the logic chip 4 is as follows:

[0054] The logic chip 4 is fixedly connected to the central area of ​​the substrate 1 through the bump solder balls 5. By setting corresponding bump solder balls 5, the logic chip 4 and the substrate 1 can be electrically connected together to achieve corresponding power supply and / or signal transmission functions. Usually, in order to improve the protection of the bump solder balls 5, a filling glue (also known as underfill) is also set between the logic chip 4 and the substrate 1.

[0055] like Figure 1As shown, when the warping suppression component is an annular reinforcement rib 2, the annular reinforcement rib 2 (also known as a ring) is connected to the edge area of ​​the substrate 1 to suppress the warping deformation of the substrate 1. The annular reinforcement rib 2 can be a metal ring made of stainless steel. And because the warping deformation characteristic of the substrate 1 during the temperature change is that the farther the position is from the center of the substrate 1, the greater the warping deformation. Therefore, in this embodiment, in order to better suppress the deformation of the substrate 1, it will be fixed at the edge of the substrate 1.

[0056] Specifically, Figures 2 to 4 As shown, the substrate 1 includes: an electrical connection layer 11 and a solder resist layer 10 .

[0057] The solder resist layer 10 is coated on the outer surface of the electrical connection layer 11. A first groove 12 is provided in the connection area corresponding to the solder resist layer 10 and the annular reinforcement rib 2. The first groove 12 penetrates the electrical connection layer 11. The electrical connection layer 11 can generally be a grounded electrical connection metal layer located at the top layer.

[0058] Usually, the substrate 1 is a layered structure, with an electrical connection layer 11 (copper layer) disposed inside for realizing the electrical connection and routing function, and a solder resist layer 10 (usually green oil) disposed outside for protection. Therefore, in order to better weld the annular reinforcement rib 2 and the substrate 1 together, it is necessary to remove the solder resist layer 10 in the corresponding connection area to expose the copper underneath. This allows the bottom side of the connection solder layer 30 to be welded to the electrical connection layer 11 at the first groove 12.

[0059] Usually, in order to prevent the finally formed connection solder layer 30 from overflowing to the outside of the annular reinforcement rib 2 and failing to meet the surface quality requirements of the package, the width of the first groove 12 should be less than or equal to the width of the annular reinforcement rib 2. Of course, if the width of the first groove 12 is too small, the size of the connection solder layer 30 will be reduced, thereby reducing the ability to suppress deformation of the substrate 1, so preferably, the width of the first groove 12 should differ from the width of the annular reinforcement rib 2 in the range of 0-1mm.

[0060] The connecting solder layer 30 is fixed between the annular reinforcement rib 2 and the electrical connection layer 11 of the substrate 1 by welding. The Young's modulus of the connecting solder layer 30 is greater than a first preset hardness value, and the first preset hardness value is greater than the maximum Young's modulus of the glue that can form the connecting glue layer 31.

[0061] Specifically, in the packaging design of the related art, the annular reinforcement rib 2 is usually adhered to the substrate 1 around the connecting glue layer 31 formed by the corresponding glue. For example, the glue can be Dow Corning SE-4450 series glue. Its thermal expansion coefficient is 117*10^-6ppm / ℃, and the Young's modulus is 7.2MPa; or the glue can also be 3M's EW3011 series glue, which has a glass transition temperature Tg of 130℃. When the temperature is lower than Tg, the thermal expansion coefficient is 45*10^-6ppm / ℃, and when the temperature is higher than Tg, the thermal expansion coefficient is 300*10^-6ppm / ℃, and the Young's modulus of the EW3011 series glue is 5200MPa.

[0062] The Young's modulus and thermal expansion coefficient of the glue used will also have different performances. The first preset hardness value in this embodiment can be determined based on the maximum Young's modulus of the glue used in the prior art, such as 50000 MPa.

[0063] The connection solder layer 30 in this embodiment can be formed by any solder in the prior art whose Young's modulus is greater than the first preset hardness value and meets the requirements for chip packaging.

[0064] For solder, the copper content is generally adjustable within the range of 0.5 to 0.95%. The copper content in the solder can be increased by adding corresponding alloys, and the specific copper content requirement depends on the actual usage. A higher copper content is more conducive to the warping control of the package substrate 1, and a solder with a lower copper content has better toughness and can absorb some stress, which is beneficial to improving the reliability of the logic chip 4.

[0065] Preferably, in this embodiment, solder SAC305 can be used to form the corresponding connecting solder layer 30. Specifically, the components of SAC305 are tin, silver, and copper, and the proportions of the three are 96.5%, 3%, and 0.5%. Its thermal expansion coefficient is 23.5*10^-6ppm / ℃, and its Young's modulus is 51000MPa. The solder in this embodiment can not only provide a higher Young's modulus to meet the demand for suppressing the warping of the substrate 1. At the same time, the copper content is also low, which can improve the reliability of the logic chip 4 for the packaging structure in this embodiment.

[0066] From the above description and the common knowledge in the prior art, it can be known that for the solder and adhesive used in the packaging structure of the present invention, the Young's modulus of the solder is naturally much greater than that of the adhesive, and usually differs by at least one order of magnitude, such as 51000MPa and 5200MPa. Therefore, the hardness of the connecting solder layer 30 will also be much higher than the hardness of the connecting adhesive layer 31, thereby providing a higher warpage suppression capability.

[0067] In the same chip packaging structure, the connecting adhesive layer 31 (0.1 mm thickness) formed by the adhesive (EW-3011) and the connecting solder layer 30 (0.1 mm thickness) formed by the solder (SAC305) are used to connect and fix the annular reinforcing rib 2 and the substrate 1 to form an experimental group (SAC305) and a comparative group (EW-3011). Then, the warping of the substrate 1 in the experimental group and the comparative group is detected.

[0068] The specifications and materials of the logic chip 4, the bump solder balls 5, the substrate 1, the annular reinforcement ribs 2 and the connecting solder layer 30 in the specific chip packaging structure meet the conditions shown in Table 1 below:

[0069] Table 1

[0070]

[0071] The warping of the substrate 1 in the above experimental group and the comparison group in a high temperature environment (125-240°C) is shown in FIG. Figure 6 The warping of substrate 1 in the experimental group and the comparison group in a low temperature environment (125-30°C) is shown in the left figure. Figure 6 As shown in the right figure, the horizontal axis in the figure represents the distance between each detection point on the diagonal line of substrate 1 and the center point of substrate 1. The vertical axis represents the degree of warping of substrate 1 at each detection point on the diagonal line.

[0072] According to the experimental results, no matter in high temperature environment or low temperature environment, the experimental group has a more superior ability to suppress the warping of the substrate 1. Specifically, in the high temperature environment, the experimental group has a greater ability to suppress the maximum warping of the substrate 1 than the control group by (162.3-142) / 162.3=12.51%; in the low temperature environment, the experimental group has a greater ability to suppress the maximum warping of the substrate 1 than the control group by (135-118) / 135=12.59%.

[0073] Moreover, the maximum warping position of the experimental group is closer to the center of the substrate 1 than the maximum warping position of the control group, indicating that the connection structure in this embodiment can form a wider area for directly suppressing warping, thereby improving the warping degree of the corresponding position on the substrate 1 over a larger area.

[0074] As another embodiment of the present invention, preferably, when the solder is SAC305, the thickness of the connecting solder layer 30 is 0.05 mm.

[0075] Since the Young's modulus of the solder is relatively high, a relatively thin connection solder layer 30 can provide sufficient warpage suppression capability, and the warpage suppression capability can be further improved by increasing the content of hard components in the solder. Therefore, in the same chip packaging structure, the thickness of the connection solder layer 30 will be less than or equal to the thickness of the connection adhesive layer 31 while meeting the warpage suppression requirements.

[0076] At the same time, the thicker the connection solder layer 30 is, the greater the distance between the upper surface of the annular reinforcing rib 2 and the upper surface of the substrate 1 will be after the final packaging is completed ( Figure 4 In order to prevent the system-level heat sink from contacting the annular reinforcing rib 2, the thickness of the heat conducting portion 6 (generally a heat spreader or a copper plate) is increased, which leads to the thickness of the heat conducting portion 6 of the heat dissipation component disposed above the logic chip 4 ( Figure 4 The L2 in the figure is further increased, which ultimately increases the heat dissipation risk of the chip. Therefore, the thickness of the connecting solder layer 30 needs to be reduced as much as possible.

[0077] However, if the thickness of the connecting welding layer 30 is less than 0.05 mm, the construction difficulty will be greatly increased. Figure 8 It can be seen that when the solder is SAC305, as the thickness of the connection solder layer 30 increases, the ability to suppress the warping of the substrate 1 is not greatly improved, so the thickness of the connection solder layer 30 is preferably 0.05 mm.

[0078] In addition, since a portion of the connection solder layer 30 is embedded in the first groove 12 (the depth is 0.021 mm), under the condition of equal thickness, the L1 of the package structure using the connection solder layer 30 will be smaller than the L1 of the package structure using the connection adhesive layer 31. Moreover, under the condition of equal connection layer thickness, the connection solder layer 30 can provide greater warpage suppression capability, so on this basis, the thickness of the annular reinforcement rib 2 can be reduced, and then the L1 of the package structure using the connection solder layer 30 can be further reduced, so as to further reduce the heat dissipation risk of the chip after packaging and improve the reliability of the chip.

[0079] As another embodiment of the present invention, the thermal expansion coefficient of the connection solder layer 30 is smaller than the thermal expansion coefficient of the connection adhesive layer 31. In this embodiment, the thermal expansion coefficient of the connection adhesive layer 31 may be 45*10^-6ppm / °C.

[0080] In this embodiment, the thermal expansion coefficient of the substrate 1 of the experimental group is generally 14-15*10^-6ppm / ℃, while the thermal expansion coefficient of the adhesive used in the prior art is greater than that of the substrate 1, and the difference is large, so when deformation occurs, there is also a large difference in the degree of deformation between the adhesive and the substrate 1. Therefore, during the deformation process, the substrate 1 and the connecting adhesive layer 31 will be more likely to crack, thereby causing the annular reinforcing rib 2 to detach.

[0081] Compared with the existing connection adhesive layer 31, the expansion coefficient of the solder SAC305 used in this embodiment is 23.5*10^-6ppm / ℃, which is closer to the difference in thermal expansion coefficient of the substrate 1, so when deformation occurs, the deformation degree of the solder and the substrate 1 is also closer. Therefore, during the deformation process, the substrate 1 and the connection adhesive layer 31 are not easy to crack, thereby making the connection between the annular reinforcement rib 2 and the substrate 1 tighter, improving the packaging stability.

[0082] As another embodiment of the present invention, the first groove 12 penetrates to the grounding electrical connection metal layer of the substrate 1 ; and the warpage suppression component is a heat dissipation cover 21 .

[0083] The heat dissipation cover 21 in this embodiment can be a lid in an existing chip packaging structure. Its functions include suppressing the warping deformation of the substrate 1, dissipating the heat generated by the die, and providing mechanical protection for the die. Figure 5 As shown, it is a cover-shaped component with an n-shaped opening on one side, which is buckled and connected to the substrate. Specifically, the lower end of the heat dissipation cover 21 is fixedly welded to the grounding electrical connection metal layer through the connection welding layer 30. The heat dissipation cover 21 is usually made of metal, such as stainless steel.

[0084] The above-mentioned heat dissipation cover 21 can not only better suppress the warping of the substrate 1, but also refer to the warping suppression effect of the annular reinforcement rib 2 in the above-mentioned embodiment. In addition, since the heat dissipation cover 21 is connected to the grounded electrical connection metal layer through the connecting solder layer 30, a completely closed metal cavity can be formed, and the metal cavity can completely cover the die therein. The metal cavity is equivalent to an electromagnetic shielding cover, which can play an electromagnetic shielding role and improve the anti-interference ability of the die to external electromagnetic signals. On this basis, there is no need to set a system-level electromagnetic shielding component outside the entire chip packaging structure, thereby reducing the space occupied by the system-level electromagnetic shielding component on the PCB board.

[0085] As another embodiment of the present invention, a packaging method for suppressing warping is also provided, which is used to prepare the above-mentioned packaging structure for suppressing warping. Specifically, it comprises the following steps:

[0086] An annular groove is provided at the installation position of the annular reinforcing rib 2 on the substrate 1 so as to expose the electrical connection layer 11 of the substrate 1 .

[0087] The solder for forming the connection solder layer 30 is printed in the annular groove, and the solder paste inspection is performed.

[0088] The purpose of solder paste inspection is to detect whether the position and amount of printed solder paste are correct. It mainly detects whether there are any abnormalities such as missing printing, offset, insufficient solder paste, excessive solder paste, etc.

[0089] If the solder paste inspection passes, the annular reinforcement rib 2 is mounted to the target area and optical inspection is performed.

[0090] The purpose of optical inspection is to detect welding quality, specifically to detect whether there are abnormalities such as empty welds, bridging, and breakage.

[0091] If the optical inspection passes, the annular reinforcement rib 2 is welded to the substrate 1 by reflow soldering in a nitrogen environment. Further, the minimum temperature of the reflow soldering is 30°C, and the maximum temperature of the reflow soldering is 240°C.

[0092] The method of fixing the annular reinforcing rib 2 and the substrate 1 by connecting the solder layer 30 provided in this embodiment is consistent with the reflow soldering method used in the existing chip packaging. Therefore, the packaging structure of the present invention can be realized by using the existing reflow soldering equipment and process, which increases the difficulty of realizing the packaging structure of the present invention and improves the applicability. There is no need to manufacture new quilt equipment, and the existing equipment and process of the packaging manufacturer can be realized.

[0093] As another embodiment of the present invention, a method for determining the packaging method of the substrate 1 and the annular reinforcement rib 2 is also provided, which is used to determine the packaging method of the substrate 1 and the annular reinforcement rib 2 in the target packaging structure, and the specifications of the logic chip 4, the bump solder ball 5, the substrate 1 and the annular reinforcement rib 2 in the target packaging structure meet the following conditions:

[0094]

[0095] The method for determining the packaging method of the substrate 1 and the annular reinforcement rib 2 comprises the following steps:

[0096] According to the maximum allowable high-temperature warpage value G of the substrate 1 in the target package structure Q And the maximum allowable value of low temperature warpage D Q , generate the connection thickness coefficient H of the connection layer between the substrate 1 and the annular reinforcement rib 2; H satisfies the following conditions:

[0097] H=min(h 1 ,h 2 );

[0098] Among them, h 1 G Q The corresponding connection thickness value, h 1 Meet the following conditions: G Q =11333h 1 4 -7533.3h 1 3 +1791.7h 1 2 -268.17h 1 -147;

[0099] h 2 D Q The corresponding connection thickness value, h 2 Meet the following conditions: D Q =-4000h 2 4 +2933.3h 2 3 -870h 2 2 +166.67h 2 +124.5; and h 1 and h 2 All belong to [0.03mm, 0.25mm];

[0100] If H<0.05, then the packaging method of the substrate 1 and the annular reinforcing rib 2 in any one of the above packaging structures for suppressing warping is determined as the target packaging method.

[0101] If the existing 3M-EW3011 series adhesive with a higher Young's modulus is used to form a connection adhesive layer 31 of different thicknesses (0.05 / 0.1 / 0.15 / 0.2 / 0.25 mm), the substrate 1 and the annular reinforcement rib 2 in the target packaging structure provided by this embodiment are connected respectively, and the warping of the substrate 1 in a high temperature environment and a low temperature environment is detected, as follows Figure 7 As shown, the horizontal axis represents the thickness of the connecting adhesive layer 31, the vertical axis represents the maximum warping value of the substrate 1, and positive and negative represent the warping direction.

[0102] Depend on Figure 7 and Fig. 9 The negative correlation between the thickness of the connecting adhesive layer 31 and the degree of warpage shown in the data can be fitted to the relationship between the thickness of the connecting adhesive layer 31 and the degree of warpage in a high temperature environment (125-240°C): y = 11333x 4 -7533.3x 3 +1791.7x 2 -268.17x-147; and the relationship between the thickness of the connecting adhesive layer 31 and the degree of warping in a low temperature environment (125-30°C): y = -4000x 4 +2933.3x 3 -870x 2 +166.67x+124.5, wherein x represents the thickness of the connecting adhesive layer 31 , and y represents the maximum warpage value of the substrate 1 .

[0103] The above relationship is verified using other warping conditions of the thickness of the connecting adhesive layer 31, and the results are shown in Table 2 below:

[0104] Table 2

[0105]

[0106] According to the situation shown in Table 2, the fitting relationship in this embodiment has a high accuracy, and thus the target packaging structure in this embodiment can be more accurately determined, and the warping suppression effect on the substrate 1 after packaging with the connecting glue layer 31 can be determined.

[0107] Correspondingly, in this embodiment, according to G Q =11333h 1 4 -7533.3h 1 3 +1791.7h 1 2 -268.17h 1 -147 and D Q =-4000h 2 4 +2933.3h 2 3 -870h 2 2 +166.67h 2 +124.5 more accurately determines h 1 and h 2 At the same time, since the thickness of the connecting adhesive layer 31 is negatively correlated with the degree of warpage, h is selected. 1 and h 2 The minimum value of is taken as the connection thickness coefficient. If H<0.05, it means that the thickness of the connection adhesive layer 31 is less than 0.05mm. In this case, the construction of the connection adhesive layer 31 is too difficult, and the connection adhesive layer 31 is prone to cracking and falling off in the later stage, and the chip stability is low. Therefore, in this case, the packaging method provided by the present invention through the connection welding layer 30 can be directly used to package the substrate 1 and the annular reinforcement rib 2, so as to better meet the target packaging structure The requirements for suppressing warpage.

[0108] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A packaging structure that suppresses warping, It is characterized in that include: A substrate, wherein a first groove is formed on the solder resist layer of the substrate, and the first groove penetrates to the electrical connection layer of the substrate; A warping suppression component connected to an edge region of the substrate, used to suppress warping deformation of the substrate; the setting position of the first groove corresponds to the installation position of the warping suppression component; The connecting solder layer is fixed between the warping suppression component and the electrical connection layer of the substrate by welding, and the Young's modulus of the connecting solder layer is greater than a first preset hardness value, and the first preset hardness value is greater than the maximum Young's modulus of the glue that can form the connecting glue layer.

2. The packaging structure for suppressing warpage according to claim 1, It is characterized in that The first groove penetrates to the grounding electrical connection metal layer of the substrate; and the warping suppression component is an annular reinforcement rib or a heat dissipation cover.

3. The packaging structure for suppressing warpage according to claim 1, It is characterized in that The warpage suppression component is an annular reinforcing rib, and a width of the first groove is less than or equal to a width of the annular reinforcing rib.

4. The packaging structure for suppressing warpage according to claim 1, It is characterized in that The solder material forming the connecting solder layer includes SAC305.

5. The packaging structure for suppressing warpage according to claim 4, It is characterized in that The thickness of the connecting solder layer is 0.05 mm.

6. The packaging structure for suppressing warpage according to claim 3, It is characterized in that Also includes: A logic chip is fixedly connected to the central area of ​​the substrate through bump solder balls.

7. The packaging structure for suppressing warpage according to claim 6, It is characterized in that The specifications of the logic chip, bump solder balls, substrate, annular reinforcement ribs and connecting solder layers meet the following conditions:

8. A packaging method for suppressing warpage, It is characterized in that A packaging structure for preventing warpage according to any one of claims 1 to 7; comprising: A first groove is formed on the substrate at the installation position of the warpage suppression component so as to expose the electrical connection layer of the substrate; Printing solder for forming the connecting solder layer in the annular groove, and performing solder paste detection; If the solder paste inspection passes, mounting the warpage suppression component to a target area and performing an optical inspection; If the optical inspection passes, the warpage suppression member is soldered to the substrate by reflow soldering in a nitrogen environment.

9. A packaging method for suppressing warpage according to claim 8, It is characterized in that The lowest temperature of the reflow soldering is 30°C, and the highest temperature of the reflow soldering is 240°C.

10. A method for determining the packaging method of a substrate and annular reinforcement ribs, It is characterized in that It is used to determine the packaging method of the substrate and the annular reinforcement rib in the target packaging structure, and the specifications of the logic chip, the bump solder ball, the substrate and the annular reinforcement rib in the target packaging structure meet the following conditions: The method for determining the packaging method of the substrate and the annular reinforcement rib comprises the following steps: According to the maximum allowable high-temperature warpage value G of the substrate in the target package structure Q And the maximum allowable value of low temperature warpage D Q , generate the connection thickness coefficient H of the connection layer between the substrate and the annular reinforcement rib; H satisfies the following conditions: H=min(h 1 ,h 2 ); Among them, h 1 G Q The corresponding connection thickness value, h 1 Meet the following conditions: G Q =11333h 1 4 -7533.3h 1 3 +1791.7h 1 2 -268.17h 1 -147; h 2 D Q The corresponding connection thickness value, h 2 Meet the following conditions: D Q =-4000h 2 4 +2933.3h 2 3 -870h 2 2 +166.67h 2 +124.5; and h 1 and h 2 All belong to [0.03mm, 0.25mm]; If H<0.05, the packaging method of the substrate and the annular reinforcement rib in the packaging structure for suppressing warping described in any one of claims 1 to 6 is determined to be the target packaging method.

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