Digital multi-bit RRAM calculation method and device for protecting high-weight data

Abstract

The invention relates to a digital multi-bit RRAM calculation method and device for protecting high-weight data, and the method comprises the steps: carrying out the separated processing of the output of a multi-bit RRAM, storing a plurality of pieces of weight data in one RRAM, and carrying out the separation protection or direct output to protect the high order, so as to guarantee the accuracy of the data; according to the method, the fault-tolerant rate of neural network convolution is combined, the calculation power consumption is greatly reduced in the test process, the accuracy and the power consumption are balanced, the multiplication and addition calculation is more flexible, and the data reliability is greatly ensured. Therefore, the problems that due to the fact that the output of the RRAM is very dense and instability exists in the RRAM, drifting possibly exists, and part of data is prone to being flipped are solved.

Description

Technical Field

[0001] The present application relates to the field of digital multi-bit RRAM storage technology, and in particular to a digital multi-bit RRAM calculation method and device for protecting high-weight data. Background Art

[0002] RRAM (Resistive Random Access Memory) is a very suitable non-volatile memory for neural network hardware acceleration. It has a very high density and can be used for storage and computing. At present, digital multi-BIT (Binary Digit) is a method with high feasibility and high reliability.

[0003] However, since RRAM output is very dense, data transmission errors may occur during the transmission process, causing some of the output data to flip. In addition, the drift of adjacent conductivity states of RRAM devices will cause data errors, and the intermediate conductivity state is relatively more unstable. At the same time, RRAM can usually only be used once after writing to store multi-bit or single-bit data for stability.

[0004] In summary, since RRAM output is very dense and has its own instability, there may be drift, which can easily cause some data to flip, which needs to be solved urgently. Summary of the invention

[0005] The present application provides a digital multi-bit RRAM calculation method and device for protecting high-weight data, so as to solve the problems that the RRAM output is very dense and has its own instability, which may cause drift and easily lead to partial data flipping.

[0006] The first aspect embodiment of the present application provides a digital multi-bit RRAM calculation method for protecting high-weight data, including the following steps: determining the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data according to the number of bits of the multiple target multi-bit weight data, and controlling each RRAM to output multiple columns of current values in each calculation cycle; converting each column of current values in the multiple columns of current values into two-bit data in the corresponding target multi-bit weight data, and determining the high-bit data and the low-bit data in the two-bit data for each target multi-bit weight data in each calculation cycle; determining multiple check-bit RRAMs among all the RRAMs, and using the multiple check-bit RRAMs to perform a data check operation on the high-bit data of each target multi-bit weight data in each calculation cycle, and performing a multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data, and performing a multiply-accumulate operation on the high-bit data after the data check operation and the high-bit data of the preset stored data, so as to obtain a low-weight multiply-accumulate result and a high-weight multiply-accumulate result; performing a preset shift operation on the high-weight multiply-accumulate result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and adding the shifted data and the low-weight multiply-accumulate result to obtain the data multiply-accumulate result corresponding to the multiple target multi-bit weight data.

[0007] Optionally, in an embodiment of the present application, the controlling each preset RRAM to output multiple columns of current values in each calculation cycle includes: determining the target bit line corresponding to each calculation cycle, and applying a preset voltage to the target bit line to control each RRAM to output the multiple columns of current values in each calculation cycle.

[0008] Optionally, in an embodiment of the present application, the converting each column of current values in the multiple columns of current values into two-bit data in the corresponding target multi-bit weight data includes: based on a preset SA structure, converting each column of current values into a corresponding target voltage value, and using a preset digital-to-analog converter to generate the two-bit data corresponding to the target voltage value.

[0009] Optionally, in an embodiment of the present application, determining multiple check-bit RRAMs among all the RRAMs, and using the multiple check-bit RRAMs to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle, and performing multiplication and addition operations on the low-bit data and the low-bit data of the preset stored data, and performing multiplication and addition operations on the high-bit data after the data verification operation and the high-bit data of the preset stored data, to obtain a low-bit weight multiplication and addition result and a high-bit weight multiplication and addition result, includes: determining the multiple check-bit RRAMs among all the RRAMs, and obtaining corresponding check-bit data according to the multiple check-bit RRAMs; transmitting the high-bit data to a preset verification unit to perform ECC data verification operation on the high-bit data by using the check-bit data in the verification unit to repair the high-bit data with a preset flip error; sending the high-bit data after the data verification operation to a preset high-bit weight multiplication and addition unit to perform multiplication and addition operations on the high-bit data after the data verification operation and the high-bit data of the preset stored data in the preset high-bit weight multiplication and addition unit to obtain the high-bit weight multiplication and addition result; sending the low-bit data to a preset low-bit weight multiplication and addition unit, and performing multiplication and addition operations on the low-bit data and the low-bit data of the preset stored data in the preset low-bit weight multiplication and addition unit to obtain a low-bit weight multiplication and addition result.

[0010] Optionally, in an embodiment of the present application, performing a preset shift operation on the high-bit weight multiplication and addition result to obtain shift data of each target multi-bit weight data in each calculation cycle, and adding the shift data and the low-bit weight multiplication and addition result to obtain a data multiplication and addition result corresponding to the multiple target multi-bit weight data, includes: performing a preset shift operation on the high-bit weight multiplication and addition result in each calculation cycle to obtain shift data and a displacement number signal corresponding to each calculation cycle; adding the shift data and the low-bit weight multiplication and addition result to obtain a high-low bit addition result, and performing a preset optional displacement operation on the high-low bit addition result according to the displacement number signal corresponding to each calculation cycle to obtain an optional displacement result of each target multi-bit weight data in each calculation cycle; sending the optional displacement result corresponding to each target multi-bit weight data to a preset accumulator to obtain a data multiplication and addition result corresponding to the multiple target multi-bit weight data.

[0011] The second aspect of the embodiments of the present application provides a digital multi-bit RRAM computing device for protecting high-weight data, including: a control module, configured to determine the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data according to the number of bits of the multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values in each calculation cycle; a conversion module, configured to convert each column of current values into two-bit data in the corresponding target multi-bit weight data, and determine the high-bit data and the low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle; a verification module, configured to determine multiple verification-bit RRAMs among all RRAMs, and perform a data verification operation on the high-bit data of each target multi-bit weight data in each calculation cycle by using the multiple verification-bit RRAMs, and perform a multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data, and perform a multiply-accumulate operation on the high-bit data after the data verification operation and the high-bit data of the preset stored data, so as to obtain a low-weight multiply-accumulate result and a high-weight multiply-accumulate result; a calculation module, configured to perform a preset shift operation on the high-weight multiply-accumulate result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and add the shifted data and the low-weight multiply-accumulate result to obtain the data multiply-accumulate result corresponding to the multiple target multi-bit weight data.

[0012] Optionally, in an embodiment of the present application, the control module includes: a determination unit, configured to determine the target bit line corresponding to each calculation cycle, and apply a preset voltage to the target bit line to control each RRAM to output the multiple columns of current values in each calculation cycle.

[0013] Optionally, in an embodiment of the present application, the conversion module includes: a generation unit, configured to convert each column of current values into a corresponding target voltage value based on a preset SA structure, and generate two-bit data corresponding to the target voltage value by using a preset digital-to-analog converter.

[0014] Optionally, in an embodiment of the present application, the inspection module includes: an acquisition unit, configured to determine the plurality of check-bit RRAMs among all the RRAMs, and acquire corresponding check-bit data according to the plurality of check-bit RRAMs; a repair unit, configured to transmit the high-bit data to a preset inspection unit, so as to perform an ECC data verification operation on the high-bit data by using the check-bit data in the inspection unit, so as to repair the high-bit data with a preset flip error; a first multiply-accumulate unit, configured to send the high-bit data after the data verification operation to a preset high-bit weight multiply-accumulate unit, so as to perform a multiply-accumulate operation on the high-bit data after the data verification operation and the high-bit data of the preset stored data in the preset high-bit weight multiply-accumulate unit, so as to obtain the high-bit weight multiply-accumulate result; a second multiply-accumulate unit, configured to send the low-bit data to a preset low-bit weight multiply-accumulate unit, and perform a multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data in the preset low-bit weight multiply-accumulate unit, so as to obtain the low-bit weight multiply-accumulate result.

[0015] Optionally, in an embodiment of the present application, the calculation module includes: a first shift unit, configured to perform a preset shift operation on the high-bit weight multiply-accumulate result in each calculation cycle, so as to obtain a shift data and a displacement number signal corresponding to each calculation cycle; a second shift unit, configured to add the shift data and the low-bit weight multiply-accumulate result to obtain a high-low bit addition result, and perform a preset optional shift operation on the high-low bit addition result according to the displacement number signal corresponding to each calculation cycle, so as to obtain an optional shift result of each target multi-bit weight data in each calculation cycle; an accumulation unit, configured to send the optional shift result corresponding to each target multi-bit weight data to a preset accumulator, so as to obtain a data multiply-accumulate result corresponding to the plurality of target multi-bit weight data.

[0016] An embodiment of the third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor executes the program to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described in the above embodiment.

[0017] An embodiment of the fourth aspect of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the program is executed by a processor, it implements the digital multi-bit RRAM calculation method for protecting high-weight data as above.

[0018] An embodiment of the fifth aspect of the present application provides a computer program product, including a computer program, where the computer program is executed to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described above.

[0019] Accordingly, the embodiments of the present application have the following beneficial effects:

[0020] The embodiments of the present application can determine the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data according to the number of bits of the multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values within each calculation cycle; convert each column of current values in the multiple columns of current values into two-bit data in the corresponding target multi-bit weight data, and determine the high-bit data and low-bit data in the two-bit data of each target multi-bit weight data within each calculation cycle; determine multiple check-bit RRAMs among all RRAMs, and use the multiple check-bit RRAMs to perform data check operations on the high-bit data of each target multi-bit weight data within each calculation cycle, and perform multiplication and addition operations on the low-bit data and the low-bit data of the preset stored data, and perform multiplication and addition operations on the high-bit data after the data check operation and the high-bit data of the preset stored data, so as to obtain the low-bit weight multiplication and addition result and the high-bit weight multiplication and addition result; perform a preset shift operation on the high-bit weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data within each calculation cycle, and add the shifted data and the low-bit weight multiplication and addition result to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data. The present application can effectively use ECC (Error-Correcting Code) to check and correct the high bits to improve the calculation accuracy. At the same time, the method of using one RRAM unit for high-BIT and low-BIT storage can increase the density of RRAM, thereby realizing the reuse of RRAM and high-precision output. Accordingly, the problems that due to the very dense output of RRAM and its inherent instability, there may be drift and it is easy to cause partial data flipping are solved.

[0021] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, wherein:

[0023] Figure 1 is a flowchart of a digital multi-bit RRAM calculation method for protecting high-weight data according to an embodiment of the present application;

[0024] Figure 2 is a schematic diagram of an 8-bit data storage structure provided by an embodiment of the present application;

[0025] Figure 3 Schematic diagram of protecting high-weight output information provided for an embodiment of the present application;

[0026] Figure 4 Schematic diagram of the output calculation structure of a multi-BIT RRAM storage cell provided for an embodiment of the present application;

[0027] Figure 5 Schematic diagram of the process of performing multiplication and addition calculations on eight 8-bit numbers provided for an embodiment of the present application;

[0028] Figure 6 Example diagram of a digital multi-bit RRAM calculation device for protecting high-weight data according to an embodiment of the present application;

[0029] Figure 7 Schematic diagram of the structure of an electronic device provided for an embodiment of the present application.

[0030] Among them, 10 is a digital multi-bit RRAM calculation device for protecting high-weight data; 100 is a control module, 200 is a conversion module, 300 is an inspection module, 400 is a calculation module; 701 is a memory, 702 is a processor, and 703 is a communication interface. Specific implementation manners

[0031] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application and should not be construed as a limitation to the present application.

[0032] The following describes a digital multi-bit RRAM calculation method and apparatus for protecting high-weight data according to embodiments of the present application. In view of the problems mentioned in the above background art, the present application provides a digital multi-bit RRAM calculation method for protecting high-weight data. In this method, the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data are determined according to the number of bits of the multiple target multi-bit weight data, and each RRAM is controlled to output multiple columns of current values in each calculation cycle; each column of current values in the multiple columns of current values is converted into two-bit data in the corresponding target multi-bit weight data, and the high-bit data and the low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle are determined; multiple check-bit RRAMs in all RRAMs are determined, and the multiple check-bit RRAMs are used to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle, and perform multiplication-addition operations on the low-bit data and the low-bit data of the preset stored data, and perform multiplication-addition operations on the high-bit data after the data verification operation and the high-bit data of the preset stored data, so as to obtain a low-weight multiplication-addition result and a high-weight multiplication-addition result; a preset shift operation is performed on the high-weight multiplication-addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and the shifted data and the low-weight multiplication-addition result are added to obtain the data multiplication-addition result corresponding to the multiple target multi-bit weight data. The present application can effectively use ECC to check and correct the high bits to improve the calculation accuracy. At the same time, a RRAM unit can be used for high-BIT and low-BIT storage, increasing the density of the RRAM, thereby realizing the reuse of the RRAM and high-precision output. Thus, the problems that due to the very dense output of the RRAM and its inherent instability, there may be drift and it is easy to cause partial data flipping are solved.

[0033] Specifically, Figure 1 FIG. is a flowchart of a digital multi-bit RRAM calculation method for protecting high-weight data provided by an embodiment of the present application.

[0034] As Figure 1 shown, the digital multi-bit RRAM calculation method for protecting high-weight data includes the following steps:

[0035] In step S101, the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data are determined according to the number of bits of the multiple target multi-bit weight data, and each RRAM is controlled to output multiple columns of current values in each calculation cycle.

[0036] Embodiments of the present application can first determine the subsequent number of calculation cycles according to the number of bits of multi-bit weight data. For example, 8-bit data requires a total of four RRAMs and four calculation cycles, and each RRAM is controlled to output multiple columns of current values within each calculation cycle.

[0037] Optionally, in an embodiment of the present application, controlling each preset RRAM to output multiple columns of current values within each calculation cycle includes: determining the target bit line corresponding to each calculation cycle, and applying a preset voltage to the target bit line to control each RRAM to output multiple columns of current values within each calculation cycle.

[0038] Specifically, Figure 2 For the schematic diagram of the 8-bit data storage structure, as can be seen from Figure 2 it, the RRAM is of the 1T1R structure. Within each calculation cycle, embodiments of the present application can select the row to be output through the bit line, and under the control of the input voltage, each RRAM can output the stored data information according to the pre-written weight information, and output each column of current according to output each column of current.

[0039] In step S102, each column of current values among the multiple columns of current values is converted into two-bit data in the corresponding target multi-bit weight data, and the high-bit data and low-bit data in the two-bit data of each target multi-bit weight data within each calculation cycle are determined.

[0040] Furthermore, embodiments of the present application convert each column of current values into corresponding two-bit data, and determine the high-bit data and low-bit data in the two-bit data of each target multi-bit weight data within each calculation cycle.

[0041] Optionally, in an embodiment of the present application, converting each column of current values among the multiple columns of current values into two-bit data in the corresponding target multi-bit weight data includes: based on a preset SA structure, converting each column of current values into a corresponding target voltage value, and using a preset digital-to-analog converter to generate two-bit data corresponding to the target voltage value.

[0042] As a feasible implementation manner, embodiments of the present application can convert each column of current values into a corresponding voltage through the SA structure, and then compare the converted voltage in the analog-to-digital converter to output 2-bit data, so as to read 2-bit digital data from the RRAM.

[0043] It should be noted that a total of 4 RRAMs are required to output 8-bit data. Subsequently, embodiments of the present application can control the bit line to read out the other 6-bit information in other calculation cycles. In short, embodiments of the present application can read 2-bit data in each calculation cycle, and a total of 4 cycles can read out 8-bit data.

[0044] It can be understood that although an RRAM stores 2-bit data, the weights of the 2-bit data are not continuous in the whole. In the first cycle, the data read from the lower bit by the embodiment of the present application is data[0], and the data read from the higher bit is data[4]; similarly, in the second cycle, data[1] is output from the lower bit of the RRAM, and data[5] is output from the higher bit; in the next two cycles, data[2], data[6] and data[3], data[7] are output. Two data are processed in one cycle, but the higher-bit data is given higher weight information in the processing; for example, when processing 8-bit data, the higher-bit data on the same RRAM needs to be left-shifted by 4 bits relative to the lower-bit data, as Figure 2 shown. The first RRAM stores 10, and the second, third, and fourth RRAMs store 01, 01, 10. When WL<0> is turned on in the first cycle, the embodiment of the present application can obtain xxx1xxx0; when WL<1> is turned on in the second cycle. xx01xx10 can be obtained; in the third cycle, x001x110 can be obtained; in the fourth cycle, the complete 8-bit number 10010110 is obtained.

[0045] In step S103, multiple check-bit RRAMs in all RRAMs are determined, and the high-bit data of each target multi-bit weight data in each calculation cycle is subjected to a data check operation by using the multiple check-bit RRAMs, and a multiply-add operation is performed on the low-bit data and the low-bit data of the preset stored data, and a multiply-add operation is performed on the high-bit data after the data check operation and the high-bit data of the preset stored data, so as to obtain a low-bit weight multiply-add result and a high-bit weight multiply-add result.

[0046] Those skilled in the art should understand that in multi-bit programming, due to the relatively more unstable intermediate conductance state of the RRAM, it may shift during the read process and the output process, resulting in the flipping of the output high bit or low bit; if two bits are checked simultaneously, the used check formula is relatively complex, and the adjacent conductance state drift will only cause 1 LSB error, and it is impossible to make corresponding adjustments according to the data distribution, which is easy to cause inaccurate correction and high power consumption in the check.

[0047] As can be seen from the above readout method of the 2-bit RRAM, although they all come from the same RRAM, their weight information in the overall data is times (n is the number of bits of the data). If the higher-bit data is flipped, obviously, it has a greater impact on the result. Although both data can be checked and protected, the check power consumption is large. Therefore, the embodiment of the present application can only perform protection check on the higher weight in the storage structure circuit, so as to improve the calculation accuracy.

[0048] Optionally, in an embodiment of the present application, a plurality of check-bit RRAMs among all RRAMs are determined, and the high-bit data of each target multi-bit weight data in each calculation cycle is subjected to a data check operation by using the plurality of check-bit RRAMs, and a multiply-accumulate operation is performed on the low-bit data and the low-bit data of the preset stored data, and a multiply-accumulate operation is performed on the high-bit data after the data check operation and the high-bit data of the preset stored data, so as to obtain a low-bit weight multiply-accumulate result and a high-bit weight multiply-accumulate result, including: determining a plurality of check-bit RRAMs among all RRAMs, and obtaining corresponding check-bit data according to the plurality of check-bit RRAMs; transmitting the high-bit data to a preset check unit, so as to perform an ECC data check operation on the high-bit data by using the check-bit data in the check unit to repair the high-bit data with a preset flip error; sending the high-bit data after the data check operation to a preset high-bit weight multiply-accumulate unit, so as to perform a multiply-accumulate operation on the high-bit data after the data check operation and the high-bit data of the preset stored data in the preset high-bit weight multiply-accumulate unit to obtain a high-bit weight multiply-accumulate result; sending the low-bit data to a preset low-bit weight multiply-accumulate unit, and performing a multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data in the preset low-bit weight multiply-accumulate unit to obtain a low-bit weight multiply-accumulate result.

[0049] It should be noted that, as Figure 3 shown, when the entire row of RRAM is output, the last few RRAMs are used as check-bit RRAMs, and the number of check bits is determined according to 2 m >n, where n is the number of data bits and m is the minimum number of check RRAMs.

[0050] In the actual execution process, the check RRAM of the embodiment of the present application only needs to provide a check code when the high weight bit is output and does not work when the low weight bit is output. Figure 3 There are a total of 11 columns of RRAM. In the first clock cycle, WL<0> is turned on. At this time, all 11 columns of RRAM in the first row output current, and 2-bit data is output through the above SA and ADC modules. The high bit of the 2-bit data enters the 8+3 check module as shown by the black line. This check module can use Hamming code for checking to repair the flipped bits, and then outputs the corrected 8 high-bit data. At the same time, the low-bit data is as Figure 2The blue line part is directly output. At this time, 8 corrected high-bit data and 8 directly output low-bit data are obtained as data[4] and data[0] of 8 8-bit numbers respectively; in the second clock cycle, WL<1> is turned on and WL<0> is turned off. Similarly, 8 8-bit numbers of data[5] and data[1] are output; in the third cycle, the remaining data[6], data[2] and data[7], data[3] are output. Through 4 cycles, two bits of each number are output per cycle, and the high-bit numbers are used for verification protection.

[0051] Thus, the RRAM storage method of the embodiment of the present application enables the RRAM to be used for both high-weight and low-weight storage structures by having ECC verification for high bits, increasing the density of the RRAM and having a greater utilization rate; in addition, the embodiment of the present application reduces the probability of errors in high-weight data through ECC verification of high bits. In the context of large-scale calculations such as neural networks, the output of small weights can be ignored in the result, and only the verification of high weights can balance the accuracy and power consumption of the result.

[0052] In step S104, a preset shift operation is performed on the high-bit weight multiplication-addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and the shifted data and the low-bit weight multiplication-addition result are added to obtain the data multiplication-addition result corresponding to multiple target multi-bit weight data.

[0053] It should be noted that Figure 4 The output calculation structure of the multi-BIT RRAM storage unit is shown. Taking 8 8-bit numbers as an example, the embodiment of the present application can output the low-weight bits to the low-bit weight multiplication-addition module, multiply them one by one with the 8-bit in_low input, store the output result in the accumulator, output the high-bit data to the high-bit weight multiplication-addition module through the verification module, and multiply it by in_high. Since the weight of the high bit is larger, in the 8-bit data, it actually corresponds to data[4], and it needs to be left-shifted by 4 bits through the shift module and then transmitted to the accumulator.

[0054] In the specific implementation process, the embodiment of the present application saves the two multiplication-addition results to the accumulator in the first clock cycle, and performs the same operation in the second clock cycle, storing the low-bit and high-bit results in the accumulator. However, since the results output in the second clock cycle are data[5] and data[1], they need to be left-shifted by one bit inside the accumulator and then added to the original result; the same is true for the next two cycles, which need to be left-shifted by 2 bits and 3 bits respectively and accumulated to the accumulator, thus completing the multiplication-addition output calculation of 8 8-BIT numbers.

[0055] Optionally, in an embodiment of the present application, a preset shift operation is performed on the high-bit weight multiplication and addition result to obtain the shift data of each target multi-bit weight data in each calculation cycle, and the shift data and the low-bit weight multiplication and addition result are added to obtain the data multiplication and addition result corresponding to multiple target multi-bit weight data, including: performing a preset shift operation on the high-bit weight multiplication and addition result in each calculation cycle to obtain the shift data and the displacement number signal corresponding to each calculation cycle; adding the shift data and the low-bit weight multiplication and addition result to obtain the high-low bit addition result, and performing a preset optional displacement operation on the high-low bit addition result according to the displacement number signal corresponding to each calculation cycle to obtain the optional displacement result of each target multi-bit weight data in each calculation cycle; sending the optional displacement result corresponding to each target multi-bit weight data to a preset accumulator to obtain the data multiplication and addition result corresponding to multiple target multi-bit weight data.

[0056] It should be noted that Figure 5 The process of multiplying and adding 8 8-bit numbers is shown. There are a total of 8 data<7:0> data. Since there are 8-bit numbers, the embodiment of the present application requires 4 cycles for calculation, and WL<0>, WL<1>, WL<2>, and WL<3> are separately enabled in the four cycles. In the first cycle, the activation of WL<0> turns on the MOS in the first row, and the RRAM works, outputting the current values of 11 columns. The current of each column is converted into 11 voltages through the SA8+3 module, and the voltages are converted into 11 2-bit data through the ADC. The 2-bit data is output separately. The high bits are used as the high 4 bits of the 8-bit data. The high bits of 13 2-bit numbers are imported into the verification module for verification and 8 verified high-bit data are output. At this time, it is the first cycle, and the high bits correspond to data[4], while the low 4 bits (corresponding to data[0] in the first cycle) directly output the low-bit data of the first 8 columns; since there is no need for verification, the data of the last 3 columns of RRAM does not work when outputting the low bits.

[0057] After that, the embodiment of the present application can import 8 data[4] data into the multiply-accumulate module, multiply and add them with 8 data from in_high. At the same time, the low-bit data data[0] also completes the multiply-accumulate operation. Since data[4] has a higher weight, it needs to be left-shifted by 4 bits, and then added to the multiply-accumulate result of the low-bit data after passing through the module that left-shifts by 4 bits; in the optional shift module, the corresponding weights of data[0] and data[4] are already the corresponding weight data, so the shift number sent by the shift number signal is 0, and the result is stored in the accumulator; in the same way in the second clock cycle, WL<1> is turned on and WL<0> is turned off. At this time, there are 8 data[5] and data[1] data. In the optional shift module, the signal needs to control the overall shift by 1 bit, and then add it to the accumulator, and add it to the result of the first clock cycle, and add it to the results of the subsequent third and fourth cycles. After four cycles, the result of the accumulator is the multiply-accumulate result of 8 8-bit numbers and 8 8-bit in data.

[0058] Thus, in the multi-BIT RRAM storage cell structure of the embodiment of the present application, by separately processing the output of the multi-BIT RRAM and protecting the high bits, the accuracy of the data is protected. Compared with the traditional RRAM full-BIT verification structure, the embodiment of the present application combines the fault tolerance rate of neural network convolution, reduces the power consumption by more than half on the verification module, and balances both the accuracy and the power consumption. Multiple weight data are stored in one RRAM and protected by bit or directly output, so that the multiply-accumulate module is more flexible, the reliability of the data is improved, and the power consumption is effectively reduced.

[0059] According to the digital multi-bit RRAM calculation method for protecting high-weight data proposed in the embodiments of the present application, the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data are determined according to the number of bits of the multiple target multi-bit weight data, and each RRAM is controlled to output multiple columns of current values in each calculation cycle; each column of current values in the multiple columns of current values is converted into two-bit data in the corresponding target multi-bit weight data, and the high-bit data and the low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle are determined for each target multi-bit weight data among the multiple target multi-bit weight data; multiple check-bit RRAMs in all RRAMs are determined, and the multiple check-bit RRAMs are used to perform data check operations on the high-bit data of each target multi-bit weight data in each calculation cycle, and perform multiplication-addition operations on the low-bit data and the low-bit data of the preset stored data, and perform multiplication-addition operations on the high-bit data after the data check operation and the high-bit data of the preset stored data, so as to obtain a low-bit weight multiplication-addition result and a high-bit weight multiplication-addition result; perform a preset shift operation on the high-bit weight multiplication-addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and add the shifted data and the low-bit weight multiplication-addition result to obtain the data multiplication-addition result corresponding to the multiple target multi-bit weight data. The present application can effectively use ECC to check and correct the high bits to improve the calculation accuracy, and at the same time, a RRAM unit can be used for high-BIT and low-BIT storage, increasing the density of the RRAM, thereby realizing the reuse of the RRAM and high-precision output.

[0060] Secondly, a digital multi-bit RRAM calculation device for protecting high-weight data proposed in the embodiments of the present application is described with reference to the accompanying drawings.

[0061] Figure 6 It is a block diagram of a digital multi-bit RRAM calculation device for protecting high-weight data according to an embodiment of the present application.

[0062] As Figure 6 shown, the digital multi-bit RRAM calculation device 10 for protecting high-weight data includes: a control module 100, a conversion module 200, a check module 300, and a calculation module 400.

[0063] Among them, the control module 100 is used to determine the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data according to the number of bits of the multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values in each calculation cycle.

[0064] The conversion module 200 is configured to convert each column of current values in the multi-column current values into two-bit data in the corresponding target multi-bit weight data, and determine the high-bit data and the low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle.

[0065] The verification module 300 is configured to determine multiple verification-bit RRAMs among all the RRAMs, and perform a data verification operation on the high-bit data of each target multi-bit weight data in each calculation cycle by using the multiple verification-bit RRAMs, and perform a multiply-accumulate operation on the low-bit data and the low-order data of the preset stored data, and perform a multiply-accumulate operation on the high-bit data after the data verification operation and the high-order data of the preset stored data, so as to obtain a low-order weight multiply-accumulate result and a high-order weight multiply-accumulate result.

[0066] The calculation module 400 is configured to perform a preset shift operation on the high-order weight multiply-accumulate result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and add the shifted data and the low-order weight multiply-accumulate result to obtain the data multiply-accumulate result corresponding to the multiple target multi-bit weight data.

[0067] Optionally, in an embodiment of the present application, the control module 100 includes: a determination unit, configured to determine the target bit line corresponding to each calculation cycle, and apply a preset voltage to the target bit line to control each RRAM to output multi-column current values in each calculation cycle.

[0068] Optionally, in an embodiment of the present application, the conversion module 200 includes: a generation unit, configured to convert each column of current values into the corresponding target voltage value based on a preset SA structure, and generate two-bit data corresponding to the target voltage value by using a preset digital-to-analog converter.

[0069] Optionally, in an embodiment of the present application, the verification module 300 includes: an acquisition unit, a repair unit, a first multiply-accumulate unit, and a second multiply-accumulate unit.

[0070] Wherein, the acquisition unit is configured to determine multiple verification-bit RRAMs among all the RRAMs, and acquire the corresponding verification-bit data according to the multiple verification-bit RRAMs.

[0071] The repair unit is configured to transmit the high-bit data to a preset verification unit, so as to perform an ECC data verification operation on the high-bit data by using the verification-bit data in the verification unit to repair the high-bit data with a preset flip error.

[0072] The first multiply-accumulate unit is configured to send the high-bit data after the data verification operation to a preset high-weight multiply-accumulate unit, so as to perform a multiply-accumulate operation on the high-bit data after the data verification operation and the high-bit data of the preset stored data in the preset high-weight multiply-accumulate unit, so as to obtain a high-weight multiply-accumulate result.

[0073] The second multiply-accumulate unit is configured to send the low-bit data to a preset low-weight multiply-accumulate unit, and perform a multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data in the preset low-weight multiply-accumulate unit, so as to obtain a low-weight multiply-accumulate result.

[0074] Optionally, in an embodiment of the present application, the calculation module 400 includes: a first shift unit, a second shift unit, and an accumulation unit.

[0075] Wherein, the first shift unit is configured to perform a preset shift operation on the high-weight multiply-accumulate result in each calculation cycle, so as to obtain a shift data and a displacement number signal corresponding to each calculation cycle.

[0076] The second shift unit is configured to add the shift data and the low-weight multiply-accumulate result to obtain a high-low bit addition result, and perform a preset optional shift operation on the high-low bit addition result according to the displacement number signal corresponding to each calculation cycle, so as to obtain an optional shift result of each target multi-bit weight data in each calculation cycle.

[0077] The accumulation unit is configured to send the optional shift result corresponding to each target multi-bit weight data to a preset accumulator, so as to obtain a data multiply-accumulate result corresponding to multiple target multi-bit weight data.

[0078] It should be noted that the foregoing explanation of the embodiments of the digital multi-bit RRAM calculation method for protecting high-weight data also applies to the digital multi-bit RRAM calculation device for protecting high-weight data in this embodiment, and will not be elaborated here.

[0079] A digital multi-bit RRAM computing device for protecting high-weight data according to an embodiment of the present application includes a control module 100, configured to determine the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data according to the number of bits of the multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values in each calculation cycle; a conversion module 200, configured to convert each column of current values in the multiple columns of current values into two-bit data in the corresponding target multi-bit weight data, and determine the high-bit data and the low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle; a verification module 300, configured to determine multiple verification-bit RRAMs in all RRAMs, and perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle by using the multiple verification-bit RRAMs, and perform multiplication and addition operations on the low-bit data and the low-bit data of the preset stored data, and perform multiplication and addition operations on the high-bit data after the data verification operation and the high-bit data of the preset stored data, so as to obtain a low-bit weight multiplication and addition result and a high-bit weight multiplication and addition result; a calculation module 400, configured to perform a preset shift operation on the high-bit weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and add the shifted data and the low-bit weight multiplication and addition result to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data. The present application can effectively use ECC to verify and correct the high bits to improve the calculation accuracy. At the same time, the method of using one RRAM unit for high-BIT and low-BIT storage can increase the density of RRAM, thereby realizing the reuse of RRAM and high-precision output.

[0080] Figure 7 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device may include:

[0081] A memory 701, a processor 702, and a computer program stored on the memory 701 and executable on the processor 702.

[0082] When the processor 702 executes the program, it implements the digital multi-bit RRAM calculation method for protecting high-weight data provided in the above embodiment.

[0083] Further, the electronic device further includes:

[0084] A communication interface 703, configured to communicate between the memory 701 and the processor 702.

[0085] The memory 701 is configured to store a computer program executable on the processor 702.

[0086] The memory 701 may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0087] If the memory 701, the processor 702, and the communication interface 703 are implemented independently, the communication interface 703, the memory 701, and the processor 702 can be interconnected through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0088] Optionally, in a specific implementation, if the memory 701, the processor 702, and the communication interface 703 are integrated on a single chip, the memory 701, the processor 702, and the communication interface 703 can communicate with each other through an internal interface.

[0089] The processor 702 may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0090] The embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above digital multi-bit RRAM calculation method for protecting high-weight data is implemented.

[0091] The embodiments of the present application also provide a computer program product, including a computer program, and when the computer program is executed, it is used to implement the above digital multi-bit RRAM calculation method for protecting high-weight data.

[0092] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0093] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0094] Any process or method description shown in a flowchart or described in other ways herein can be understood to represent a module, segment, or portion of code including one or N executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of this application includes additional implementations, where the functions can be executed in a manner that is not in the order shown or discussed, including in a substantially simultaneous manner or in the reverse order according to the functions involved, which should be understood by those skilled in the art to which the embodiments of this application pertain.

[0095] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion (electronic device) having one or N wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0096] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0097] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0098] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0099] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A digital multi-bit RRAM computing method for protecting high-weight data, characterized in that: The following steps are involved: Determine the number of calculation cycles and the number of RRAMs corresponding to the plurality of target multi-bit weight data according to the number of bits of the plurality of target multi-bit weight data, and control each RRAM to output a plurality of columns of current values ​​in each calculation cycle; Convert each column of current values ​​in the multiple columns of current values ​​into two bits of data in the corresponding target multi-bit weight data, and determine the high bit data and the low bit data in the two bits of data in each calculation cycle for each target multi-bit weight data in the multiple target multi-bit weight data; Determine a plurality of check bit RRAMs in all RRAMs, and use the plurality of check bit RRAMs to perform a data check operation on the high bit data of each target multi-bit weight data in each calculation cycle, and perform a multiplication and addition operation on the low bit data and the low bit data of the preset storage data, and perform a multiplication and addition operation on the high bit data after the data check operation and the high bit data of the preset storage data, so as to obtain a low bit weight multiplication and addition result and a high bit weight multiplication and addition result; A preset shift operation is performed on the high-order weight multiplication and addition result to obtain the shift data of each target multi-bit weight data in each calculation cycle, and the shift data and the low-order weight multiplication and addition result are added to obtain the data multiplication and addition results corresponding to the multiple target multi-bit weight data.

2. The method according to claim 1, characterized in that The method of controlling each preset RRAM to output multiple columns of current values ​​in each calculation cycle includes: A target bit line corresponding to each calculation cycle is determined, and a preset voltage is applied to the target bit line to control each RRAM to output the multiple columns of current values ​​in each calculation cycle.

3. The method according to claim 1, characterized in that The converting each column of the multiple columns of current values ​​into two-bit data in the corresponding target multi-bit weight data includes: Based on the preset SA structure, each column current value is converted into a corresponding target voltage value, and a preset digital-to-analog converter is used to generate two-bit data corresponding to the target voltage value.

4. The method according to claim 3, characterized in that The method of determining a plurality of check bit RRAMs in all RRAMs, and using the plurality of check bit RRAMs to perform a data check operation on the high bit data of each target multi-bit weight data in each calculation cycle, and performing a multiplication and addition operation on the low bit data and the low bit data of the preset storage data, and performing a multiplication and addition operation on the high bit data after the data check operation and the high bit data of the preset storage data to obtain a low bit weight multiplication and addition result and a high bit weight multiplication and addition result, includes: Determine the plurality of check bit RRAMs among all the RRAMs, and obtain corresponding check bit data according to the plurality of check bit RRAMs; The high-bit data is transmitted to a preset check unit, so that the high-bit data is subjected to an ECC data check operation by using the check bit data in the check unit, so as to repair the high-bit data with a preset flip error; The high-bit data after the data verification operation is sent to a preset high-bit weight multiplication and addition unit, so that the high-bit data after the data verification operation and the high-bit data of the preset storage data are multiplied and added in the preset high-bit weight multiplication and addition unit to obtain the high-bit weight multiplication and addition result; The low-bit data is sent to a preset low-bit weight multiplication-addition unit, and a multiplication-addition operation is performed on the low-bit data and the low-bit data of the preset storage data in the preset low-bit weight multiplication-addition unit to obtain a low-bit weight multiplication-addition result.

5. The method according to claim 4, characterized in that The performing of a preset shift operation on the high-order weight multiplication and addition result to obtain the shift data of each target multi-bit weight data in each calculation cycle, and adding the shift data and the low-order weight multiplication and addition result to obtain the data multiplication and addition results corresponding to the multiple target multi-bit weight data, including: Performing a preset shift operation on the high-order weight multiplication and addition result in each calculation cycle to obtain shift data and a shift number signal corresponding to each calculation cycle; Adding the shifted data and the low-bit weight multiplication and addition result to obtain a high- and low-bit addition result, and performing a preset optional shift operation on the high- and low-bit addition result according to the displacement number signal corresponding to each calculation cycle to obtain an optional shift result of each target multi-bit weight data in each calculation cycle; The optional shift result corresponding to each target multi-bit weight data is sent to a preset accumulator to obtain the data multiplication and addition results corresponding to the multiple target multi-bit weight data.

6. A digital multi-bit RRAM computing device for protecting high-weight data, characterized in that: include: A control module, configured to determine the number of calculation cycles and the number of RRAMs corresponding to the plurality of target multi-bit weight data according to the number of bits of the plurality of target multi-bit weight data, and control each RRAM to output a plurality of columns of current values ​​in each calculation cycle; A conversion module, used for converting each column of current values ​​in the multiple columns of current values ​​into two bits of data in the corresponding target multi-bit weight data, and determining the high bit data and the low bit data in the two bits of data for each target multi-bit weight data in each calculation cycle; A verification module, used to determine a plurality of verification bit RRAMs in all RRAMs, and use the plurality of verification bit RRAMs to perform a data verification operation on the high-bit data of each target multi-bit weighted data in each calculation cycle, and perform a multiplication-addition operation on the low-bit data and the low-bit data of the preset stored data, and perform a multiplication-addition operation on the high-bit data after the data verification operation and the high-bit data of the preset stored data, so as to obtain a low-bit weight multiplication-addition result and a high-bit weight multiplication-addition result; A calculation module is used to perform a preset shift operation on the high-order weight multiplication and addition results to obtain the shift data of each target multi-bit weight data in each calculation cycle, and add the shift data and the low-order weight multiplication and addition results to obtain the data multiplication and addition results corresponding to the multiple target multi-bit weight data.

7. The device according to claim 6, characterized in that The control module comprises: The determination unit is used to determine the target bit line corresponding to each calculation cycle, and apply a preset voltage to the target bit line to control each RRAM to output the multiple columns of current values ​​in each calculation cycle.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the digital multi-bit RRAM computing method for protecting high-weight data as described in any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the digital multi-bit RRAM computing method for protecting high-weight data as described in any one of claims 1 to 5.

10. A computer program product, comprising a computer program, characterized in that The computer program is executed to implement the digital multi-bit RRAM computing method for protecting high-weight data as described in any one of claims 1 to 5.

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