Built-in self-test circuit and method for ILV fault location optimization in 3D IC

Abstract

The invention belongs to the technical field of integrated circuit design and test, and discloses a built-in self-test circuit and method for ILV fault positioning optimization in a 3D IC, and the circuit comprises a BIST mode generation module, a signal transmission module, a fault capturing module, and a fault positioning module. The ILV fault can be efficiently detected and positioned by generating test modes for different fault types, controlling one-way propagation of signals and scanning and capturing fault signals. The method is suitable for high-density irregular ILV layout, extra test ports are not needed, compared with a traditional test method, the method is short in test time and high in fault positioning precision, meanwhile, consumption of hardware resources is reduced, and the reliability and production efficiency of a 3D integrated circuit are further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design and testing, and specifically relates to a built-in self-test circuit and method for optimizing ILV fault location in 3D ICs. Background Art

[0002] With the continuous progress of integrated circuit technology, especially the breakthrough of 3D integrated circuit technology, the performance and integration density of chips have been significantly improved. Three Dimensional Integrated Circuit (3D IC) stacks multiple transistor layers vertically, which not only greatly reduces the physical footprint of the chip, but also improves its computing power, bandwidth, and power consumption efficiency, greatly promoting the development of fields such as smart devices, data centers, and high-performance computing. However, with the wide application of 3D IC technology, the challenges in design, manufacturing, testing, etc. are increasing, especially in the field of ILV design and fault detection.

[0003] Inter Layer Via (ILV) is an important part of the inter-layer circuit interconnection in 3D ICs, responsible for the electrical signal transmission between different circuit layers. With the increase in integration density, the number and density of ILVs have increased sharply, which also means that these connection paths are more vulnerable to manufacturing defects, process variations, aging, and other factors. Specifically, ILV faults may manifest as open circuits, short circuits, delay faults (such as increased delay due to resistance changes), etc. If these faults cannot be detected and repaired in time, it will lead to abnormal circuit function, performance degradation, and even complete chip failure. Due to the high density and complex layout of 3D ICs, how to effectively detect and locate these faults throughout the chip has become a major challenge in integrated circuit design.

[0004] Most traditional fault detection methods rely on built-in self-test technology, which self-checks the chip by embedding a self-test module in the chip. The built-in self-test (BIST) structure can quickly identify fault points during the design and production processes and help locate the fault positions. However, with the increasing complexity of the ILV layout in 3D ICs, existing BIST methods have encountered multiple problems in practical applications. First, the irregular ILV layout makes fault location more difficult. Especially in the case of a large number of cross-layer connections and complex interconnection paths, traditional BIST methods are difficult to effectively identify the fault source and accurately locate the problematic ILV. Second, traditional BIST methods usually require multiple rounds of test iterations. Especially when facing multiple potential fault points, each iteration tests multiple ILVs, which not only increases the time overhead of the test but also results in a large consumption of hardware resources, greatly affecting the test efficiency and increasing the production cost. In addition, the traditional BIST architecture also faces problems of redundant paths and short circuits in the routing design of multi-instantiated modules. In multi-instantiated modules, the same template module may cause short circuits or violate design rules due to path redundancy. These problems are usually difficult to effectively solve in the traditional BIST architecture because the traditional method cannot effectively optimize these redundant paths, resulting in a large number of useless test results during the test process, wasting valuable resources and time. Moreover, with the increase in the design scale of 3D ICs, the increase in the number and complexity of ILVs makes it difficult to effectively guarantee the test coverage and accuracy. Traditional BIST methods have poor adaptability to high-density ILV layouts and cannot ensure that all potential faults can be effectively detected and located while guaranteeing the test efficiency. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a built-in self-test circuit and method for ILV fault location optimization in 3D ICs. Through an improved BIST architecture, the accuracy and efficiency of fault detection are improved, the consumption of hardware resources and test time are reduced, and accurate fault location in high-density ILV layouts is achieved.

[0006] A built-in self-test circuit for ILV fault location optimization in 3D ICs according to the present invention is used to detect an M×N group of ILVs to be tested array between the logic layer and the memory layer of a single-chip three-dimensional integrated circuit, and includes a BIST pattern generation (BISTPattern Generation) module, a signal transmission (Signal Transmission) module, a fault capture (FaultCapture) module, and a fault location (Fault Location) module. Among them, the BIST pattern generation module is responsible for generating test patterns for different fault types to detect different types of ILV faults; The signal transmission module is responsible for stably transmitting the test signal to the fault capture module; The fault capture module synchronously analyzes the response signals from multiple ILVs and transmits the test results to the fault location module; The fault location module uses the scan chain mechanism to accurately locate and store the detected faults, ensuring that the fault information can be used for chip modification or debugging in subsequent stages.

[0007] Furthermore, the BIST pattern generation module includes a finite state machine FSM and a multiplexer MUX; the finite state machine FSM receives an external test enable signal ST and a dedicated test clock, and sets the built-in self-test circuit to the test mode; in the test mode, the FSM generates various test control signals to ensure the operation of the built-in self-test circuit; each multiplexer MUX corresponds to an ILV under test, and the inputs of the MUX are respectively connected to the normal logic signal (functional path) and the test signal (test path) generated by the FSM; when the external controller issues a test enable signal, i.e., ST = 1, the MUX switches the input of the ILV to the test mode, and the TS test sequence driven by the FSM is injected into the ILV.

[0008] Furthermore, the signal transmission module includes the ILV under test and four groups of independent tri-state gates. The tri-state gates include two groups of test transmission tri-state gates and two groups of functional transmission tri-state gates, and the four groups of independent tri-state gates are added to both sides of the ILV under test; among them, UP is the control signal of the test transmission tri-state gate, EN is the control signal of the functional transmission tri-state gate, the input of the bottom test transmission tri-state gate is connected to the multiplexer MUX that selects the ILV under test, and the output is connected to the ILV under test. The input of the top test transmission tri-state gate is connected to the ILV under test, and the output is connected to the combinational logic network of the fault capture module; FI and FO are the inputs and outputs in the functional mode.

[0009] For the upstream ILV, the signal itself propagates from bottom to top in the functional mode, so the test and functional transmission tri-state gates can be placed in the same direction; for the downstream ILV under test, the signal propagates from top to bottom in the functional mode. At this time, the test and functional tri-state gates are placed in the opposite direction, so that the test signal can propagate from bottom to top in the test mode. For each ILV under test, after the FSM receives the test instruction, the signal UP = 1 and EN = 0 are set, the test transmission path is opened, the functional transmission path is closed, and the data transmission directions of the upstream and downstream MIVs in the original functional mode are both changed to propagate from bottom to top.

[0010] Further, the fault capture module includes an XOR-OR combined logic network and a data selector MUX; the XOR-OR combined logic network consists of two layers of logic: the first layer is an exclusive-OR gate XOR array for detecting short circuits between adjacent ILVs; the second layer is an OR gate array for integrating the output results of the exclusive-OR gates and generating a fault flag; each ILV signal is connected to the input pin of the XOR-OR combined logic network through the MUX; if the number of input pins (i.e., the width of the XOR-OR combined logic network) is n, usually a power of 2, i.e., n = 2^k, where k is a non-negative integer, generally depending on the number of ILVs to be tested in each group; then the ILV signals corresponding to adjacent pins (such as pin i and pin , where i is a value less than n) will be input into an exclusive-OR gate.

[0011] When a short circuit occurs between adjacent ILVs, their signals will remain the same in the test mode (due to driving complementary signals), resulting in the output of the exclusive-OR gate being logic 0; the outputs of all exclusive-OR gates are further connected to the OR gates, and the outputs of adjacent two exclusive-OR gates are used as the inputs of one OR gate. For example, the outputs of exclusive-OR gates Xi and are connected to the OR gate . This design enables the short circuit faults of any adjacent ILV pair to be captured by at least one OR gate. After the fault detection is completed, the FSM controls the fault capture module to store the fault information into the scan chain and uses the asynchronous capture mechanism to store the fault data, so as to reduce the consumption of hardware resources and improve the test efficiency. Through the XOR-OR structure, the fault detection module can store the fault information with very few bits and transfer it to the fault location module to perform subsequent fault location operations.

[0012] Further, the fault location module introduces a scan chain mechanism to improve the detection and location capabilities of ILVs defects, including scan flip-flops (Scan Flip-Flop, SFF) and logic AND gates; multiple SFFs are connected in series to form a scan chain, and each SFF is connected to the output terminal of the OR gate in the XOR-OR combined logic network corresponding to a pair of ILVs and its corresponding fault capture module. If there is a difference in the transmission delays of two ILVs (indicating that one of them has a resistive open circuit or short circuit defect), the XOR-OR combined logic network will output a low-level pulse, and this output is combined with the scan chain clock signal Scan CLK through a logic AND gate to the clock input CK of the corresponding SFF. And in order to isolate the interference of the scan chain clock signal Scan CLK in the capture mode, it is combined with the Scan CLK signal through a logic AND gate to ensure that only in the scan mode is the clock signal allowed to drive this pulse connected to the clock input (CK) of the corresponding SFF, while the data input (D terminal) of the SFF is fixed to logic "0".

[0013] Furthermore, the operation mode of the scan chain is divided into a capture mode and a scan mode; when in the capture mode (SE = 0), the input selector locks the D terminal to ground low level, the logic AND gate isolates the scan chain clock signal, and at this time the XOR-OR logic network directly drives the CK terminal of the corresponding SFF; if there is a fault in the circuit, the XOR-OR combinational logic network generates a low-level pulse to trigger the SFF, forcing its output to maintain a low-level state, forming a stable fault mark; when switched to the scan mode (SE = 1), the input selection SIN terminal of the SFF, the output terminal of the XOR-OR returns to high level, and at this time the scan clock Scan CLK directly drives the SFF; at this time, all the latched fault data are sequentially transmitted along the scan chain, and finally complete ILVs fault information is generated at the system output terminal.

[0014] The present invention also provides a built-in self-test method for ILV fault location optimization in 3D ICs, which is implemented based on the above-mentioned built-in self-test circuit, and includes the following steps: Step 1, in the functional mode, the BIST mode generation module receives the external test enable signal ST and sets the built-in self-test circuit to the test mode; Step 2, the BIST mode generation module configures the FSM to ensure that the test vectors can be correctly applied to the ILV to be tested, and places the scan chain structure in the fault location module in the ready state to receive and analyze the test response; Step 3, within any one clock cycle, dynamically allocate ILVs to the input pins of the signal transmission module in different test iterations, so as to gradually complete the detection of all possible short circuits; Step 4, the FSM generates a tri-state gate control signal and sends it to the control end of the tri-state gate in the signal transmission module respectively, to ensure that the upstream or downstream ILVs can propagate signals in the same direction in the test mode; Step 5, the XOR-OR network in the fault capture module compares the test signals to determine whether a fault occurs; Step 6, the fault location module uses an asynchronous capture mechanism through the scan chain to detect ILV defects; Step 7, after the test is completed, the FSM decides whether to continue the test according to the fault detection result of the scan chain; if all ILVs are fault-free, the FSM generates a test completion signal and controls the BIST system to exit the test mode and restore the normal functional mode; if a fault is detected, the FSM continues to perform fault masking, iterative testing, and data storage operations to ensure that all ILV faults can be accurately detected and located; Step 8, when all test iterations are completed, the BIST system returns to the functional mode and stores the test data in the system fault log.

[0015] The beneficial effects of the present invention are: (1)Efficient fault detection and location: Through the asynchronous capture and serial scan output of the scan chain mechanism, the present invention can effectively identify various fault types (such as open circuit, short circuit, delay, etc.), and can accurately capture fault signals in high-density and complex ILV layouts; Through the design of the scan chain, after a fault occurs, the corresponding fault signal is quickly recorded and gradually transmitted through the scan chain, enabling the test system to efficiently process fault information from multiple test points. This solution is particularly suitable for 3D ICs with complex connections and multiple fault points, and can accurately locate multi-layer faults in a short time; (2)Improve test efficiency and reliability: The present invention significantly improves the efficiency and reliability of ILV testing through the XOR-OR combined logic network; This network realizes high-sensitivity detection of short-circuit faults through the complementary signal driving strategy of adjacent ILVs. When the signals of any two adjacent ILVs are the same due to a short circuit, the XOR gate outputs logic 0, and the OR gate triggers a fault flag to ensure the rapid capture of fault signals. Compared with traditional scan chains or complex test circuits, this network only requires a linear number of logic gates (such as n + 1 XOR gates and n OR gates for n ILVs), with extremely low hardware overhead; In addition, the network supports full parallel operation, and can cover the short-circuit detection of all adjacent ILV pairs within a single test cycle, without bit-by-bit scanning or multiple iterations; (3)Meet the test requirements of high-density and irregular ILV layouts: Different from traditional methods that assume ILVs are arranged in one dimension, the present invention optimizes for the irregular layouts of ILVs in 3D integrated circuits and can efficiently handle faults of irregularly arranged ILVs; The signal transmission module controls the signal flow direction design through a tri-state gate structure to achieve precise detection of cross short circuits between up and down ILV, filling the core blind spot of traditional test technologies; The signal transmission module designed in the present invention forces the signal flow directions of up and down ILVs to be consistent in the test mode. For example, it reverses the logical connection of the down ILV so that it transmits complementary signals in the same direction as the up ILV during testing. This method performs particularly well in actual M3D layouts and can provide more accurate test and diagnostic solutions for complex design rules. Brief Description of the Drawings

[0016] Figure 1 It is the test circuit diagram of ILVs between the upper and lower Dies of the 3D IC in the present invention; Figure 2 It is the tri-state gate structure in the signal transmission module; Figure 3 It is the scan chain structure in the fault location module; Figure 4 It is the flow chart of the method described in the present invention; Figure 5 It is the schematic diagram of the test process; Figure 6 The barrier-free waveform of the embodiment in the present invention; Figure 7 The SAF fault waveform of the embodiment in the present invention; Figure 8 The short-circuit fault waveform of the embodiment in the present invention. Specific embodiments

[0017] In order to make the content of the present invention easier to be clearly understood, the following further describes the present invention in detail according to specific embodiments and in conjunction with the accompanying drawings.

[0018] In this embodiment, the BIST circuit of the present invention is arranged between the upper and lower layers of Dies (bare chips) of the 3D IC, as Figure 1 shown, with four ILVs to be tested. The entire test circuit includes four core modules: a BIST mode generation module, a signal transmission module, a fault capture module, and a fault location module. The BIST mode generation is responsible for coordinating the entire test process, including the switching of test modes, the control of test sequences, the management of test processes, and the generation of multiple test modes to ensure that different types of ILV faults can be detected, and redundant test vectors are reduced through optimized test sequences to improve test efficiency. The signal transmission module ensures that test signals can be stably transmitted to the ILV to be tested and guarantees the unidirectional propagation of signals during the test process to avoid signal interference. The fault capture module synchronously analyzes the response signals from multiple ILVs through an XOR-OR logic network and transfers the test results to the fault location module. The fault location module uses the scan chain mechanism to accurately locate the detected faults and stores them to ensure that the fault information can be used for chip repair or debugging in subsequent stages.

[0019] The BIST mode generation module is composed of a finite state machine FSM and the ILVs to be tested. Among them, the FSM controls the operation logic of the entire BIST circuit and generates a series of key test signals. These signals include a test start signal (ST) and a dedicated test clock (CLK). ST and CLK enter the finite state machine FSM controller, generating various control signals, including a test sequence TS={T0=1,T1=0,T2=1} composed of three 1-bit test modes, the switching signal of the tri-state gate in the data transfer device, and the enable signal SE, scan chain clock signal Scan CLK, system reset signal Reset, etc. used in the scan chain of the fault location module. The task of the FSM is to manage the entire test process, ensure that test data can be transmitted to each module according to the set process, and coordinate the application of test vectors, the acquisition of test data, and the execution of fault location.

[0020] During the application phase of the test vectors, the FSM controls the test vector generation module to generate a test sequence TS = {T0 = 1, T1 = 0, T2 = 1} of three 1-bit test patterns and applies it to the ILV under test; the FSM generates a clock signal CLK to ensure that the test vectors can be correctly input into the ILV. In different test iterations, the test system alternately applies the test vector Ti and its inverted signal Tī to cover all possible short circuit, SAF, and delay fault conditions. The signal transmission module is responsible for ensuring stable and unidirectional transmission to the fault capture module during this phase. To support parallel testing of multiple ILVs, the test system dynamically allocates ILVs to the input pins of the XOR-OR combinational logic network through a digital selector MUX to improve test efficiency.

[0021] Figure 2 For one of the tri-state gate connection structures in the signal transmission module, when the built-in self-test circuit receives the test start signal "ST = 1", the FSM generates the test transmission tri-state gate UP and the functional transmission tri-state gate control signal EN. For each ILV under test, "UP = 1", "EN = 0", the test transmission path is opened, the functional transmission path is closed, and the data of the upstream and downstream ILVs are transmitted in the same direction.

[0022] After the test signal propagates to the ILV, the fault capture module will perform real-time comparison and analysis on the test signal to determine whether a fault has occurred. This module uses an XOR-OR combinational logic network to quickly detect whether there are abnormalities in the ILV. If all ILVs are working properly, the output of the XOR gate is always "1", and the output of the OR gate also remains "1". However, if a certain ILV fails, some outputs of the XOR gate will become "0", which in turn affects the output of the OR gate, making the signal at the corresponding position also become "0", thus successfully detecting the existence of the fault. After the fault detection is completed, the FSM controls the fault capture module to store the fault information in the scan chain and uses an asynchronous capture mechanism to store the fault data to reduce the consumption of hardware resources and improve test efficiency. Through the XOR-OR structure, the fault detection module can store the fault information with very few bits and transfer it to the fault location module to perform subsequent fault location operations.

[0023] In the fault location module, a scan chain mechanism is introduced to improve the detection and location capabilities of ILVs defects. Through the XOR-OR structure, when there are short circuit, open circuit, or delay defects in the ILVs, the output of the XOR-OR structure will generate a low-level pulse, indicating the existence of a fault; this fault signal will further trigger the scan flip-flop (Scan Flip-Flop, SFF) in the scan chain, causing it to store the error indication information and latch the fault status for subsequent fault analysis and location.

[0024] Figure 3 This is the specific way in which the scan chain is connected to the fault capture module. It can be seen that the clock input of each SFF is controlled by the output of the XOR-OR structure and is simultaneously controlled by the scan clock (Scan CLK) and the scan enable signal (SE). In the capture mode (i.e., the test mode), the scan enable signal SE = 0. At this time, the input selection D terminal of the SFF is used as the input, and the scan clock signal is isolated by the AND gate, so that the XOR-OR structure drives the clock input CK of the SFF. Therefore, the low pulse at the output end of the XOR-OR structure combined with the logic of the AND gate triggers the SFF as an error indication and sets its output to low level because the D input is always grounded at low level. The low-level pulse of the XOR-OR structure will trigger the SFF as a clock signal, keeping its output low level, indicating that a fault has been detected. This method ensures that the fault information can be stably recorded without being lost due to test clock skew or other factors. In the scan mode (SE = 1), the input selection of the SFF is the SIN terminal. At this time, the test clock generator is turned off, and the output of the XOR-OR structure returns to high level. The scan clock Scan CLK drives the SFF so that the stored error information can be sequentially shifted out through the scan chain for further analysis. At the end of the scan mode, the outputs of all SFFs are sequentially transmitted to the final output terminal of the system, thereby obtaining the complete ILVs fault distribution information.

[0025] After fault location is completed, the FSM controls the scan chain to update the fault information and continues to execute test iterations until the tests for all ILVs are completed. When all test iterations are completed, the FSM generates a test completion signal and stores the fault detection data in the system fault log for subsequent debugging and chip repair. At the same time, the FSM controls the BIST circuit to return to the functional mode to ensure the normal operation of the chip.

[0026] In this example, a built-in self-test method for ILV fault location optimization in 3D ICs, as Figure 4 and Figure 5 shown, includes the following steps: Step 1: In the functional mode, the finite state machine FSM receives the external test enable signal "ST = 1", sets the built-in self-test circuit to the test mode; the finite state machine FSM enters the test state and generates the test transfer tri-state gate and functional transfer tri-state gate control signals; for each ILV to be tested, the test transfer path is opened, the functional transfer path is closed, and the data of the upstream and downstream ILVs are transmitted in the same direction; Step 2: The BIST mode generation module generates a test sequence TS = {T0 = 1, T1 = 0, T2 = 1} consisting of three 1-bit test modes; Step 3: Within one clock cycle, Ti and its inverted signal are sent to the test mode input terminal of the data selector MUX. The output of the MUX is connected to the group of ILVs under test. The selection line of the MUX switches the switch to the BIST working mode. The inverted signals are cross-input to Is0, I1, I2, I3, where I0 and I2 receive Ti, and I1 and I3 are inverted. The input waveforms are as Figure 6 shown; Step 4: The FSM generates tri-state gate control signals and sends them to the control terminals of four groups of tri-state gates respectively to ensure that the ILVs in the up or down direction can propagate signals in the same direction in the test mode; Step 5: The BIST system dynamically allocates ILVs to the input pins of the fault capture module through the selector MUX, thereby gradually completing the detection of all possible faults. In this test, there is only one group of ILVs. Therefore, this MUX part can be ignored; Step 6: The fault capture module establishes an XOR-OR combinational logic network to compare and analyze the test signals to determine whether a fault occurs; if all ILVs work normally, the output of the XOR gate is always "1", and the output of the OR gate also remains "1"; when a fault exists, some outputs of the XOR gate will become "0", which in turn affects the output of the OR gate, and the corresponding output will also become "0"; Step 7: The fault location module uses an asynchronous capture mechanism through the scan chain to detect ILV defects; at this time, SE = 0 causes SE to enter the capture mode; Step 8: After the test is completed, the FSM decides whether to continue the test according to the fault detection results of the scan chain; in this embodiment, since there is only one group of ILVs, the test is directly ended; when all tests are completed, the BIST system returns to the functional mode, sets the scan chain SE = 1 to enter the scan mode, and outputs the fault information through the scan chain.

[0027] After the above steps are completed, the input and output waveforms of this embodiment are simulated through simulation software. CLK is the system clock. When the rising edge of CLK comes, the values of Ti and ~Ti change, 1 becomes 0, and 0 becomes 1. Clka is the clock set for the scan chain, which is four times that of CLK. O[i] is the value output through the XOR-OR structure, and Sout is the sequence output by the scan chain after the test is completed. As Figure 5 shown, it is the waveform generated by the normal test without faults in this embodiment. It can be found that all the fault information generated after passing through the test circuit is 1, indicating that no faults occur.

[0028] Apply a stuck-at-1 fault to IVL1 and a stuck-at-0 fault to IVL2. After simulation, as Figure 7As shown, when Ti = 1 is applied, the waveform outputs a fault message 0 for O[1] and O[2], and the corresponding Sout also outputs 0, thereby locating the faults of IVL1 and IVL2.

[0029] A short - circuit fault is applied to IVL2 and IVL3 for testing. As Figure 8 shown, it can be found that for O[2], the output value is constantly 0, and the corresponding Sout also outputs a fault message of 0, indicating that the fault can be located at IVL2, thereby determining the short - circuit fault between IVL2 and IVL3.

[0030] The optimized BIST structure of the present invention significantly improves the test efficiency and fault coverage rate of ILV in 3D ICs by improving the test sequence, optimizing the signal transmission path, and introducing efficient fault capture and location methods. At the same time, it reduces the hardware resource overhead and test time, enabling it to be applicable to the in - line test and production test scenarios of high - density M3D ICs. The BIST system of the present invention can achieve efficient and low - power ILV fault detection and ensure 100% short - circuit fault coverage rate, providing an efficient and reliable solution for the testing of future high - integration 3D ICs.

[0031] The above description is only the preferred solution of the present invention and is not intended as a further limitation of the present invention. All equivalent changes made by using the content of the specification and drawings of the present invention are within the protection scope of the present invention.

Claims

1. A built-in self-test circuit for optimizing ILV fault location in 3D IC, characterized in that: It includes BIST pattern generation module, signal transmission module, fault capture module and fault location module. The BIST pattern generation module is responsible for generating test patterns for different fault types to detect different types of ILV faults; The signal transmission module is responsible for stably transmitting the test signal to the fault capture module; The fault capture module synchronously analyzes the response signals from multiple ILVs and transmits the test results to the fault location module; The fault location module uses a scan chain mechanism to accurately locate and store the detected faults.

2. A built-in self-test circuit for ILV fault location optimization in 3D IC according to claim 1, characterized in that: The BIST pattern generation module includes a finite state machine FSM and a data selector MUX; The finite state machine FSM receives an external test enable signal ST and a dedicated test clock, and sets the built-in self-test circuit to be in a test mode; In the test mode, the FSM generates various test control signals to ensure the operation of the built-in self-test circuit; Each data selector MUX corresponds to an ILV to be tested, and the input of the MUX is connected to a normal logic signal and a test signal generated by the FSM respectively.

3. A built-in self-test circuit for ILV fault location optimization in 3D IC according to claim 2, characterized in that: The signal transmission module includes an ILV to be tested and four groups of independent three-state gates, wherein the three-state gates include two groups of test transmission three-state gates and two groups of function transmission three-state gates, and the four groups of independent three-state gates are added to both sides of the ILV to be tested; Among them, UP is the control signal of the test transmission tri-state gate, and EN is the control signal of the functional transmission tri-state gate; the input of the test transmission tri-state gate at the bottom is connected to the data selector MUX that selects the ILV to be tested, and the output is connected to the ILV to be tested; the input of the test transmission tri-state gate at the top is connected to the ILV to be tested, and the output is connected to the combinational logic network of the fault capture module; FI and FO are the input and output in the functional mode.

4. A built-in self-test circuit for ILV fault location optimization in 3D IC according to claim 3, characterized in that: The fault capture module includes an XOR-OR combinational logic network and a data selector MUX; The XOR-OR combinational logic network is composed of two layers of logic: the first layer is an XOR array of XOR gates, which is used to detect short circuits between adjacent ILVs; the second layer is an OR array of OR gates, which is used to integrate the output results of the XOR gates and generate fault flags; Each ILV signal is connected to the input pin of the XOR-OR combinational logic network through a MUX; the number of input pins is n, that is, n=2^k, where k is a non-negative integer, then the ILV signals corresponding to two adjacent pins will be input into an XOR gate; When a short circuit occurs between adjacent ILVs, the signals of both will remain the same in the test mode, resulting in the XOR gate output being logic 0; The outputs of all XOR gates are further connected to an OR gate, and the outputs of two adjacent XOR gates serve as the inputs of an OR gate.

5. A built-in self-test circuit for ILV fault location optimization in 3D IC according to claim 4, characterized in that: The fault location module introduces a scan chain mechanism, including a scan trigger SFF and a logic AND gate; Multiple SFFs are connected in series to form a scan chain. Each SFF is connected to a pair of ILVs and the output end of the OR gate in the XOR-OR combinational logic network in the corresponding fault capture module. If there is a difference in the transmission delay of the two ILVs, the XOR-OR combinational logic network will output a low-level pulse, which is combined with the scan chain clock signal Scan CLK through a logic AND gate to the clock input CK of the corresponding SFF; and in order to isolate the interference of the scan chain clock signal Scan CLK in the capture mode, it is combined with the Scan CLK signal through a logic AND gate to ensure that the clock signal is allowed to drive the SFF only in the scan mode, and the data input of the SFF, that is, the D end, is fixed to logic "0".

6. A built-in self-test circuit for ILV fault location optimization in 3D IC according to claim 5, characterized in that: The operation mode of the scan chain is divided into a capture mode and a scan mode; When in capture mode, that is, the scan chain enable signal SE=0, the logic AND gate isolates the scan chain clock signal. At this time, the XOR-OR combinational logic network will directly drive the CK end of the corresponding SFF. If there is a fault in the circuit, the XOR-OR combinational logic network will generate a low-level pulse to trigger the SFF, forcing its output to maintain a low-level state, forming a stable fault mark; when switched to scan mode, that is, SE=1, the scan clock Scan CLK directly drives the SFF; at this time, all latched fault data are transmitted in sequence along the scan chain, and finally generate complete ILVs fault information at the system output end.

7. A built-in self-test method for optimizing ILV fault location in 3D IC, characterized in that: The built-in self-test circuit according to any one of claims 1 to 6 is implemented, comprising the following steps: Step 1: In the functional mode, the BIST mode generation module receives an external test enable signal ST and sets the built-in self-test circuit to the test mode; Step 2: The BIST pattern generation module configures the FSM to ensure that the test vectors can be correctly applied to the ILV to be tested, and puts the scan chain structure in the fault location module into a ready state to receive and analyze the test response; Step 3: In any clock cycle, dynamically assign ILV to the input pins of the signal transmission module in different test iterations, so as to gradually complete the detection of all possible short circuits; Step 4: FSM generates a three-state gate control signal and sends it to the control end of the three-state gate in the signal transmission module, so that the uplink or downlink ILV can propagate the signal in the same direction in the test mode; Step 5: The XOR-OR combinational logic network in the fault capture module compares the test signal to determine whether a fault occurs; Step 6: The fault location module records the ILV defect in the capture mode through the scan chain; Step 7: After the test is completed, the FSM decides whether to continue the test based on the fault detection results of the scan chain; if all ILVs are fault-free, the FSM generates a test completion signal and controls the BIST system to exit the test mode and resume the normal functional mode; if a fault is detected, the FSM continues to perform fault masking, iterative testing, and data storage operations to ensure that all ILV faults can be accurately detected and located; Step 8: When all test iterations are completed, the BIST system returns to the functional mode and stores the test data in the system fault log.

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