Patch repair method and device for read-only code and storage medium

Abstract

The embodiment of the invention discloses a read-only code patch repairing method and device and a storage medium, and relates to the field of embedding. According to the method, the read-write request on the system bus is monitored, so that all-bus patch coverage of any code / data is realized. According to the patch repairing device, the patch pool containing various kinds of information is preset, and when a read-write request of a specific address is detected, corresponding patch data items can be quickly inquired and matched. And if the matching is successful and the patch is valid, replacing the target data according to the patch type or triggering a CPU exception instruction to enter an interrupt processing flow to obtain the patch. The method is universal and flexible, supports undifferentiated full-function patches, can cope with various code / data errors, and greatly reduces the risk of chip scrapping or re-burning caused by ROM code abnormity. By means of bus replacement, abnormal triggering and the like, effective repair of read-only codes is achieved, remarkable economic effects are achieved, production efficiency is improved, and product cost is reduced.

Description

Technical Field

[0001] This application relates to the field of embedded systems, and particularly to a method, apparatus, and storage medium for patching read-only code. Background Art

[0002] In the development of embedded systems, as the core component, the choice of the code carrier of the processor chip is crucial. Common code carriers include ROM (Read-Only Memory), OTP (One-Time Programmable Memory), MTP (Multiple-Time Programmable Memory), SPI FLASH, and NAND FLASH, etc. These storage media have their own characteristics, but the common point is that they all carry the startup code and application code of the embedded system. Among them, the startup code is usually built in by the chip manufacturer and stored in the ROM to ensure that the initialization operation can be automatically executed when the system is powered on. For the application code, due to its functional complexity and space requirements, it is often stored in the larger-capacity OTP or even ROM, especially for low-cost solutions.

[0003] However, a significant drawback of these storage media is their read-only property. Once the code is written, it cannot be modified unless special physical means (such as MetalFix light repair) are used. This means that if there are errors or vulnerabilities in the code, it will cause great trouble to developers. Especially in large-scale production, code errors in a certain batch of chips may lead to the scrapping of the entire batch, causing huge economic losses.

[0004] To address this issue, the industry has explored some code patching solutions. One such solution is to predict the code segments or functions that are likely to have problems and preset function pointers at these positions. When patching is required, by modifying the value of the function pointer, it is made to jump to the patch code for execution, thereby achieving code repair. Although this solution solves the code patching problem to a certain extent, it requires developers to have a deep understanding of the code and accurate prediction ability. At the same time, the introduction of function pointers and patch code also increases the consumption of RAM space, which is undoubtedly a significant challenge for resource-limited embedded systems.

[0005] Another solution is to externalize the interrupt vector table and execute the patch code by monitoring exceptions through peripheral interrupts. This solution can cover the handling of most hardware exception problems, but it requires the hardware module to work in an interrupt mode and may be unable to handle software vulnerabilities effectively. Similarly, the introduction of the interrupt vector table and patch code also increases the burden on RAM space. Summary of the Invention

[0006] The embodiments of the present application provide a method, apparatus, and storage medium for patching read-only code, which can solve the problem of excessive RAM space occupation in the existing patching methods. The technical solutions are as follows:

[0007] In a first aspect, the embodiments of the present application provide a method for patching read-only code, the method comprising:

[0008] Monitoring the system bus, and when a read / write request from the CPU is detected on the system bus, parsing the read / write address of the read / write request;

[0009] Querying in a patch pool for a patch data item that matches the read / write address; wherein, the patch pool is pre-configured with a plurality of patch data items, and the patch data item includes: a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table;

[0010] If a target patch data item with a patch address identical to the read / write address is queried, determining whether the patch status value of the target patch data item indicates a valid state;

[0011] If so, determining whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item;

[0012] If so, obtaining the patch type value of the target patch data item;

[0013] If the patch type value of the target patch data item is a first preset value, replacing the target data indicated by the read / write request with the patch data;

[0014] If the patch type value of the target patch data item is a second preset value, replacing the target data indicated by the read / write request with a CPU exception instruction, the CPU exception instruction being used to instruct the CPU to enter an interrupt handling process according to the interrupt vector table of the target patch data item, and obtaining corresponding patch data in the interrupt handling process;

[0015] Determining whether the target patch data item has expired according to the patch validity period, and if so, setting the patch status value to an invalid state and deleting the patch data from the patch pool, otherwise remaining in a valid state.

[0016] In a second aspect, the embodiments of the present application provide a patching device for read-only code, the device comprising:

[0017] A monitoring unit, configured to monitor the system bus, and when a read / write request from the CPU is detected on the system bus, parse the read / write address of the read / write request;

[0018] A query unit for querying a patch data item matching the read / write address in a patch pool; wherein, the patch pool is pre-configured with multiple patch data items, and the patch data item includes: a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table;

[0019] A judgment unit for, if a target patch data item with the same patch address as the read / write address is queried, judging whether the patch status value of the target patch data item indicates a valid state; if so, judging whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; if so, obtaining the patch type value of the target patch data item; if the patch type value of the target patch data item is a first preset value, replacing the target data indicated by the read / write request with the patch data; if the patch type value of the target patch data item is a second preset value, replacing the target data indicated by the read / write request with a CPU exception instruction, and the CPU exception instruction is used to instruct the CPU to enter an interrupt handling process according to the interrupt vector table of the target patch data item, and obtaining corresponding patch data in the interrupt handling process;

[0020] An update unit for judging whether the target patch data item is invalid according to the patch validity period, and if so, setting the patch status value to an invalid state and deleting the patch data from the patch pool, otherwise remaining in a valid state.

[0021] In a third aspect, an embodiment of the present application provides a computer storage medium storing multiple instructions, and the instructions are adapted to be loaded and executed by a processor to perform the above method steps.

[0022] In a fourth aspect, an embodiment of the present application provides a patch repair device for read-only code, which may include: a processor and a memory; wherein, the memory stores a computer program, and the computer program is adapted to be loaded and executed by the processor to perform the above method steps.

[0023] The beneficial effects brought by the technical solutions provided by some embodiments of the present application at least include:

[0024] By monitoring read and write requests on the system bus, full bus patch coverage for any code / data is achieved. The patch repair device pre - sets a patch pool containing various information. When a read / write request for a specific address is detected, it can quickly query and match the corresponding patch data item. If the match is successful and the patch is valid, the target data is replaced according to the patch type or the CPU exception instruction is triggered to enter the interrupt handling process to obtain the patch. This method is general and flexible, supports non - discriminatory full - function patches, can handle various code / data errors, and greatly reduces the risk of chip scrapping or re - programming due to ROM code anomalies. Through means such as bus replacement and exception triggering, effective repair of read - only code is achieved, with significant economic effects, improved production efficiency, and reduced product costs. Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following - described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 is a schematic diagram of the system architecture of the chip provided by the embodiment of the present application;

[0027] Figure 2 is a schematic diagram of the flow of the patch repair method for read - only code provided by the embodiment of the present application;

[0028] Figure 3 is a schematic diagram of the structure of a patch repair device for read - only code provided by the present application;

[0029] Figure 4 is a schematic diagram of the structure of a terminal device provided by the present application. Detailed Embodiments

[0030] To make the purpose, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail in conjunction with the drawings.

[0031] As Figure 1 shown, the system architecture of the chip may include: a CPU, a code repair device, a read - only memory, an external memory, and an electronic fuse. The above - mentioned components are connected through the system bus. The operation method of this system architecture includes: after the CPU is powered on, it starts from the read - only memory indicated by the 0 address and directly reads and runs the program code in the read - only memory; or starts the bootloader and loads and runs the program code in the external memory through the bootloader.

[0032] Among them, the read-only memory can be OTP or ROM, and the external memory can be EEPROM, SPI Flash, etc. The code repair device can be a module inside the chip.

[0033] It should be understood that Figure 1 the number of each component in

[0034] is only illustrative. According to the implementation requirements, it can be any number. Figure 2 Next, the patch repair method for read-only code provided by the embodiments of the present application will be introduced in detail. Among them, the patch repair device for read-only code in the embodiments of the present application can be Figure 1 the code repair device shown in

[0035] Please refer to Figure 2 which is a schematic flowchart of a patch repair method for read-only code provided by the embodiments of the present application. As Figure 2 shown, the method of the embodiments of the present application may include the following steps:

[0036] S201. Monitor the system bus. When a read / write request from the CPU is detected on the system bus, parse the read / write address of the read / write request.

[0037] Among them, the patch repair device continuously monitors the signal transmission on the system bus in real time through the integrated monitoring unit. When a read / write request from the CPU is detected, the monitoring module immediately captures the request and enters the parsing stage. In the parsing stage, the device first identifies the type of the request (read or write), and then extracts the key information in the request, especially the read / write address. The read / write address is the identifier of the memory location that the CPU hopes to access or modify. The device obtains this key information by parsing the address field in the request packet or instruction. To ensure the legality and accuracy of the address, the device may also perform an address range check to prevent out-of-bounds or illegal access.

[0038] S202. Query the patch data item that matches the read / write address in the patch pool; among them, the patch pool is pre-configured with multiple patch data items, and the patch data item includes: patch status value, code data type value, patch validity period value, patch type value, patch address, patch data, and interrupt vector table.

[0039] Among them, the patch pool is a data structure maintained inside the device for storing and managing multiple patch data items. Each patch data item contains a series of attributes:

[0040] Patch status value: indicates whether the patch data is in a valid state or an invalid state. The valid state means that the patch can be applied, and the invalid state means that the patch should be ignored.

[0041] Code data type value: Indicates that the patch data is data, code, or contains both data and code. This helps the device determine how to apply the patch and its target.

[0042] Patch validity period: Represents the validity period of the patch data, which is a timestamp or date range used to determine whether the patch is still within the available period.

[0043] Patch type value: Includes replacement methods, etc., indicating how the patch should be applied, such as directly replacing data or triggering an interrupt handling process.

[0044] Patch address: Represents the storage address of the patch data, which is the location identifier of the patch data in memory.

[0045] Patch data: Is the actual patch content indicated by the patch address, used to replace or modify the original data.

[0046] When the device obtains the read / write address, it uses an efficient search algorithm (such as hash search, binary search tree search, etc.) to search for the patch data item that matches the read / write address in the patch pool. The matching criterion is that the patch address is exactly the same as the read / write address. If a matching patch data item is found, the device will use it as the target patch data item for subsequent processing.

[0047] Furthermore, to improve storage efficiency and access speed, each patch data item in the patch pool is compressed. Before adding the patch data item to the patch pool, the device uses an efficient compression algorithm (such as gzip, bzip2, etc.) to compress the data.

[0048] The compressed data item includes the compressed patch data, patch status value, code data type value, patch validity period, patch type value (including replacement methods, etc.), and the decompressed patch address. These information are organized into a structured data format for easy subsequent query and application.

[0049] Furthermore, in some embodiments of the present application,

[0050] The length of the patch status value is set to 1 bit (bit). Using 1 bit can represent two states (such as valid or invalid), which is concise and efficient.

[0051] The length of the data code type value is set to 2 bits. 2 bits can represent 4 different data types (such as data, code, contains both data and code, or other reserved types), meeting the basic type differentiation requirements.

[0052] The length of the patch validity period is set to 1 bit. Under this setting, the patch validity period can be simplified into two representations (such as a simplified representation of being valid for N times or permanently valid, or a certain flag within a specific validity period, and the actual meaning needs to be defined in combination with the specific implementation). If a more complex representation is required, it may need to be extended through other mechanisms or fields.

[0053] The length of the patch type value is set to 3 bits. 3 bits can represent 8 different patch types, such as replacement, modification, addition, deletion, etc., as well as possible combinations or reserved types, providing flexibility for the application of patches.

[0054] The length of the patch address is equal to the length of the address bus. This means that the patch address can accurately represent any address location in the system memory, ensuring that the patch can be correctly applied to the target location.

[0055] S203. If a target patch data item with the same patch address and read / write address is found, determine whether the patch status value of the target patch data item indicates a valid status.

[0056] Among them, after the device obtains the target patch data item, it will first check its patch status value. By reading the patch status value and comparing it with the valid status value defined internally, it is determined whether the patch is in a valid status. If the patch status value indicates valid, the device will continue with subsequent processing. If the patch status value indicates invalid, the device will ignore the patch data item and not perform any modification or interruption processing.

[0057] Furthermore, in some embodiments of the present application, in the patch repair process, the patch repair device will query the patch pool to check if there is a patch address that matches the current read / write request address of the CPU. The patch pool is a collection that stores multiple patch data items, and each patch data item contains various information about the patch, such as patch status, data code type, patch validity period, patch type, and patch address, etc. If the patch repair device finds a target patch data item in the patch pool with the same patch address and read / write request address, then it will process the patch data item according to the established patch repair process, such as applying the patch, updating the data, etc. If no matching patch data item is found, it means that there is no corresponding patch to be applied to the memory address accessed by the current read / write request. In the case of not finding a matching patch data item, the patch repair device will no longer intervene in the read / write request but directly instruct the CPU to execute the target data operation indicated by the read / write request. This means that the CPU will read data from or write data to the specified memory address according to the normal memory access process.

[0058] S204. If so, determine whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item.

[0059] Among them, after confirming that the patch status is valid, the device further verifies whether the data type of the read / write data indicated by the read / write request matches the code data type value in the target patch data item. The device determines whether the data types match by comparing the data type identifiers in the read / write request or performing type compatibility checks. If the data types do not match, the device ignores the patch data item. If the data types match, the device continues with subsequent processing.

[0060] S205. If it is yes, obtain the patch type value of the target patch data item.

[0061] Among them, after the data types match, the device obtains the patch type value in the target patch data item. The patch type value indicates how the patch should be applied. The device determines what processing strategy should be taken to apply the patch by reading the patch type value. For example, if the patch type value indicates the replacement method, the device will prepare to replace the original data.

[0062] S206. If the patch type value of the target patch data item is the first preset value, replace the target data indicated by the read / write request with the patch data.

[0063] S207. If the patch type value of the target patch data item is the second preset value, replace the target data indicated by the read / write request with a CPU exception instruction. The CPU exception instruction is used to instruct the CPU to enter the interrupt processing flow according to the interrupt vector table of the target patch data item, and obtain the corresponding patch data in the interrupt processing flow.

[0064] Among them, according to the different patch type values, the device will adopt different processing strategies to apply the patch:

[0065] Replacement method: If the patch type value indicates direct replacement, the device will replace the target data indicated by the read / write request with the patch data. This involves writing the patch data (stored at the location indicated by the patch address) to the memory location being accessed by the CPU. During the replacement process, the device may perform data integrity checks or back up the original data to prevent data loss or corruption.

[0066] Trigger the interrupt processing flow: The device will replace the target data indicated by the read / write request with a CPU exception instruction. The exception instruction is a special instruction that, when executed by the CPU, triggers the interrupt processing flow. The interrupt processing flow will jump to the corresponding interrupt service routine according to the interrupt vector table in the patch data item. In the interrupt service routine, the device will obtain and apply the corresponding patch data to complete the process of applying the patch.

[0067] Further, during the patch repair process, when it is necessary to trigger the CPU exception handling process, the CPU exception instruction is the trap instruction or the break instruction.

[0068] The trap instruction, also known as the self-trap instruction or the supervisor call instruction, is a special instruction in a computer operating system. It is used for a process running in user mode to call the operating system kernel program. That is, when the running user process or system utility process needs to request the operating system kernel to serve it, it can execute the trap instruction to trigger a special exception. The trap instruction is commonly used in scenarios such as system calls and program debugging. For example, during program debugging, the trap instruction can be used to set breakpoints so that the program pauses execution when it reaches a specific location and enters the debugging mode. In the patch repair process, the trap instruction can be used to trigger the interrupt handling process, causing the CPU to jump to the corresponding interrupt service program. In the interrupt service program, the patch repair device can obtain and apply the corresponding patch data to complete the patch repair work.

[0069] The break instruction is usually used to terminate the execution of the current loop or conditional statement in programming. However, in the context of CPU exception handling, the break instruction can be regarded as a generalized exception triggering mechanism for interrupting the normal execution flow of a program under specific conditions. Although the direct application of the break instruction in programming is different from that of the trap instruction, in some exception handling mechanisms, the break instruction can be combined with the exception handling process through specific implementation methods. For example, in some embedded systems or specific processor architectures, the break instruction may be designed to be able to trigger a specific exception handling routine. In a specific patch repair scenario, if the break instruction is designed to be able to trigger the exception handling process, it can be used to interrupt the execution of the program when a specific error or exception situation is detected and guide the CPU into the exception handling mode. In the exception handling mode, the patch repair device can perform the corresponding repair operations.

[0070] S208. Determine whether the target patch data item has expired according to the patch validity period. If so, set the patch status value to the expired state and delete the patch data from the patch pool; otherwise, keep it in the valid state.

[0071] Among them, after applying the patch, the device will determine whether the target patch data item has expired according to the patch validity period value. The device judges whether the patch is still within the validity period by comparing the current time with the patch validity period expiration time. If the patch has expired, the device will set the patch status value to the invalid state and delete the patch data item from the patch pool to ensure the accuracy and effectiveness of the patch pool. If the patch is still within the validity period, the device will keep the patch status value in the valid state and continue to monitor and process subsequent read and write requests.

[0072] In some embodiments of the present application, the patch validity period is now represented as valid for N times or permanently valid. Specifically:

[0073] Valid for N times: N is an integer greater than 1, indicating that the patch data item can be applied N times. Each time the patch is applied, the device records the usage count of the patch. When the usage count reaches N, the patch is considered invalid. Permanently valid: The patch data item is marked as permanently valid, meaning there is no limit on the number of times it can be used and it can be applied an unlimited number of times.

[0074] For a patch that is valid for N times, the device stores a usage count counter in the patch data item. Each time the patch is applied, the counter is incremented. The device checks whether the value of the counter is less than or equal to N. If so, the patch is still valid; if not, the patch is considered invalid, the device updates the patch status value accordingly, and deletes the patch data item from the patch pool.

[0075] For a permanently valid patch, the device does not need to store a usage count counter in the patch data item. The device directly determines whether the patch is permanently valid. If so, the patch is always considered valid; if not (i.e., the patch has a specific validity period limit but is not permanently valid), the original validity period judgment logic is used for processing.

[0076] Furthermore, in some embodiments of the present application, the present application adds a step of performing integrity verification on the target patch data item, and requires that the verification result passes. This step is a key link to ensure that the patch data item has not been tampered with or damaged during storage, transmission, and application.

[0077] The object of verification is the target patch data item obtained from the patch pool. This data item contains various information about the patch, such as the patch status value, data code type value, patch validity period, patch type value, and patch address, etc. Integrity verification usually uses mathematical operation methods, such as hash algorithms (such as MD5, SHA-1, etc.) or checksum algorithms. These algorithms can perform unique mathematical transformations on the content of the patch data item to generate a fixed verification value or hash value. Before the patch data item is stored or transmitted, its verification value or hash value is calculated first and saved or transmitted together with the patch data item. Before the patch data item is applied, its verification value or hash value is recalculated and compared with the previously saved verification value or hash value. If the recalculated verification value or hash value matches the previously saved verification value or hash value, it means that the patch data item has not been tampered with or damaged during storage, transmission, and application, and the verification result passes. If the verification result does not pass, it means that there may be a problem with the patch data item. The patch repair device will not apply this patch data item and may trigger corresponding error handling processes, such as recording error logs, notifying the administrator, etc.

[0078] The present application has the following beneficial effects:

[0079] The technical solution can monitor read and write requests on the system bus, respond and process access to a specific address in real time, thereby realizing dynamic patch repair of code in a read-only storage medium. This avoids the limitation that traditional read-only storage media cannot modify code, and greatly reduces the economic losses caused by code errors or vulnerabilities. It supports patching for any code / data, achieving a non-discriminatory full-function patch. This means that regardless of the location of the code or data in the memory, it can be repaired by the patch repair device, greatly enhancing the coverage and applicability of the patch. Due to the full-function patch ability of the patch repair device, it can handle various types of code or data errors, including but not limited to logic errors, data corruption, functional defects, etc. This powerful function enables most bugs to be repaired in a timely and effective manner, improving the stability and reliability of the system. The technical solution realizes read-only code patching by means of replacing code / data through the bus and triggering exceptions such as traps / breakpoints. This general and flexible method greatly reduces the risk that ROM code exceptions require reworking the chip or discarding the chip and re-burning. Developers do not need to worry about the entire batch of chips being scrapped due to code errors, thus saving time and costs. By avoiding the costs of chip scrapping and re-burning, and reducing production stagnation and maintenance costs caused by code errors, this technical solution has a huge economic effect. It can not only improve production efficiency, but also reduce the overall cost of products and enhance the competitiveness of enterprises.

[0080] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the method embodiment of the present application.

[0081] Please refer to Figure 3 , which shows a schematic structural diagram of a read-only code patch repair device provided by an exemplary embodiment of the present application, hereinafter referred to as device 3. Device 3 includes: a monitoring unit 301, a query unit 302, a judgment unit 303, and an update unit 304.

[0082] The monitoring unit 301 is used to monitor the system bus and parse the read / write address of the read / write request when a read / write request from the CPU is detected on the system bus;

[0083] The query unit 302 is used to query a patch data item matching the read / write address in the patch pool; wherein, the patch pool is pre-configured with a plurality of patch data items, and the patch data item includes: a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table;

[0084] A determination unit 303 is configured to, if a target patch data item with a patch address identical to the read / write address is found, determine whether the patch status value of the target patch data item indicates a valid status; if so, determine whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; if so, obtain the patch type value of the target patch data item; if the patch type value of the target patch data item is a first preset value, replace the target data indicated by the read / write request with the patch data; if the patch type value of the target patch data item is a second preset value, replace the target data indicated by the read / write request with a CPU exception instruction, where the CPU exception instruction is used to instruct the CPU to enter an interrupt handling process according to the interrupt vector table of the target patch data item, and obtain the corresponding patch data in the interrupt handling process.

[0085] An update unit 304 is configured to determine whether the target patch data item has expired according to the patch validity period. If so, set the patch status value to an invalid status and delete the patch data from the patch pool; otherwise, keep it in a valid status.

[0086] In one or more possible embodiments, compression processing is performed on each patch data entry in the patch pool.

[0087] In one or more possible embodiments, the patch validity period indicates valid for N times or permanently valid, where N is an integer greater than 1.

[0088] In one or more possible embodiments, the length of the patch status value in the patch data item is 1 bit, the length of the data code type value is 2 bits, the length of the patch validity period is 1 bit, the length of the patch type value is 3 bits, and the length of the patch address is equal to the length of the address bus.

[0089] In one or more possible embodiments, the CPU exception instruction is a trap instruction or a break instruction.

[0090] In one or more possible embodiments, it further includes:

[0091] A verification unit is configured to perform integrity verification on the target patch data item, and the verification result is passed.

[0092] In one or more possible embodiments, the determination unit 303 is further configured to:

[0093] If no target patch data item with a patch address identical to the read / write address is found, instruct the CPU to directly execute the target data indicated by the read / write request.

[0094] It should be noted that when the device 3 provided in the above embodiments executes the patch repair method for read-only code, only the division of the above-mentioned functional modules is used for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the patch repair device for read-only code provided in the above embodiments and the embodiments of the patch repair method for read-only code belong to the same concept. The implementation process is detailed in the method embodiments and will not be repeated here.

[0095] The serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0096] The embodiments of the present application also provide a computer storage medium, which can store multiple instructions. The instructions are suitable for being loaded and executed by a processor to perform the method steps of the embodiments as described above. Figure 2 For the specific execution process, reference can be made to Figure 2 the specific description of the embodiments shown, and details will not be repeated here.

[0097] The present application also provides a computer program product, which stores at least one instruction. The at least one instruction is loaded and executed by the processor to implement the patch repair method for read-only code as described in each of the above embodiments.

[0098] Please refer to Figure 4 , which is a schematic structural diagram of a device provided by an embodiment of the present application. As Figure 4 shown, the device 400 may include: at least one processor 401, at least one communication interface 403, a memory 404, and at least one communication bus 402.

[0099] Among them, the communication bus 402 is used to realize the connection and communication between these components.

[0100] Among them, the communication interface 403 may optionally include a standard wired interface and a wireless interface, and is used to communicate with the CPU inside the chip through the system bus.

[0101] Among them, the processor 401 may include one or more processing cores. The processor 401 connects various parts within the entire device 400 through various interfaces and lines. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 404, and by calling the data stored in the memory 404, it executes various functions of the device 400 and processes data. Optionally, the processor 401 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 401 may integrate a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, application programs, etc.; the GPU is responsible for the rendering and drawing of the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 401 and may be implemented separately by a single chip.

[0102] Among them, the memory 404 may include random access memory (RAM) and may also include read-only memory. Optionally, the memory 404 includes a non-transitory computer-readable storage medium. The memory 404 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 404 may include a program storage area and a data storage area. Among them, the program storage area may store instructions for implementing the operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store the data involved in the above-mentioned various method embodiments. Optionally, the memory 404 may also be at least one storage device located far from the aforementioned processor 401. As Figure 4 shown, the memory 404, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0103] In Figure 4 the device 400 shown, the processor 401 may be used to call the application programs stored in the memory 404 and specifically execute as Figure 2The method shown, for the specific process, reference may be made to Figure 2 as shown, which will not be elaborated here.

[0104] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it may include the processes of the embodiments of the above various methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, or a random access memory, etc.

[0105] The foregoing disclosure is only for the better embodiments of the present application. Of course, the scope of the rights of the present application cannot be limited thereby. Therefore, equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A read-only code patch repair method, characterized in that: include: Monitoring a system bus, and when a read / write request from a CPU is detected on the system bus, parsing a read / write address of the read / write request; Querying a patch data item matching the read / write address in a patch pool; wherein the patch pool is pre-configured with a plurality of patch data items, the patch data items including: a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table; If a target patch data item with the same patch address as the read / write address is found, determining whether the patch status value of the target patch data item indicates a valid status; If yes, determining whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; If yes, obtain the patch type value of the target patch data item; If the patch type value of the target patch data item is a first preset value, replacing the target data indicated by the read / write request with the patch data; If the patch type value of the target patch data item is a second preset value, the target data indicated by the read / write request is replaced with a CPU exception instruction, wherein the CPU exception instruction is used to instruct the CPU to enter an interrupt processing flow according to an interrupt vector table of the target patch data item, and obtain corresponding patch data in the interrupt processing flow; Determine whether the target patch data item is invalid according to the patch validity period. If yes, set the patch status value to invalid state and delete the patch data from the patch pool. Otherwise, keep it in valid state.

2. The method according to claim 1, characterized in that Each patch data row item in the patch pool is compressed.

3. The method according to claim 1 or 2, characterized in that: The patch validity period indicates that the patch is valid for N times or permanently, where N is an integer greater than 1.

4. The method according to claim 3, characterized in that The length of the patch status value in the patch data item is 1 bit, the length of the data code type value is 2 bits, the length of the patch validity period is 1 bit, the length of the patch type value is 3 bits, and the length of the patch address is equal to the length of the address bus.

5. The method according to claim 1, 2 or 4, characterized in that: The CPU exception instruction is a trap instruction or a break instruction.

6. The method according to claim 5, characterized in that Also includes: An integrity check is performed on the target patch data item, and the check result is passed.

7. The method according to claim 6, characterized in that Also includes: If no target patch data item with the same patch address as the read / write address is found, the CPU is instructed to directly execute the target data indicated by the read / write request.

8. A read-only code patch repair device, characterized in that: include: A monitoring unit, used for monitoring a system bus, and when a read / write request from a CPU is detected on the system bus, parsing a read / write address of the read / write request; A query unit, used to query a patch pool for a patch data item matching the read / write address; wherein the patch pool is pre-configured with a plurality of patch data items, the patch data items including: a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table; a judging unit configured to judge whether the patch status value of the target patch data item indicates a valid status if a target patch data item whose patch address is the same as the read / write address is queried; if yes, judge whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; if yes, obtain the patch type value of the target patch data item; if the patch type value of the target patch data item is a first preset value, replace the target data indicated by the read / write request with the patch data; if the patch type value of the target patch data item is a second preset value, replace the target data indicated by the read / write request with a CPU exception instruction, the CPU exception instruction being used to instruct the CPU to enter an interrupt processing flow according to the interrupt vector table of the target patch data item, and obtain the corresponding patch data in the interrupt processing flow; An updating unit is used to determine whether the target patch data item is invalid according to the patch validity period. If yes, the patch status value is set to an invalid state and the patch data is deleted from the patch pool; otherwise, it is kept in a valid state.

9. A computer storage medium, characterized in that The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 7.

10. A read-only code patch repair device, characterized in that: include: A processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the method steps as claimed in any one of claims 1 to 7.

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